Vref Status And Control Register (Vref_Sc) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Table of Contents

26.2.2 VREF Status and Control Register (VREF_SC)

This register contains the control bits used to enable the internal voltage reference and to

select the buffer mode to be used.

Address: 4007_4000h base + 1h offset = 4007_4001h

Internal Voltage Reference enable

This bit is used to enable the bandgap reference within the Voltage Reference module.

NOTE: After the VREF is enabled, turning off the clock to the VREF module via the corresponding clock

The module is disabled.

The module is enabled.

Regulator enable

This bit is used to enable the internal 1.75 V regulator to produce a constant internal voltage supply in

order to reduce the sensitivity to external supply noise and variation. If it is desired to keep the regulator

enabled in very low power modes, refer to the Chip Configuration details for a description on how this can

be achieved.

This bit should be written to 1 to achieve the performance stated in the data sheet.

Internal 1.75 V regulator is disabled.

Internal 1.75 V regulator is enabled.

Second order curvature compensation enable

This bit should be written to 1 to achieve the performance stated in the data sheet.

This field is reserved.

This read-only field is reserved and always has the value 0.

This field is reserved.

This read-only field is reserved and always has the value 0.

Internal Voltage Reference stable

This bit indicates that the bandgap reference within the Voltage Reference module has completed its

startup and stabilization.

NOTE: This bit is valid only when the chop oscillator is not being used.

Freescale Semiconductor, Inc.

VREF_SC field descriptions

gate register will not disable the VREF. VREF must be disabled via this VREFEN bit.

Table continues on the next page...

KL27 Sub-Family Reference Manual , Rev. 5, 01/2016

Chapter 26 Voltage Reference (VREFV1)