Pit Upper Lifetime Timer Register (Pit_Ltmr64H); Pit Lower Lifetime Timer Register (Pit_Ltmr64L) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

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Allows the timers to be stopped when the device enters the Debug mode.

Timers continue to run in Debug mode.

Timers are stopped in Debug mode.

30.4.2 PIT Upper Lifetime Timer Register (PIT_LTMR64H)

This register is intended for applications that chain timer 0 and timer 1 to build a 64-bit

Access: User read only

Address: 4003_7000h base + E0h offset = 4003_70E0h

Life Timer value

Shows the timer value of timer 1. If this register is read at a time t1, LTMR64L shows the value of timer 0

This register is intended for applications that chain timer 0 and timer 1 to build a 64-bit

To use LTMR64H and LTMR64L, timer 0 and timer 1 need to be chained. To obtain the

correct value, first read LTMR64H and then LTMR64L. LTMR64H will have the value

of CVAL1 at the time of the first access, LTMR64L will have the value of CVAL0 at the

time of the first access, therefore the application does not need to worry about carry-over

effects of the running counter.

Access: User read only

Freescale Semiconductor, Inc.

PIT_MCR field descriptions (continued)

PIT_LTMR64H field descriptions

KL27 Sub-Family Reference Manual , Rev. 5, 01/2016

Chapter 30 Periodic Interrupt Timer (PIT)