Rxedgif Description - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Table of Contents

System level interrupt sources

RXEDGIF description

interrupt because of its complexity of operation. Any of the UART interrupt requests

listed in the table can be used to bring the CPU out of Wait mode.

Interrupt Source

38.7.1 RXEDGIF description

S2[RXEDGIF] is set when an active edge is detected on the RxD pin. Therefore, the

active edge can be detected only when in two wire mode. A RXEDGIF interrupt is

generated only when S2[RXEDGIF] is set. If RXEDGIE is not enabled before

S2[RXEDGIF] is set, an interrupt is not generated.

38.7.1.1 RxD edge detect sensitivity

Edge sensitivity can be software programmed to be either falling or rising. The polarity

of the edge sensitivity is selected using S2[RXINV]. To detect the falling edge,

S2[RXINV] is programmed to 0. To detect the rising edge, S2[RXINV] is programmed

Synchronizing logic is used prior to detect edges. Prior to detecting an edge, the receive

data on RxD input must be at the deasserted logic level. A falling edge is detected when

the RxD input signal is seen as a logic 1 (the deasserted level) during one module clock

also outlines additional details regarding the RXEDGIF

Table 38-14. UART interrupt sources

KL27 Sub-Family Reference Manual , Rev. 5, 01/2016

Local enable

Freescale Semiconductor, Inc.