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Functional description
The frame sync signal is used to indicate the start of each frame. A valid frame sync
requires a rising edge (if active high) or falling edge (if active low) to be detected and the
transmitter or receiver cannot be busy with a previous frame. A valid frame sync is also
ignored (slave mode) or not generated (master mode) for the first four bit clock cycles
after enabling the transmitter or receiver.
The transmitter and receiver frame sync can be configured independently with any of the
following options:
• Externally generated or internally generated
• Active high or active low
• Assert with the first bit in frame or asserts one bit early
• Assert for a duration between 1 bit clock and the first word length
• Frame length from 1 to 2 words per frame
• Word length to support 8 to 32 bits per word
• First word length and remaining word lengths can be configured separately
• Words can be configured to transmit/receive MSB first or LSB first
These configuration options cannot be changed after the SAI transmitter or receiver is
enabled.
40.5.5 Data FIFO
Each transmit and receive channel includes a FIFO of size 1 × 32-bit. The FIFO data is
accessed using the SAI Transmit/Receive Data Registers.
40.5.5.1 Data alignment
Data in the FIFO can be aligned anywhere within the 32-bit wide register through the use
of the First Bit Shifted configuration field, which selects the bit index (between 31 and 0)
of the first bit shifted.
Examples of supported data alignment and the required First Bit Shifted configuration are
illustrated in
Figure 40-3
configurations.
816
for LSB First configurations and
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Figure 40-4
for MSB First
Freescale Semiconductor, Inc.
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