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Memory Map and Registers
39.2.4 Modes of operation
The FlexIO module supports the chip modes described in the following table.
Table 39-2. Chip modes supported by the FlexIO module
Chip mode
Run
Stop/Wait
Low Leakage Stop
Debug
39.2.5 FlexIO Signal Descriptions
Signal
FXIO_Dn (n=0...7)
39.3
Memory Map and Registers
Absolute
address
(hex)
4005_F000
Version ID Register (FLEXIO_VERID)
4005_F004
Parameter Register (FLEXIO_PARAM)
4005_F008
FlexIO Control Register (FLEXIO_CTRL)
4005_F010
Shifter Status Register (FLEXIO_SHIFTSTAT)
4005_F014
Shifter Error Register (FLEXIO_SHIFTERR)
4005_F018
Timer Status Register (FLEXIO_TIMSTAT)
4005_F020
Shifter Status Interrupt Enable (FLEXIO_SHIFTSIEN)
4005_F024
Shifter Error Interrupt Enable (FLEXIO_SHIFTEIEN)
4005_F028
Timer Interrupt Enable Register (FLEXIO_TIMIEN)
4005_F030
Shifter Status DMA Enable (FLEXIO_SHIFTSDEN)
4005_F080
Shifter Control N Register (FLEXIO_SHIFTCTL0)
748
FlexIO Operation
Normal operation
Can continue operating provided the Doze Enable bit (CTRL[DOZEN]) is set and
the FlexIO is using an external or internal clock source which remains operating
during stop/wait modes.
The Doze Enable (CTRL[DOZEN]) bit is ignored and the FlexIO will wait for all
Timers to complete any pending operation before acknowledging low leakage
mode entry.
Can continue operating provided the Debug Enable bit (CTRL[DBGE]) is set.
Description
Bidirectional FlexIO Shifter and Timer
pin inputs/outputs
FLEXIO memory map
Register name
Table continues on the next page...
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
I/O
I/O
Width
Access
Reset value
(in bits)
32
R
0100_0000h
32
R
See section
32
R/W
0000_0000h
32
w1c
0000_0000h
32
w1c
0000_0000h
32
w1c
0000_0000h
32
R/W
0000_0000h
32
R/W
0000_0000h
32
R/W
0000_0000h
32
R/W
0000_0000h
32
R/W
0000_0000h
Freescale Semiconductor, Inc.
Section/
page
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39.3.11/
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