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33.5.9 Status register (USBx_STAT)
Reports the transaction status within the USB module. When the processor's interrupt
controller has received a TOKDNE, interrupt the Status Register must be read to
determine the status of the previous endpoint communication. The data in the status
register is valid when TOKDNE interrupt is asserted. The Status register is actually a
read window into a status FIFO maintained by the USB module. When the USB module
uses a BD, it updates the Status register. If another USB transaction is performed before
the TOKDNE interrupt is serviced, the USB module stores the status of the next
transaction in the STAT FIFO. Thus STAT is actually a four byte FIFO that allows the
processor core to process one transaction while the SIE is processing the next transaction.
Clearing the TOKDNE bit in the ISTAT register causes the SIE to update STAT with the
contents of the next STAT value. If the data in the STAT holding register is valid, the
SIE immediately reasserts to TOKDNE interrupt.
Address: 4007_2000h base + 90h offset = 4007_2090h
Bit
7
Read
Write
Reset
0
Field
7–4
This four-bit field encodes the endpoint address that received or transmitted the previous token. This
ENDP
allows the processor core to determine the BDT entry that was updated by the last USB transaction.
3
Transmit Indicator
TX
0
The most recent transaction was a receive operation.
1
The most recent transaction was a transmit operation.
2
This bit is set if the last buffer descriptor updated was in the odd bank of the BDT.
ODD
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
Freescale Semiconductor, Inc.
6
5
ENDP
0
0
USBx_STAT field descriptions
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Chapter 33 Universal Serial Bus (USB) FS Subsystem
4
3
TX
ODD
0
0
Description
2
1
0
0
0
0
0
549
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