Mtb_Dwt Memory Map - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Memory map and register definition
43.3.1.14 Peripheral ID Register (MTB_PERIPHIDn)
These registers indicate the peripheral IDs. They are hardwired to specific values used
during the auto-discovery process by an external debug agent.
Address: F000_0000h base + FD0h offset + (4d × i), where i=0d to 7d
Bit 31 30 29 28 27 26
R
W
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
Reset
Field
PERIPHID PERIPHID
Peripheral ID4 is hardwired to 0x0000_0004; ID0 to 0x0000_0032; ID1 to 0x0000_00B9; ID2 to
0x0000_001B; and all the others to 0x0000_0000.
43.3.1.15 Component ID Register (MTB_COMPIDn)
These registers indicate the component IDs. They are hardwired to specific values used
during the auto-discovery process by an external debug agent.
Address: F000_0000h base + FF0h offset + (4d × i), where i=0d to 3d
Bit 31 30 29 28 27 26
R
W
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
Reset
Field
COMPID Component ID
Component ID0 is hardwired to 0x0000_000D; ID1 to 0x0000_0090; ID2 to 0x0000_0005; ID3 to
0x0000_00B1.

43.3.2 MTB_DWT Memory Map

The MTB_DWT programming model supports a very simplified subset of the v7M debug
architecture and follows the standard ARM DWT definition.
868
25 24 23 22 21 20 19 18
MTB_PERIPHIDn field descriptions
25 24 23 22 21 20 19 18
MTB_COMPIDn field descriptions
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
17 16 15 14 13 12 11 10
PERIPHID
Description
17 16 15 14 13 12 11 10
COMPID
Description
9 8 7 6 5 4 3 2
9 8 7 6 5 4 3 2
Freescale Semiconductor, Inc.
1 0
1 0