Interrupts; Chained Timers; Initialization And Application Information - NXP Semiconductors MKL27Z128VFM4 Reference Manual

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Timer enabled

Start value = p1

Figure 30-4. Dynamically setting a new load value

30.5.1.2 Debug mode

In Debug mode, the timers will be frozen based on MCR[FRZ]. This is intended to aid

software development, allowing the developer to halt the processor, investigate the

current state of the system, for example, the timer values, and then continue the

30.5.2 Interrupts

All the timers support interrupt generation. See the MCU specification for related vector

addresses and priorities.

Timer interrupts can be enabled by setting TCTRLn[TIE]. TFLGn[TIF] are set to 1 when

a timeout occurs on the associated timer, and are cleared to 0 by writing a 1 to the

corresponding TFLGn[TIF].

When a timer has chain mode enabled, it will only count after the previous timer has

expired. So if timer n-1 has counted down to 0, counter n will decrement the value by

one. This allows to chain some of the timers together to form a longer timer. The first

timer (timer 0) cannot be chained to any other timer.

30.6 Initialization and application information

In the example configuration:

• The PIT clock has a frequency of 50 MHz.

Value p2 set

KL27 Sub-Family Reference Manual , Rev. 5, 01/2016

Freescale Semiconductor, Inc.