Port Set Output Register (Gpiox_Psor); Port Clear Output Register (Gpiox_Pcor) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Memory map and register definition
Field
PDO Port Data Output
Register bits for unbonded pins return a undefined value when read.
0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output.

41.3.2 Port Set Output Register (GPIOx_PSOR)

This register configures whether to set the fields of the PDOR.
Address: Base address + 4h offset
Bit 31 30 29 28 27 26
R
W
0 0 0 0 0 0
Reset
Field
PTSO Port Set Output
Writing to this register will update the contents of the corresponding bit in the PDOR as follows:
0 Corresponding bit in PDORn does not change.
1 Corresponding bit in PDORn is set to logic 1.

41.3.3 Port Clear Output Register (GPIOx_PCOR)

This register configures whether to clear the fields of PDOR.
Address: Base address + 8h offset
Bit 31 30 29 28 27 26
R
W
0 0 0 0 0 0
Reset
Field
PTCO Port Clear Output
826
GPIOx_PDOR field descriptions
25 24 23 22 21 20 19 18
0 0 0 0 0 0 0 0
GPIOx_PSOR field descriptions
25 24 23 22 21 20 19 18
0 0 0 0 0 0 0 0
GPIOx_PCOR field descriptions
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Description
17 16 15 14 13 12 11 10
0
PTSO
0 0 0 0 0 0 0 0
Description
17 16 15 14 13 12 11 10
0
PTCO
0 0 0 0 0 0 0 0
Description
9 8 7 6 5 4 3 2
0 0 0 0 0 0 0 0
9 8 7 6 5 4 3 2
0 0 0 0 0 0 0 0
Freescale Semiconductor, Inc.
1 0
0 0
1 0
0 0