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Table 39-9. SPI Slave (CPHA=1) Configuration (continued)
Register
TIMCTLn
SHIFTBUFn
SHIFTBUF(n+1)
39.5.5 I2C Master
I2C master mode can be supported using two Timers, two Shifters and two Pins. One
timer is used to generate the SCL output and one timer is used to control the shifters. The
two shifters are used to transmit and receive for every word, when receiving the
transmitter must transmit 0xFF to tristate the output. FlexIO inserts a stop bit after every
word to generate/verify the ACK/NACK. FlexIO waits for the first write to the transmit
data buffer before enabling SCL generation. Data transfers can be supported using the
DMA controller and the shifter error flag will set on transmit underrun or receive
overflow.
The first timer generates the bit clock for the entire packet (START to Repeated START/
STOP), so the compare register needs to be programmed with the total number of clock
edges in the packet (minus one). The timer supports clock stretching using the reset
counter when pin equal to output (although this increases both the clock high and clock
low periods by at least 1 FlexIO clock cycle each). The second timer uses the SCL input
pin to control the transmit/receive shift registers, this enforces an SDA data hold time by
an extra 2 FlexIO clock cycles.
Both the transmit and receive shifters need to be serviced for each word in the transfer,
the transmit shifter must transmit 0xFF when receiving and the receive shifter returns the
data actually present on the SDA pin. The transmit shifter will load 1 additional word on
the last falling edge of SCL pin, this word should be 0x00 if generating a STOP condition
or 0xFF if generating a repeated START condition. During the last word of a master-
receiver transfer, the transmit SSTOP bit should be set by software to generate a NACK.
Freescale Semiconductor, Inc.
0x06C0_0203
Data to transmit
Data to receive
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Value
Configure 16-bit counter using Pin 2
input (shift clock), with Pin 3 input (slave
SHIFTBUF, use the Shifter Status Flag
to indicate when data can be written
using interrupt or DMA request. Can
support MSB first transfer by writing to
SHIFTBUFBYS, use the Shifter Status
Flag to indicate when data can be read
using interrupt or DMA request. Can
support MSB first transfer by reading
from SHIFTBUFBIS register instead.
Chapter 39 FlexIO
Comments
select) as the inverted trigger.
Transmit data can be written to
SHIFTBUFBBS register instead.
Received data can be read from
779
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