Destination Address Register (Dma_Darn) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

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Memory Map/Register Definition

Each SAR contains the byte address used by the DMA controller to read data. The SARn is typically

aligned on a 0-modulo-ssize boundary—that is, on the natural alignment of the source data.

Restriction: Bits 31-20 of this register must be written with one of only several allowed values. Each of

21.3.2 Destination Address Register (DMA_DARn)

For this register:

• Only 32-bit writes are allowed. 16-bit and 8-bit writes

result in a bus error.

• Only several values are allowed to be written to bits 31-20

of this register, see the value list in the field description. A

write of any other value to these bits causes a configuration

error when the channel starts to execute. For more

information about the configuration error, see the

description of the

Address: 4000_8000h base + 104h offset + (16d × i), where i=0d to 3d

Each DAR contains the byte address used by the DMA controller to write data. The DARn is typically

aligned on a 0-modulo-dsize boundary—that is, on the natural alignment of the destination data.

Restriction: Bits 31-20 of this register must be written with one of only several allowed values. Each of

DMA_SARn field descriptions

these allowed values corresponds to a valid region of the device's memory map. The

allowed values are:

• 0x000x_xxxx

• 0x1FFx_xxxx

• 0x200x_xxxx

• 0x400x_xxxx

After being written with one of the allowed values, bits 31-20 read back as the written value.

After being written with any other value, bits 31-20 read back as an indeterminate value.

field of DSR.

DMA_DARn field descriptions

these allowed values corresponds to a valid region of the device's memory map. The

allowed values are:

KL27 Sub-Family Reference Manual , Rev. 5, 01/2016

Freescale Semiconductor, Inc.