System Clock Gating Control Register 5 (Sim_Scgc5) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Memory map and register definition

12.3.9 System Clock Gating Control Register 5 (SIM_SCGC5)

Address: 4004_7000h base + 1038h offset = 4004_8038h
Bit 31 30 29
R
W
Reset
0 0 0
Bit 15 14 13
0
R
W
Reset
0 0 0
Field
31 FlexIO Module
FLEXIO
This bit controls the clock gate to the FlexIO Module.
0 Clock disabled
1 Clock enabled
30–22 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
21 LPUART1 Clock Gate Control
LPUART1
This bit controls the clock gate to the LPUART1 module.
0 Clock disabled
1 Clock enabled
20 LPUART0 Clock Gate Control
LPUART0
This bit controls the clock gate to the LPUART0 module.
0 Clock disabled
1 Clock enabled
19 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
18–14 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
13 Port E Clock Gate Control
PORTE
Controls the clock gate to the Port E module.
158
28 27 26 25
0
0 0 0 0
12 11 10 9
0 0 0 0
SIM_SCGC5 field descriptions
Table continues on the next page...
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
24 23 22 21
0 0 0 0
8 7 6 5
1 0 0
1 1 0 0
Description
20 19 18 17
0 0
0 0 0 0
4 3 2 1
0 1
0 0 0 1
Freescale Semiconductor, Inc.
16
0
0
0