Dac Control Register (Dacx_C0) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

25.4.4 DAC Control Register (DACx_C0)

Address: 4003_F000h base + 21h offset = 4003_F021h
Bit 7
Read
DACEN
Write
Reset 0
Field
7 DAC Enable
DACEN
Starts the Programmable Reference Generator operation.
0 The DAC system is disabled.
1 The DAC system is enabled.
6 DAC Reference Select
DACRFS
0 The DAC selects DACREF_1 as the reference voltage.
1 The DAC selects DACREF_2 as the reference voltage.
5 DAC Trigger Select
DACTRGSEL
0 The DAC hardware trigger is selected.
1 The DAC software trigger is selected.
4 DAC Software Trigger
DACSWTRG
Active high. This is a write-only field, which always reads 0. If DAC software trigger is selected and buffer
is enabled, writing 1 to this field will advance the buffer read pointer once.
0 The DAC soft trigger is not valid.
1 The DAC soft trigger is valid.
3 DAC Low Power Control
LPEN
NOTE: See the 12-bit DAC electrical characteristics of the device data sheet for details on the impact of
0 High-Power mode
1 Low-Power mode
2 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
1 DAC Buffer Read Pointer Top Flag Interrupt Enable
DACBTIEN
0 The DAC buffer read pointer top flag interrupt is disabled.
1 The DAC buffer read pointer top flag interrupt is enabled.
0 DAC Buffer Read Pointer Bottom Flag Interrupt Enable
DACBBIEN
0 The DAC buffer read pointer bottom flag interrupt is disabled.
1 The DAC buffer read pointer bottom flag interrupt is enabled.
Freescale Semiconductor, Inc.
6 5
DACTRGSE
DACRFS
L
0 0
DACx_C0 field descriptions
the modes below.
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Chapter 25 12-bit Digital-to-Analog Converter (DAC)
4 3
0
LPEN
DACSWTRG
0 0
Description
2 1
0
DACBTIEN DACBBIEN
0 0
0
0
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