NXP Semiconductors Kinetis KE1xZ256 Reference Manual

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Kinetis KE1xZ256 Sub-Family

Reference Manual

Supports: MKE15Z256VLL7, MKE15Z256VLH7; MKE15Z128VLL7,

MKE15Z128VLH7; MKE14Z256VLL7, MKE14Z256VLH7;

MKE14Z128VLL7, MKE14Z128VLH7.

Document Number: KE1xZP100M72SF0RM

Rev. 3, 07/2018

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Summary of Contents for NXP Semiconductors Kinetis KE1xZ256

Page 1 Kinetis KE1xZ256 Sub-Family Reference Manual Supports: MKE15Z256VLL7, MKE15Z256VLH7; MKE15Z128VLL7, MKE15Z128VLH7; MKE14Z256VLL7, MKE14Z256VLH7; MKE14Z128VLL7, MKE14Z128VLH7. Document Number: KE1xZP100M72SF0RM Rev. 3, 07/2018...
Page 2 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 3: Table Of Contents
Chapter 3 Core Overview ARM Cortex-M0+ ............................... 53 Core Buses and Interfaces.............................54 Core Component Configuration............................55 SysTick Clock Configuration............................55 Chapter 4 Interrupts Introduction...................................57 NVIC configuration..............................57 4.2.1 Interrupt priority levels..........................57 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 4 Memory-Mapped Divide and Square Root (MMDVSQ) Chip-specific Information for this Module........................79 Introduction...................................79 6.2.1 Features................................79 6.2.2 Block diagram..............................80 6.2.3 Modes of operation............................82 External signal description............................83 Memory map and register definition..........................83 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 5 Chip-specific Information for this Module........................105 Introduction...................................105 8.2.1 Overview................................ 106 8.2.2 Features................................107 8.2.3 Modes of operation............................107 Memory map and register definition..........................107 Functional description..............................108 8.4.1 BME decorated stores............................ 108 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 6 Functional description..............................133 10.4.1 Access support............................... 133 Chapter 11 Trigger MUX Control (TRGMUX) 11.1 Chip-specific information for this module........................135 11.1.1 Module Interconnectivity..........................135 11.2 Introduction...................................140 11.2.1 Features................................140 11.3 Functional description..............................140 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 7 DMA channels with no triggering capability....................187 12.5.3 Always-enabled DMA sources........................187 12.6 Initialization/application information........................... 189 12.6.1 Reset................................189 12.6.2 Enabling and configuring sources........................189 Chapter 13 Enhanced Direct Memory Access (eDMA) 13.1 Introduction...................................193 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 8 13.3.20 Enable Asynchronous Request in Stop Register (DMA_EARS)..............225 13.3.21 Channel n Priority Register (DMA_DCHPRIn).................... 226 13.3.22 TCD Source Address (DMA_TCDn_SADDR)..................... 227 13.3.23 TCD Signed Source Address Offset (DMA_TCDn_SOFF)................227 13.3.24 TCD Transfer Attributes (DMA_TCDn_ATTR)...................228 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 9 Initialization/application information........................... 251 13.5.1 eDMA initialization............................251 13.5.2 Programming errors............................253 13.5.3 Arbitration mode considerations........................253 13.5.4 Performing DMA transfers..........................254 13.5.5 Monitoring transfer descriptor status......................258 13.5.6 Channel Linking.............................260 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 10 15.1.2 Modes of operation............................279 15.1.3 External signal description..........................279 15.1.4 Memory map and register descriptions......................279 15.1.5 Functional description............................280 15.2 Usage Guide..................................280 15.2.1 FAU Features..............................281 15.2.2 FAU Configuration............................281 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 11 Flash Program and Erase..........................318 16.5.9 FTFE Command Operations.......................... 318 16.5.10 Margin Read Commands..........................325 16.5.11 Flash command descriptions.......................... 326 16.5.12 Security................................351 16.6 Reset Sequence................................354 16.7 Usage Guide..................................355 Chapter 17 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 12 Chip-specific information for this module........................369 18.1.1 Instantiation Information..........................369 18.2 Introduction...................................372 18.2.1 Features................................372 18.3 Memory Map/Register Definition..........................373 18.3.1 Version ID Register (SCG_VERID)......................374 18.3.2 Parameter Register (SCG_PARAM)......................374 18.3.3 Clock Status Register (SCG_CSR)........................ 375 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 13 RTC Oscillator (OSC32) 19.1 Introduction...................................405 19.1.1 Features and Modes............................405 19.1.2 Block Diagram............................... 405 19.2 RTC Signal Descriptions.............................. 406 19.2.1 EXTAL32 — Oscillator Input........................406 19.2.2 XTAL32 — Oscillator Output........................406 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 14 Reset Pin ............................... 464 21.3 Boot....................................464 21.3.1 Boot options..............................465 21.3.2 Boot sequence..............................466 Chapter 22 Kinetis ROM Bootloader 22.1 Chip-specific information for this module........................469 22.1.1 Boot ROM Configuration..........................469 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 15 Get/SetProperty Command Properties..........................525 22.6.1 Property Definitions............................527 22.7 Kinetis Bootloader Status Error Codes......................... 528 Chapter 23 Reset Control Module (RCM) 23.1 Chip-specific information for this module........................531 23.1.1 Instantiation Information..........................531 23.2 Introduction...................................531 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 16 Peripheral doze...............................559 24.6 Low-power wake-up sources............................560 24.7 Power supply supervisor............................... 560 Chapter 25 System Mode Controller (SMC) 25.1 Introduction...................................563 25.2 Modes of operation............................... 563 25.3 Memory map and register descriptions.........................565 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 17 Memory Map and Register Definition..........................583 26.6.1 Low Voltage Detect Status and Control 1 Register (PMC_LVDSC1)............584 26.6.2 Low Voltage Detect Status and Control 2 Register (PMC_LVDSC2)............585 26.6.3 Regulator Status and Control Register (PMC_REGSC)................586 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 18 Compare Low Register (EWM_CMPL)......................597 28.3.4 Compare High Register (EWM_CMPH)....................... 598 28.3.5 Clock Prescaler Register (EWM_CLKPRESCALER).................. 599 28.4 Functional Description..............................599 28.4.1 The EWM_out Signal............................ 599 28.4.2 The EWM_in Signal............................600 28.4.3 EWM Counter..............................601 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 19 Watchdog refresh mechanism........................614 29.4.3 Configuring the Watchdog..........................616 29.4.4 Using interrupts to delay resets........................617 29.4.5 Backup reset..............................617 29.4.6 Functionality in debug and low-power modes....................618 29.4.7 Fast testing of the watchdog...........................618 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 20 16-bit KERMIT CRC.............................633 Chapter 31 Debug 31.1 Introduction...................................635 31.2 Debug port pin descriptions............................635 31.3 SWD status and control registers..........................635 31.3.1 MDM-AP status register..........................637 31.3.2 MDM-AP Control register..........................638 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 21 KE1xZ Signal Multiplexing and Pin Assignments..................675 33.2.2 Pin properties..............................679 33.2.3 Pinout diagram............................... 682 33.3 Module Signal Description Tables..........................684 33.3.1 Core Modules..............................684 33.3.2 System Modules............................. 685 33.3.3 Clock Modules............................... 685 33.3.4 Analog................................686 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 22 Digital Filter Clock Register (PORTx_DFCR)....................707 34.6.7 Digital Filter Width Register (PORTx_DFWR).................... 707 34.7 Functional description..............................708 34.7.1 Pin control..............................708 34.7.2 Global pin control............................709 34.7.3 External interrupts............................709 34.7.4 Digital filter..............................710 Chapter 35 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 23 35.4.6 Port Data Direction Register (FGPIOx_PDDR).................... 724 35.5 Functional description..............................725 35.5.1 General-purpose input............................725 35.5.2 General-purpose output..........................725 35.5.3 IOPORT................................. 725 Chapter 36 Analog-to-Digital Converter (ADC) 36.1 Chip-specific information for this module........................727 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 24 36.4.13 ADC Gain Register (ADCx_G)........................754 36.4.14 ADC User Gain Register (ADCx_UG)......................755 36.4.15 ADC General Calibration Value Register S (ADCx_CLPS)................. 755 36.4.16 ADC Plus-Side General Calibration Value Register 3 (ADCx_CLP3)............756 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 25 MCU Normal Stop mode operation....................... 773 36.6 Usage Guide..................................773 36.6.1 ADC module initialization sequence......................773 36.6.2 Pseudo-code example.............................774 36.6.3 Calibration..............................775 36.6.4 Application hints............................776 36.6.5 DMA Support on ADC..........................776 36.6.6 ADC low-power modes..........................776 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 26 Windowed mode (#s 5A & 5B)........................795 37.7.6 Windowed/Resampled mode (# 6).........................797 37.7.7 Windowed/Filtered mode (#7)........................798 37.8 Memory map/register definitions..........................799 37.8.1 CMP Control Register 0 (CMPx_C0)......................799 37.8.2 CMP Control Register 1 (CMPx_C1)......................803 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 27 PDB Clocking Information..........................821 38.1.3 Inter-connectivity Information........................822 38.2 Introduction...................................824 38.2.1 Features................................824 38.2.2 Implementation.............................. 825 38.2.3 Back-to-back acknowledgment connections....................825 38.2.4 Block diagram..............................825 38.2.5 Modes of operation............................827 38.3 PDB signal descriptions..............................827 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 28 Using PDB to precisely control ADC conversion..................844 Chapter 39 FlexTimer Module (FTM) 39.1 Chip-specific information for this module........................845 39.1.1 Instantiation Information..........................845 39.1.2 FTM Clocking Information..........................845 39.1.3 Inter-connectivity Information........................846 39.2 Introduction...................................850 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 29 39.4.18 Fault Mode Status (FTMx_FMS)........................890 39.4.19 Input Capture Filter Control (FTMx_FILTER)..................... 892 39.4.20 Fault Control (FTMx_FLTCTRL)......................... 893 39.4.21 Quadrature Decoder Control And Status (FTMx_QDCTRL)................896 39.4.22 Configuration (FTMx_CONF)........................898 39.4.23 FTM Fault Input Polarity (FTMx_FLTPOL)....................899 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 30 39.5.14 Software Output Control Mode........................955 39.5.15 Deadtime insertion............................957 39.5.16 Output mask..............................960 39.5.17 Fault control..............................960 39.5.18 Polarity Control..............................964 39.5.19 Initialization..............................965 39.5.20 Features priority............................. 965 39.5.21 External Trigger............................. 966 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 31 FTM Global Time Base..........................1007 39.9.5 FTM BDM and debug halt mode........................1008 Chapter 40 Low-power Periodic Interrupt Timer (LPIT) 40.1 Chip-specific Information for this Module........................1009 40.1.1 Instantiation Information..........................1009 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 32 Trigger Control for Timers..........................1025 40.5.4 Channel Chaining............................1026 40.6 Usage Guide..................................1026 40.6.1 Periodic timer/counter............................1026 40.6.2 LPIT/ADC Trigger............................1027 Chapter 41 Pulse Width Timer (PWT) 41.1 Chip-specific information for this module........................1031 41.1.1 Instantiation Information..........................1031 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 33 Edge detection and capture control........................ 1042 41.6 Reset overview................................1046 41.6.1 Description of reset operation........................1046 41.7 Interrupts..................................1047 41.7.1 Description of interrupt operation........................1047 41.7.2 Application examples.............................1048 41.8 Initialization/Application information.......................... 1049 41.9 Usage Guide..................................1050 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 34 LPTMR prescaler/glitch filter........................1061 42.5.4 LPTMR compare............................1063 42.5.5 LPTMR counter............................. 1063 42.5.6 LPTMR hardware trigger..........................1064 42.5.7 LPTMR interrupt............................1064 42.6 Usage Guide..................................1064 42.6.1 Time Counter mode............................1064 42.6.2 Pulse Counter mode............................1065 Chapter 43 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 35 43.4.1 Power, clocking, and reset..........................1082 43.4.2 Time counter..............................1083 43.4.3 Compensation..............................1084 43.4.4 Time alarm..............................1085 43.4.5 Update mode..............................1085 43.4.6 Register lock..............................1085 43.4.7 Access control..............................1086 43.4.8 Interrupt................................1086 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 36 Configuration Register 0 (LPSPIx_CFGR0)....................1102 44.3.8 Configuration Register 1 (LPSPIx_CFGR1)....................1103 44.3.9 Data Match Register 0 (LPSPIx_DMR0).......................1105 44.3.10 Data Match Register 1 (LPSPIx_DMR1).......................1105 44.3.11 Clock Configuration Register (LPSPIx_CCR)....................1106 44.3.12 FIFO Control Register (LPSPIx_FCR)......................1107 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 37 Memory Map and Registers............................1128 45.3.1 Version ID Register (LPI2Cx_VERID)......................1131 45.3.2 Parameter Register (LPI2Cx_PARAM)......................1131 45.3.3 Master Control Register (LPI2Cx_MCR)...................... 1132 45.3.4 Master Status Register (LPI2Cx_MSR)......................1133 45.3.5 Master Interrupt Enable Register (LPI2Cx_MIER)..................1135 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 38 45.3.28 Slave Receive Data Register (LPI2Cx_SRDR)..................... 1160 45.4 Functional description..............................1161 45.4.1 Clocking and Resets............................1161 45.4.2 Master Mode..............................1162 45.4.3 Slave Mode..............................1167 45.4.4 Interrupts and DMA Requests........................1170 45.4.5 Peripheral Triggers............................1172 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 39 Interrupts and status flags..........................1219 Chapter 47 Flexible I/O (FlexIO) 47.1 Chip-specific Information for this Module........................1221 47.1.1 Instantiation Information..........................1221 47.1.2 FlexIO Clocking Information.........................1221 47.1.3 Inter-connectivity Information........................1222 47.2 Introduction...................................1223 47.2.1 Overview................................ 1223 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 40 47.3.18 Timer Control N Register (FLEXIO_TIMCTLn)..................1240 47.3.19 Timer Configuration N Register (FLEXIO_TIMCFGn)................1242 47.3.20 Timer Compare N Register (FLEXIO_TIMCMPn)..................1244 47.4 Functional description..............................1245 47.4.1 Shifter operation.............................1245 47.4.2 Timer operation..............................1247 47.4.3 Pin operation..............................1249 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 41 48.4.3 TSI Threshold Register (TSI_TSHD)......................1279 48.4.4 TSI MODE Register (TSI_MODE)....................... 1280 48.4.5 TSI MUTUAL-CAP Register 0 (TSI_MUL0)....................1282 48.4.6 TSI MUTUAL-CAP Register 1 (TSI_MUL1)....................1285 48.4.7 TSI SINC filter Register (TSI_SINC)......................1288 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 42 48.5.12 Wake up MCU from low power modes......................1306 48.5.13 DMA function support........................... 1306 48.5.14 Spread spectrum clocking..........................1306 48.6 Usage Guide..................................1309 48.6.1 TSI Interrupts..............................1309 48.6.2 How to use TSI module..........................1309 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 43: About This Manual
• Chip-specific: The first section, Chip-specific [module name] information, includes the number of module instances on the chip and possible implementation differences between the module instances, such as differences in FIFO depths or the number of Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 44: Example: Chip-Specific Information That Supersedes Content In The Same Chapter
• LIN Specification Package Revision 1.3; December 12, 2002 • LIN Specification Package Revision 2.0; September 23, 2003 Sample Reference Manual Figure 1-1. Example: chapter chip-specific information and general module information Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 45: Example: Chip-Specific Information That Refers To A Different Chapter
1.3.2 Example: chip-specific information that refers to a different chapter The chip-specific information below refers to another chapter's chip-specific information. In this case, read both sets of chip-specific information before reading further in the chapter. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 46: Register Descriptions
• The page number on which each register is described • Register figures • Field-description tables • Associated text The register figures show the field structure using the conventions in the following figure. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 47: Conventions
Fixed-width type indicates text that must be typed exactly as shown. It is used for instruction mnemonics, directives, symbols, subcommands, parameters, and operators. Fixed-width type Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 48: Special Terms
• Consider undefined locations in memory to be reserved. Write 1 to clear: Refers to a register bitfield that must be written as 1 to be "cleared." Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 49: Introduction
-M0+ MCUs and product family. It also presents high-level descriptions of the modules available on the device covered by this document. 2.2 Block Diagram The following figure shows a top-level block diagram of the MCU superset device. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 50: Module Functional Categories
Figure 2-1. MCU block diagram 2.3 Module Functional Categories The modules on this device are grouped into functional categories. The following sections describe the modules assigned to each category in more detail. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 51 • Low-power Inter-integrated circuit (LPI • Low-power UART (LPUART) • FlexIO Human-machine interfaces (HMI) • General purpose input/output controller (GPIO) • Capacitive touch sense input (TSI) interface enabled in hardware Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 52 Module Functional Categories Table 2-1. Module functional categories Module category Description • High drive I/O pins, see properties. • Digital filters, see "Ports summary" table in Port control and interrupt module features. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 53: Core Overview
• Micro Trace Buffer (MTB) • 24-bit system tick timer (SysTick) The detailed architecture and programming model of Cortex-M0+ processor are discussed in the following documents from ARM. • Cortex-M0+ Devices Generic User Guide Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 54: Core Buses And Interfaces
Debugger Wakeup Interrupt Memory Protection interface Controller (WIC) Unit (MPU) Optional Debug Access Bus Matrix Port AHB-Lite interface Optional Optional to system single-cycle Serial-Wire or JTAG IO port debug port Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 55: Core Component Configuration
SysTick Calibration Value Register (SYST_CALIB) is always zero. • The NOREF bit in SysTick Calibration Value Register (SYST_CALIB) is always set, implying that CORE_CLK is the only available source of reference timing. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 56 SysTick Clock Configuration Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 57: Interrupts
Cortex-M0+ Technical Reference Manual 4.2 NVIC configuration The NVIC supports configurable interrupt number and level of priority. The following sections speficy the exact priority level and interrupt vectors implemented on this device. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 58: Non-Maskable Interrupt
ARM core Hard Fault 0x0000_0010 – – — — 0x0000_0014 – – — — 0x0000_0018 – – — — 0x0000_001C – – — — Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 59 — 0x0000_0098 LPIT LPIT channel 0-3 0x0000_009C FlexIO — 0x0000_00A0 — 0x0000_00A4 PDB0 — 0x0000_00A8 Port control module Pin detect (Port B, C, D) Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 60: Determining The Bitfield And Register Location For Configuring A Particular Interrupt
• To determine the particular IRQ's bitfield location within these particular registers: • NVIC_ISER1, NVIC_ICER1, NVIC_ISPR1, NVIC_ICPR1, NVIC_IABR1 bit location = IRQ mod 32 = 26 • NVIC_IPR14 bitfield starting location = 8 × (IRQ mod 4) + 4 = 20 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 61 NVIC_IPR14 bitfield range is 20-21 Therefore, the following bitfield locations are used to configure the LPTMR interrupts: • NVIC_ISER1[26] • NVIC_ICER1[26] • NVIC_ISPR1[26] • NVIC_ICPR1[26] • NVIC_IABR1[26] • NVIC_IPR14[21:20] Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 62 Interrupt channel assignments Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 63: System Integration Module (Sim)
5.2 Memory map and register definition NOTE The SIM registers can only be written in the supervisor mode. In the user mode, write accesses are blocked and will result in a bus error. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 64: Chip Control Register (Sim_Chipctl)
E_EN Reset SIM_CHIPCTL field descriptions Field Description 31–20 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 65 This read-only field is reserved and always has the value 0. ADC_ ADC interleave channel enable INTERLEAVE_ Select ADC interleave pins. Bit 1 to 0 are for PTB1 and PTB0 respectively. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 66: Ftm Option Register 0 (Sim_Ftmopt0)
FTM1 external clock driven by TCLK2 pin. No clock input 25–24 FTM0 External Clock Pin Select FTM0CLKSEL Selects the external pin used to drive the clock to the FTM0 module. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 67: Adc Options Register (Sim_Adcopt)
Reset Reset SIM_ADCOPT field descriptions Field Description 31–22 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 68 2–1 ADC0 software pre-trigger sources ADC0SWPRETRG disabled software pre-trigger 0 software pre-trigger 1 disabled ADC0 trigger source select ADC0TRGSEL Selects trigger source for ADC0. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 69: Ftm Option Register 1 (Sim_Ftmopt1)
FTM2 CH1 Select FTM2CH1SEL Selects FTM2 CH1 input FTM2_CH1 input exclusive OR of FTM2_CH0, FTM2_CH1, and FTM1_CH1 7–6 FTM2 CH0 Select FTM2CH0SEL Selects FTM2 CH0 input Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 70 Software control for FTM0 hardware trigger synchronization No effect. Write 1 to assert the TRIG1 input to FTM0. Software must clear this bit to allow other trigger sources to assert. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 71: System Device Identification Register (Sim_Sdid)
Specifies the silicon feature set identication number for the device. 00010 for this device. PINID Pin identification Specifies the pin count of the device. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 72: Flash Configuration Register 1 (Sim_Fcfg1)
IFR via the PGMPART flash command. Address: 4004_8000h base + 4Ch offset = 4004_804Ch NVMSIZE PFSIZE EEERAMSIZE Reset DEPART Reset * Notes: • x = Undefined at reset. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 73 Flash accesses are disabled (and generate a bus error) and the Flash memory is placed in a low power state. This bit should not be changed during VLP modes. Relocate the interrupt vectors out of Flash memory before disabling the Flash. Flash is enabled Flash is disabled Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 74: Flash Configuration Register 2 (Sim_Fcfg2)
This field concatenated with 13 trailing zeros indicates the first invalid address of data flash (block 1). Reserved This field is reserved. This read-only field is reserved and always has the value 0. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 75: Unique Identification Register High (Sim_Uidh)
0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* Reset * Notes: • Reset value loaded during System Reset from Flash IFR. SIM_UIDMH field descriptions Field Description UID95_64 Unique Identification Unique identification for the device. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 76: Unique Identification Register Mid Low (Sim_Uidml)
0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* Reset * Notes: • Reset value loaded during System Reset from Flash IFR. SIM_UIDL field descriptions Field Description UID31_0 Unique Identification Unique identification for the device. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 77: Miscellaneous Control Register (Sim_Misctrl)
DMA channel 5 and channel 1 interrupt select bit (logic 1 is ch5 and logic 0 is ch1) SIM_MISCTRL Bit 4 of DMA channel 4 and channel 0 interrupt select bit (logic 1 is ch4 and logic 0 is ch0) SIM_MISCTRL Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 78 Memory map and register definition SIM_MISCTRL field descriptions (continued) Field Description 3–1 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Software Trigger bit to TRGMUX SW_TRG Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 79: Memory-Mapped Divide And Square Root (Mmdvsq)
The supported integer divide operations include 32/32 signed (SDIV) and unsigned (UDIV) calculations. 6.2.1 Features The key features of the MMDVSQ include: • Lightweight implementation of 32-bit integer divide and square root arithmetic operations Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 80: Block Diagram
A generic block diagram of the processor core and platform for this class of ultra low-end microcontrollers is shown in Figure 6-1. The MMDVSQ module’s location as a memory- mapped co-processor is highlighted. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 81 Peripherals Alt-Master PBRIDGE DMA_4ch Array Figure 6-1. Generic Cortex-M0+ Core Platform Block Diagram Next, a block diagram of the internal structure of the MMDVSQ module is presented. See Figure 6-2. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 82: Modes Of Operation
MMDVSQ is only clocked when responding to bus requests to its programming model or is busy performing a calculation. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 83: External Signal Description
Input dividend (numerator) for the divide Divisor (MMDVSQ_DSOR) Input divisor (denominator) for the divide Control/Status (MMDVSQ_CSR) Control for divide, status for divide and square root Result (MMDVSQ_RES) Output result Radicand (MMDVSQ_RCND) Input "square" data Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 84: Dividend Register (Mmdvsq_Dend)
(read or write) of the DSOR register while the module is busy during a calculation causes the access to be stalled (using wait states) until the calculation completes. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 85 Reset * Notes: • x = Undefined at reset. MMDVSQ_DSOR field descriptions Field Description DIVISOR Divisor This is the input divisor operand for divide calculations. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 86: Control/Status Register (Mmdvsq_Csr)
This read-only bit is asserted when the MMDVSQ is performing a divide or square root. When an operation is initiated, the hardware sets this flag. It remains asserted until the operation completes and the Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 87 This indicator configures the MMDVSQ’s response to divide-by-zero calculations. If both CSR[DZ] and CSR[DZE] are set, then a subsequent read of the RES register is error terminated to signal the processor of the attempted divide-by-zero. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 88 CSR[DFS] = 0, it is ignored. This bit always reads as a zero. The state of the register write data defines this bit’s function. No operation initiated If CSR[DFS] = 1, then initiate a divide calculation, else ignore Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 89: Result Register (Mmdvsq_Res)
Reset * Notes: • x = Undefined at reset. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 90: Functional Description
ARM Cortex-Mx definition and returns 0x8000_0000 (the lower 32 bits of the +2 result) as the quotient with no indication of the overflow condition. If the remainder is selected as the output of this calculation, it returns 0x0000_0000. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 91 6.5.1.2.2 Square root using Q notation Consider the use of Q notation for square root calculations returning fractional values. The following description is taken from http://en.wikipedia.org/wiki/Q_(number_format). Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 92 Q number left justified in the machine word. For a given Qm.n format, using an m+n+1 bit signed integer container with n fractional bits: • its range is [-2 • its resolution is 2 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 93: Execution Times
Stated differently, it represents the time CSR[BUSY] is asserted for a given calculation. In the following two tables, “x” signals a bit with a don’t care value. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 94 Table 6-5. Square Root Execution Times RCND[31:0] Execution Time with CSR[BUSY] = 1 [cycles] (01,1x)xx_xxxx_xxxx_xxxx__xxxx_xxxx_xxxx_xxxx 00(01,1x)_xxxx_xxxx_xxxx_x_xxx_xxxx_xxxx_xxxx 0000_(01,1x)xx_xxxx_xxxx__xxxx_xxxx_xxxx_xxxx 0000_00(01,1x)_xxxx_xxxx__xxxx_xxxx_xxxx_xxxx 0000_0000_(01,1x)xx_xxxx__xxxx_xxxx_xxxx_xxxx 0000_0000_00(01,1x)_xxxx__xxxx_xxxx_xxxx_xxxx 0000_0000_0000_(01,1x)xx__xxxx_xxxx_xxxx_xxxx 0000_0000_0000_00(01,1x)__xxxx_xxxx_xxxx_xxxx 0000_0000_0000_0000__(01,1x)xx_xxxx_xxxx_xxxx 0000_0000_0000_0000__00(01,1x)_xxxx_xxxx_xxxx 0000_0000_0000_0000__0000_(01,1x)xx_xxxx_xxxx 0000_0000_0000_0000__0000_00(01,1x)_xxxx_xxxx 0000_0000_0000_0000__0000_0000_(01,1x)xx_xxxx 0000_0000_0000_0000__0000_0000_00(01,1x)_xxxx 0000_0000_0000_0000__0000_0000_0000_(01,1x)xx 0000_0000_0000_0000__0000_0000_0000_00(01,1x) 0000_0000_0000_0000__0000_0000_0000_0000 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 95: Software Interface
1. Read DEND, DSOR, and CSR registers and save the values as part of the task state. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 96 2. Reload DEND, DSOR, CSR, and RES registers from the saved state. Since the original context save of the control/status register is guaranteed to have CSR[SRT] = 0, there is no divide operation initiated when this register is reloaded in step Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 97: Miscellaneous Control Module (Mcm)
Fetch NVIC SHFT LD/ST MTB Port AHB Bus IO Port MMDVSQ PRAM Array GPIO AXBS Slave -Lite Peripherals Alt-Master PBRIDGE DMA_4ch Array (FMC) Figure 7-1. Cortex-M0+ core platform block diagram Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 98: Introduction
Crossbar Switch (AXBS) Slave Configuration F000_3008 0007h 7.3.1/99 (MCM_PLASC) Crossbar Switch (AXBS) Master Configuration F000_300A 0005h 7.3.2/99 (MCM_PLAMC) F000_300C Platform Control Register (MCM_PLACR) 0000_0250h 7.3.3/100 F000_3040 Compute Operation Control Register (MCM_CPO) 0000_0000h 7.3.4/103 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 99: Crossbar Switch (Axbs) Slave Configuration (Mcm_Plasc)
This read-only field is reserved and always has the value 0. Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 100: Platform Control Register (Mcm_Placr)
Cache is on for instruction and off for data. Cache is off for instruction and on for data. Cache is off for both instruction and data. Cache is off. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 101 Disable Flash Controller Speculation DFCS Disables flash controller speculation. Enable flash controller speculation. Disable flash controller speculation. Enable Flash Data Speculation EFDS Enables flash data speculation. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 102 Arbitration select Fixed-priority arbitration for the crossbar masters Round-robin arbitration for the crossbar masters Reserved This field is reserved. This read-only field is reserved and always has the value 0. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 103: Compute Operation Control Register (Mcm_Cpo)
Compute operation entry has completed or compute operation exit has not completed. Compute Operation Request CPOREQ This bit is auto-cleared by vector fetching if CPOWOI = 1. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 104 Memory map/register descriptions MCM_CPO field descriptions (continued) Field Description Request is cleared. Request Compute Operation. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 105: Bit Manipulation Engine (Bme)
BME decorated references are only available on system bus transactions generated by the processor core and targeted at the standard 512 KB peripheral address space based at 0x4000_0000 . The decoration semantic is embedded into address bits[28:19], creating a Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 106: Overview
KB space based at 0x400F_F000 for GPIO accesses. This organization provides compatibility with the Kinetis K Family. Attempted accesses to the memory space located between 0x4008_0000 - 0x400F_EFFF are error terminated due to an illegal address. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 107: Features
The BME module provides a memory-mapped capability and does not include any programming model registers. The exact set of functions supported by the BME are detailed in the Functional description. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 108: Functional Description
AHB data phase, and then the write is performed in the second AHB data phase. A generic timing diagram of a decorated store showing a peripheral bit field insert operation is shown as follows: Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 109 NOTE Any wait states inserted by the slave device are simply passed through the BME back to the master input bus, stalling the AHB transaction cycle for cycle. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 110 Table 8-1. Cycle definitions of decorated store: logical AND Pipeline stage Cycle BME AHB_ap Forward addr to memory; Recirculate captured addr + <next> Decode decoration; Convert attr to memory as slave_wt Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 111 & 0xE00FFFFF, size] // memory read tmp | wdata // modify mem[accessAddress & 0xE00FFFFF, size] = tmp // memory write The cycle-by-cycle BME operations are detailed in the following table. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 112 & 0xE00FFFFF, size] // memory read tmp ^ wdata // modify mem[accessAddress & 0xE00FFFFF, size] = tmp // memory write The cycle-by-cycle BME operations are detailed in the following table. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 113 The "-" indicates an address bit "don't care". Note, unlike the other decorated store operations, BFI uses addr[19] as the least significant bit in the "w" specifier and not as an address bit. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 114 Capture address, attributes BME AHB_dp <previous> Perform memory read; Form Perform write sending bit mask; Form bitwise registered data to memory ((mask) ? wdata : rdata)) and capture destination data in register Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 115: Bme Decorated Loads
AHB data phase. This is the only decorated transaction that is not an atomic read-modify-write, as it is a simple data read. A generic timing diagram of a decorated load showing a peripheral load-and-set 1-bit operation is shown as follows. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 116 4. Cycle x+2, second AHB data phase: The selected original 1-bit is right-justified, zero-filled and then driven onto the input read data bus, while the registered write data is sourced onto the output write data bus Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 117 • Cycle x, 1st AHB address phase: Read from input bus is translated into a read operation on the output bus with the actual memory address (with the decoration removed) and then captured in a register • Cycle x+1, 2nd AHB address phase: Idle cycle Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 118 // generate bit mask rdata = (tmp & mask) >> b // read data returned to core tmp & ~mask // modify mem[accessAddress & 0xE00FFFFF, size] = tmp // memory write Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 119 // decorated load-and-set 1 mem[accessAddress & 0xE00FFFFF, size] // memory read mask 1 << b // generate bit mask rdata = (tmp & mask) >> b // read data returned to core Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 120 8-11, where addr[30:29] = 10 for peripheral, addr[28] = 1 specifies the unsigned bit field extract operation, addr[27:23] is "b", the LSB identifier, addr[22:19] is "w", the bit field width minus 1 identifier, and mem_addr[18:0] specifies the address Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 121: Additional Details On Decorated Addresses And Gpio Accesses
AND, OR, XOR, LAC1 and LAS1, this bit functions as a true address bit, while for BFI and UBFX, this bit defines the least significant bit of the "w" bit field specifier. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 122: Application Information
:: [addr] "r" (ADDR), [wdata] "r" (WDATA) : "r2", "r3"); #define IOANDB(ADDR,WDATA) __asm("ldr r3, =(1<<26);" "orr r3, %[addr];" "mov r2, %[wdata];" "strb r2, [r3];" :: [addr] "r" (ADDR), [wdata] "r" (WDATA) : "r2", "r3"); Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 123 :: [addr] "r" (ADDR), [wdata] "r" (WDATA) : "r2", "r3"); #define IOXORB(ADDR,WDATA) __asm("ldr r3, =(3<<26);" "orr r3, %[addr];" "mov r2, %[wdata];" "strb r2, [r3];" :: [addr] "r" (ADDR), [wdata] "r" (WDATA) : "r2", "r3"); Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 124 Application information Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 125: Crossbar Switch Lite (Axbs-Lite)
PRAM Array GPIO AXBS Slave -Lite Peripherals Alt-Master PBRIDGE DMA_4ch Array (FMC) Figure 9-1. Cortex-M0+ core platform block diagram The masters connected to the crossbar switch are assigned as follows: Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 126: Introduction
9.2.1 Features The crossbar switch includes these features: • Symmetric crossbar bus switch implementation • Allows concurrent accesses from different masters to different slaves Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 127: Memory Map / Register Definition
Additionally, when no master is requesting access to a slave port, the crossbar drives IDLE transfers onto the slave bus, even though a default master may be granted access to the slave port. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 128: Arbitration
The following table describes possible scenarios based on the requesting master port: Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 129: Initialization/Application Information
9.5 Initialization/application information No initialization is required for the crossbar switch. See the chip-specific crossbar switch information for the reset state of the arbitration scheme. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 130 Initialization/application information Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 131: Peripheral Bridge (Aips-Lite)
This device contains one peripheral bridge. A generic block diagram of the processor core and platform for this class of microcontrollers is shown in the following figure. The AIPS (PBRIDGE) module's location is highlighted. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 132: Introduction
4 KB. (It might be possible that all the peripheral slots are not used. See the memory map chapter for details on slot assignments.) The bridge includes separate clock enable inputs for each of the slots to accommodate slower peripherals. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 133: Features
Misaligned accesses are supported to allow memory to be placed on the slave peripheral bus. Peripheral registers must not be misaligned, although no explicit checking is performed by the peripheral bridge. All accesses are performed with a single transfer. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 134 All accesses to the peripheral slots must be sized less than or equal to the designated peripheral slot size. If an access is attempted that is larger than the targeted port, an error response is generated. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 135: Trigger Mux Control (Trgmux)
1-1 paired up, and are both selected by the same trigger control register. Not every module has pre-trigger input, please refer to the respective module chapter for details. Following is the main structure of TRGMUX, and take ModuleA as an example. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 136 VSS trigger VDD trigger SIM_SW_TRG Software trigger controlled by SIM module TRGMUX_INx TRGMUX external trigger input x LPUARTx_RX_data LPUARTx receive end of word trigger Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 137 LPTMRx timer counter match trigger LPIT_CHx LPIT channel x timer counter match trigger FTMx_TRIG FTMx timer counter match trigger CMPx_OUT CMPx output trigger FlexIO_TRIGx FlexIO timer x counter match trigger Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 138 ---------> in27 out51 ---------> in28 out52 Reserved Reserved ---------> in29 out53 ---------> in30 out54 ---------> in31 out55 TRGMUX_PDB0 out56 SEL0 ----------------------> PDB0_EXTRG out57 out58 out59 Reserved out60 Reserved out61 out62 out63 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 139 ADC. There is another PDB pre-trigger scheme existing on this device, which is not through TRGMUX. Please refer to ADC section for details on ADC trigger implementation on this device. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 140: Introduction
See each peripheral's TRGMUX register for details. 11.4 Memory map and register definition The TRGMUX module contains register fields for selecting the trigger input for peripheral modules. 11.4.1 TRGMUX1 Register Descriptions Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 141 011100 - (0x1c) Unused. 011101 - (0x1d) Unused. 011110 - (0x1e) Unused. 011111 - (0x1f) Unused. 100000 - (0x20) Unused 100001 - (0x21) Unused 100010 - (0x22) Unused 100011 - (0x23) Unused Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 142 111100 - (0x3c) Unused 111101 - (0x3d) Unused 111110 - (0x3e) Unused 111111 - (0x3f) Unused Absolute Register Width Access Reset value address (In bits) 40063000h TRGMUX_CTRL0 (TRGMUX_CTRL0) 00000000h 40063004h TRGMUX_CTRL1 (TRGMUX_CTRL1) 00000000h Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 143 This read/write bit field is used to configure the MUX select for peripheral trigger input 2. Refer to the Select Bit Fields table in the Features section for bit field information. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 144 Reset Bits Reserved SEL1 Reserved SEL0 Reset 11.4.1.3.3 Fields Field Function Enable This bit shows whether the register can be written or not. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 145: Trgmux0 Register Descriptions
000011 - (0x03) TRGMUX IN3 input is selected. 000100 - (0x04) RTC Seconds input is selected. 000101 - (0x05) RTC Alarm input is selected. 000110 - (0x06) LPTMR0 input is selected. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 146 100101 - (0x25) Unused 100110 - (0x26) Unused 100111 - (0x27) Unused 101000 - (0x28) Unused 101001 - (0x29) Unused 101010 - (0x2a) Unused 101011 - (0x2b) Unused 101100 - (0x2c) Unused Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 147 TRGMUX PDB0 (TRGMUX_PDB0) 00000000h 40062044h TRGMUX FLEXIO (TRGMUX_FLEXIO) 00000000h 40062048h TRGMUX LPIT0 (TRGMUX_LPIT0) 00000000h 4006204Ch TRGMUX LPUART0 (TRGMUX_LPUART0) 00000000h 40062050h TRGMUX LPUART1 (TRGMUX_LPUART1) 00000000h Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 148 11.4.2.2.2 Function TRGMUX Register 11.4.2.2.3 Diagram Bits Rese SEL3 Reserved SEL2 rved Reset Bits Reserved SEL1 Reserved SEL0 Reset 11.4.2.2.4 Fields Field Function Enable Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 149 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. Refer to the Select Bit Fields table in the Features section for bit field information. 11.4.2.3 TRGMUX EXTOUT0 (TRGMUX_EXTOUT0) 11.4.2.3.1 Address Register Offset TRGMUX_EXTOUT0 40062004h TRGMUX Register Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 150 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. Refer to the Select Bit Fields table in the Features section for bit field information. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 151 Select Bit Fields table in the Features section for bit field information. 15-14 This read-only bit field is reserved and always has the value 0. — Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 152 SEL0 Reset 11.4.2.5.3 Fields Field Function Enable This bit shows whether the register can be written or not. 0 - Register can be written. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 153 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. Refer to the Select Bit Fields table in the Features section for bit field information. 11.4.2.6 TRGMUX ADC1 (TRGMUX_ADC1) 11.4.2.6.1 Address Register Offset TRGMUX_ADC1 40062010h TRGMUX Register Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 154 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. Refer to the Select Bit Fields table in the Features section for bit field information. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 155 This read-only bit field is reserved and always has the value 0. — 13-8 This read-only bit field is reserved and always has the value 0. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 156 0 - Register can be written. 1 - Register cannot be written until the next system Reset. This read-only bit field is reserved and always has the value 0. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 157 Select Bit Fields table in the Features section for bit field information. 11.4.2.9 TRGMUX FTM0 (TRGMUX_FTM0) 11.4.2.9.1 Address Register Offset TRGMUX_FTM0 40062028h TRGMUX Register 11.4.2.9.2 Diagram Bits Rese SEL3 Reserved SEL2 rved Reset Bits Reserved SEL1 Reserved SEL0 Reset Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 158 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. Refer to the Select Bit Fields table in the Features section for bit field information. 11.4.2.10 TRGMUX FTM1 (TRGMUX_FTM1) 11.4.2.10.1 Address Register Offset TRGMUX_FTM1 4006202Ch TRGMUX Register Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 159 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. Refer to the Select Bit Fields table in the Features section for bit field information. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 160 Select Bit Fields table in the Features section for bit field information. 15-14 This read-only bit field is reserved and always has the value 0. — Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 161 SEL0 Reset 11.4.2.12.3 Fields Field Function Enable This bit shows whether the register can be written or not. 0 - Register can be written. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 162 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. Refer to the Select Bit Fields table in the Features section for bit field information. 11.4.2.13 TRGMUX FLEXIO (TRGMUX_FLEXIO) 11.4.2.13.1 Address Register Offset TRGMUX_FLEXIO 40062044h TRGMUX Register Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 163 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. Refer to the Select Bit Fields table in the Features section for bit field information. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 164 Select Bit Fields table in the Features section for bit field information. 15-14 This read-only bit field is reserved and always has the value 0. — Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 165 SEL0 Reset 11.4.2.15.3 Fields Field Function Enable This bit shows whether the register can be written or not. 0 - Register can be written. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 166 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. Refer to the Select Bit Fields table in the Features section for bit field information. 11.4.2.16 TRGMUX LPUART1 (TRGMUX_LPUART1) 11.4.2.16.1 Address Register Offset TRGMUX_LPUART1 40062050h TRGMUX Register Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 167 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. Refer to the Select Bit Fields table in the Features section for bit field information. 11.4.2.17 TRGMUX LPI2C0 (TRGMUX_LPI2C0) Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 168 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 169 This read-only bit field is reserved and always has the value 0. — 29-24 This read-only bit field is reserved and always has the value 0. — Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 170 Select Bit Fields table in the Features section for bit field information. 11.4.2.19 TRGMUX LPSPI0 (TRGMUX_LPSPI0) 11.4.2.19.1 Address Register Offset TRGMUX_LPSPI0 4006205Ch TRGMUX Register 11.4.2.19.2 Diagram Bits Rese Reserved Reserved Reserved rved Reset Bits Reserved Reserved Reserved SEL0 Reset Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 171 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. Refer to the Select Bit Fields table in the Features section for bit field information. 11.4.2.20 TRGMUX LPSPI1 (TRGMUX_LPSPI1) 11.4.2.20.1 Address Register Offset TRGMUX_LPSPI1 40062060h TRGMUX Register Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 172 This read/write bit field is used to configure the MUX select for peripheral trigger input 0. Refer to the Select Bit Fields table in the Features section for bit field information. 11.4.2.21 TRGMUX LPTMR0 (TRGMUX_LPTMR0) Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 173 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 174 This read-only bit field is reserved and always has the value 0. — 29-24 This read-only bit field is reserved and always has the value 0. — Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 175 Select Bit Fields table in the Features section for bit field information. 11.4.2.23 TRGMUX PWT (TRGMUX_PWT) 11.4.2.23.1 Address Register Offset TRGMUX_PWT 4006206Ch TRGMUX Register 11.4.2.23.2 Diagram Bits Rese Reserved Reserved Reserved rved Reset Bits Reserved Reserved Reserved SEL0 Reset Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 176: Usage Guide
CPU, which is also useful when CPU is in WAIT/STOP mode. The following are some typical use-cases for TRGMUX. 11.5.1 ADC Trigger Source The following triggers are via the TRGMUX: • CMP out to trigger each ADC Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 177: Cmp Window/Sample Input
For details, please refer to “Window Mode” section in the CMP chapter. 11.5.3 FTM Fault Detection Input / Hardware Triggers and Synchronization Please refer to the FTM chapter for more details. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 178 Usage Guide Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 179: Direct Memory Access Multiplexer (Dmamux)
TSI DMA Transfer LPUART0 Receive LPUART0 Transmit LPUART1 Receive LPUART1 Transmit LPUART2 Receive LPUART2 Transmit Reserved — Reserved — FlexIO Shifter0 FlexIO Shifter1 FlexIO Shifter2 Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 180 ADC0 COCO ADC1 ADC1 COCO Reserved — CMP0 — CMP1 — Reserved — PDB0 — Reserved — Reserved — Port control module Port A Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 181: Dma Trigger Sources
LPIT can trigger DMA via TRGMUX. Table 12-2. DMAMUX trigger sources Trigger number Trigger module Trigger description TRGMUX TRGMUX trigger out0 TRGMUX TRGMUX trigger out1 TRGMUX TRGMUX trigger out2 TRGMUX TRGMUX trigger out3 12.2 Introduction Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 182: Overview
• The first four channels additionally provide a trigger functionality. • Each channel router can be assigned to one of the possible peripheral DMA slots or to one of the always-on slots. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 183: Modes Of Operation
4002_1000 Channel Configuration register (DMAMUX_CHCFG0) 12.4.1/184 4002_1001 Channel Configuration register (DMAMUX_CHCFG1) 12.4.1/184 4002_1002 Channel Configuration register (DMAMUX_CHCFG2) 12.4.1/184 4002_1003 Channel Configuration register (DMAMUX_CHCFG3) 12.4.1/184 Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 184: Channel Configuration Register (Dmamux_Chcfgn)
DMA channel. (Normal mode) Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode. SOURCE DMA Channel Source (Slot) Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 185: Functional Description
Because of the dynamic nature of the system (due to DMA channel priorities, bus arbitration, interrupt service routine lengths, etc.), the number of clock cycles between a trigger and the actual DMA transfer cannot be guaranteed. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 186 This means that if a trigger is seen, but the peripheral is not requesting a transfer, then that trigger will be ignored. This situation is illustrated in the following figure. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 187: Dma Channels With No Triggering Capability
12.5.2 DMA channels with no triggering capability The other channels of the DMAMUX provide the normal routing functionality as described in Modes of operation. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 188: Always-Enabled Dma Sources
DMA registers after every minor loop. For this option, the DMA channel must be disabled in the DMA channel MUX. • Use an always-enabled DMA source. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 189: Initialization/Application Information
DMA channels that have triggering capability. To configure source #5 transmit for use with DMA channel 1, with periodic triggering capability: 1. Write 0x00 to CHCFG1. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 190 *CHCFG10= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000A); volatile unsigned char *CHCFG11= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000B); volatile unsigned char *CHCFG12= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000C); volatile unsigned char *CHCFG13= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000D); Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 191 *CHCFG12= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000C); volatile unsigned char *CHCFG13= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000D); volatile unsigned char *CHCFG14= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000E); volatile unsigned char *CHCFG15= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000F); Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 192 Initialization/application information In File main.c: #include "registers.h" *CHCFG8 = 0x00; *CHCFG8 = 0x87; Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 193: Enhanced Direct Memory Access (Edma)
• Local memory containing transfer control descriptors for each of the 8 channels 13.1.1 eDMA system block diagram Figure 13-1 illustrates the components of the eDMA system, including the eDMA module ("engine"). Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 194: Block Parts
After the minor loop completes execution, the address path hardware writes Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 195: Features
The eDMA module features: • All data movement via dual-address transfers: read from source, write to destination • Programmable source and destination addresses and transfer size • Support for enhanced addressing modes Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 196: Modes Of Operation
In Normal mode, the eDMA transfers data between a source and a destination. The source and destination can be a memory block or an I/O block capable of operation with the eDMA. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 197: Memory Map/Register Definition
0, channel 1, ... channel 7. Each TCDn definition is presented as 11 registers of 16 or 32 bits. 13.3.2 TCD initialization Prior to activating a channel, you must initialize its TCD with the appropriate transfer profile. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 198: Tcd Structure
0000_0000h 13.3.8/211 4000_8018 Clear Enable Error Interrupt Register (DMA_CEEI) (always 13.3.9/212 reads 0) 4000_8019 Set Enable Error Interrupt Register (DMA_SEEI) (always 13.3.10/213 reads 0) Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 199 TCD Signed Minor Loop Offset (Minor Loop Mapping and 4000_9008 Undefined 13.3.27/231 Offset Enabled) (DMA_TCD0_NBYTES_MLOFFYES) TCD Last Source Address Adjustment 4000_900C Undefined 13.3.28/232 (DMA_TCD0_SLAST) Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 200 (Channel Linking Disabled) (DMA_TCD1_BITER_ELINKNO) 4000_9040 TCD Source Address (DMA_TCD2_SADDR) Undefined 13.3.22/227 4000_9044 TCD Signed Source Address Offset (DMA_TCD2_SOFF) Undefined 13.3.23/227 4000_9046 TCD Transfer Attributes (DMA_TCD2_ATTR) Undefined 13.3.24/228 Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 201 TCD Current Minor Loop Link, Major Loop Count (Channel 4000_9076 Undefined 13.3.31/233 Linking Enabled) (DMA_TCD3_CITER_ELINKYES) 4000_9076 DMA_TCD3_CITER_ELINKNO Undefined 13.3.32/235 TCD Last Destination Address Adjustment/Scatter Gather 4000_9078 Undefined 13.3.33/236 Address (DMA_TCD3_DLASTSGA) Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 202 TCD Signed Minor Loop Offset (Minor Loop Mapping 4000_90A8 Enabled and Offset Disabled) Undefined 13.3.26/229 (DMA_TCD5_NBYTES_MLOFFNO) TCD Signed Minor Loop Offset (Minor Loop Mapping and 4000_90A8 Undefined 13.3.27/231 Offset Enabled) (DMA_TCD5_NBYTES_MLOFFYES) Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 203 13.3.35/239 (DMA_TCD6_BITER_ELINKYES) TCD Beginning Minor Loop Link, Major Loop Count 4000_90DE Undefined 13.3.36/240 (Channel Linking Disabled) (DMA_TCD6_BITER_ELINKNO) 4000_90E0 TCD Source Address (DMA_TCD7_SADDR) Undefined 13.3.22/227 Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 204: Control Register (Dma_Cr)
(from high to low channel number) without regard to priority. NOTE For correct operation, writes to the CR register must be performed only when the DMA channels are inactive; that is, when TCDn_CSR[ACTIVE] bits are cleared. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 205 When minor loop mapping is disabled (EMLM is 0), all 32 bits of TCDn word2 are assigned to the NBYTES field. Address: 4000_8000h base + 0h offset = 4000_8000h Reserved Reset Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 206 The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled. Continuous Link Mode Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 207: Error Status Register (Dma_Es)
• A cancel transfer with error bit that will be set when a transfer is canceled via the corresponding cancel transfer control bit Fault reporting and handling for more details. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 208 No source offset configuration error The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. Destination Address Error Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 209: Enable Request Register (Dma_Erq)
The state of the DMA enable request flag does not affect a channel service request made explicitly through software or a linked channel request. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 210 The DMA request signal for the corresponding channel is enabled Enable DMA Request 0 ERQ0 The DMA request signal for the corresponding channel is disabled The DMA request signal for the corresponding channel is enabled Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 211: Enable Error Interrupt Register (Dma_Eei)
The error signal for corresponding channel does not generate an error interrupt The assertion of the error signal for corresponding channel generates an error interrupt request Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 212: Clear Enable Error Interrupt Register (Dma_Ceei)
Clear All Enable Error Interrupts CAEE Clear only the EEI bit specified in the CEEI field Clear all bits in EEI 5–3 This field is reserved. Reserved Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 213: Set Enable Error Interrupt Register (Dma_Seei)
Set only the EEI bit specified in the SEEI field. Sets all bits in EEI 5–3 This field is reserved. Reserved SEEI Set Enable Error Interrupt Sets the corresponding bit in EEI Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 214: Clear Enable Request Register (Dma_Cerq)
Clear only the ERQ bit specified in the CERQ field Clear all bits in ERQ 5–3 This field is reserved. Reserved CERQ Clear Enable Request Clears the corresponding bit in ERQ. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 215: Set Enable Request Register (Dma_Serq)
Set only the ERQ bit specified in the SERQ field Set all bits in ERQ 5–3 This field is reserved. Reserved SERQ Set Enable Request Sets the corresponding bit in ERQ. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 216: Clear Done Status Bit Register (Dma_Cdne)
Clears only the TCDn_CSR[DONE] bit specified in the CDNE field Clears all bits in TCDn_CSR[DONE] 5–3 This field is reserved. Reserved CDNE Clear DONE Bit Clears the corresponding bit in TCDn_CSR[DONE] Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 217: Set Start Bit Register (Dma_Ssrt)
Set only the TCDn_CSR[START] bit specified in the SSRT field Set all bits in TCDn_CSR[START] 5–3 This field is reserved. Reserved SSRT Set START Bit Sets the corresponding bit in TCDn_CSR[START] Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 218: Clear Error Register (Dma_Cerr)
Clear only the ERR bit specified in the CERR field Clear all bits in ERR 5–3 This field is reserved. Reserved CERR Clear Error Indicator Clears the corresponding bit in ERR Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 219: Clear Interrupt Request Register (Dma_Cint)
Clear only the INT bit specified in the CINT field Clear all bits in INT 5–3 This field is reserved. Reserved CINT Clear Interrupt Request Clears the corresponding bit in INT Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 220: Interrupt Request Register (Dma_Int)
Interrupt Request 6 INT6 The interrupt request for corresponding channel is cleared The interrupt request for corresponding channel is active Interrupt Request 5 INT5 Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 221: Error Register (Dma_Err)
A zero in any bit position has no affect on the corresponding channel’s current error status. The CERR is provided so the error indicator for a single channel can easily be cleared. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 222 An error in this channel has not occurred An error in this channel has occurred Error In Channel 0 ERR0 An error in this channel has not occurred An error in this channel has occurred Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 223: Hardware Request Status Register (Dma_Hrs)
A hardware service request for channel 6 is not present A hardware service request for channel 6 is present Hardware Request Status Channel 5 HRS5 Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 224 Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically cleared by hardware. A hardware service request for channel 0 is not present A hardware service request for channel 0 is present Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 225: Enable Asynchronous Request In Stop Register (Dma_Ears)
Disable asynchronous DMA request for channel 2. Enable asynchronous DMA request for channel 2. Enable asynchronous DMA request in stop mode for channel 1. EDREQ_1 Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 226: Channel N Priority Register (Dma_Dchprin)
Channel priority when fixed-priority arbitration is enabled NOTE: Reset value for the channel priority field, CHPRI, is equal to the corresponding channel number for each priority register, that is, DCHPRI7[CHPRI] = 0b111. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 227: Tcd Source Address (Dma_Tcdn_Saddr)
= Undefined at reset. DMA_TCDn_SOFF field descriptions Field Description SOFF Source address signed offset Sign-extended offset applied to the current source address to form the next-state value as each source read is completed. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 228: Tcd Transfer Attributes (Dma_Tcdn_Attr)
The eDMA defaults to privileged data access for all transactions. 8-bit 16-bit 32-bit Reserved 16-byte 32-byte Reserved Reserved 7–3 Destination Address Modulo DMOD See the SMOD definition DSIZE Destination data transfer size See the SSIZE definition Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 229: Tcd Minor Byte Count (Minor Loop Mapping Disabled) (Dma_Tcdn_Nbytes_Mlno)
Which register to use depends on whether minor loop mapping is disabled, enabled but not used for this channel, or enabled and used. TCD word 2 is defined as follows if: Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 230 After the minor count is exhausted, the SADDR and DADDR values are written back into the TCD memory, the major iteration count is decremented and restored to the TCD memory. If the major iteration count is completed, additional processing is performed. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 231: Tcd Signed Minor Loop Offset (Minor Loop Mapping And Offset Enabled)
The minor loop offset is applied to the SADDR Destination Minor Loop Offset enable DMLOE Selects whether the minor loop offset is applied to the destination address upon minor loop completion. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 232: Tcd Last Source Address Adjustment (Dma_Tcdn_Slast)
Reset * Notes: • x = Undefined at reset. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 233: Tcd Signed Destination Address Offset (Dma_Tcdn_Doff)
Address: 4000_8000h base + 1016h offset + (32d × i), where i=0d to 7d Read ELINK LINKCH CITER Write Reset Read CITER Write Reset * Notes: • x = Undefined at reset. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 234 NOTE: When the CITER field is initially loaded by software, it must be set to the same value as that contained in the BITER field. NOTE: If the channel is configured to execute a single service request, the initial values of BITER and CITER should be 0x0001. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 235: (Dma_Tcdn_Citer_Elinkno)
NOTE: When the CITER field is initially loaded by software, it must be set to the same value as that contained in the BITER field. NOTE: If the channel is configured to execute a single service request, the initial values of BITER and CITER should be 0x0001. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 236: Tcd Last Destination Address Adjustment/Scatter Gather Address (Dma_Tcdn_Dlastsga)
Address: 4000_8000h base + 101Ch offset + (32d × i), where i=0d to 7d Read MAJORLINKCH Write Reset Read ACTIVE MAJORELI DONE DREQ INTHALF INTMAJOR START Write Reset * Notes: • x = Undefined at reset. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 237 32-byte data structure loaded as the transfer control descriptor into the local memory. NOTE: To support the dynamic scatter/gather coherency model, this field is forced to zero when written to while the TCDn_CSR[DONE] bit is set. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 238 If this flag is set, the channel is requesting service. The eDMA hardware automatically clears this flag after the channel begins execution. The channel is not explicitly started. The channel is explicitly started via a software initiated service request. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 239: Tcd Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled)
CITER field. As the major iteration count is exhausted, the contents of this field are reloaded into the CITER field. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 240: Tcd Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled)
NOTE: When the software loads the TCD, this field must be set equal to the corresponding CITER field; otherwise, a configuration error is reported. As the major iteration count is exhausted, the Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 241: Functional Description
Descriptor (TCD) eDMA Engine Program Model/ Read Data Channel Arbitration Read Data Address Path Control Data Path Write Data Address eDMA Peripheral eDMA Done Request Figure 13-2. eDMA operation, part 1 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 242 Descriptor (TCD) eDMA Engine Program Model/ Read Data Channel Arbitration Read Data Address Path Control Data Path Write Data Address eDMA Peripheral eDMA Done Request Figure 13-3. eDMA operation, part 2 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 243 En g in e Program Model/ Read Data Channel Arbitration Read Data Address Path Control Data Path Write Data Address eDMA Peripheral eDMA Done Request Figure 13-4. eDMA operation, part 3 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 244: Fault Reporting And Handling
Once all of the channel priorities are set to unique numbers, the DMA may be enabled again by clearing the Halt bit. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 245 The cancel transfer bit does not abort the channel. It simply stops the transferring of data and then retires the channel through its normal shutdown sequence. The application Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 246: Channel Preemption
These low priority channels can be configured to not preempt each other, thus preventing a low priority channel from consuming the preempt slot normally available to a true, high priority channel. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 247: Performance
66.7 53.3 83.3 MHz, 32 bit 166.7 83.3 66.7 100.0 MHz, 32 bit 200.0 100.0 80.0 133.3 MHz, 32 bit 266.7 133.3 106.7 150.0 MHz, 32 bit 300.0 150.0 120.0 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 248 The last part of the TCD is read in. This cycle represents the first data phase for the read, and the address phase for the destination write. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 249 A general formula to compute the peak request rate with overlapping requests is: PEAKreq = freq / [ entry + (1 + read_ws) + (1 + write_ws) + exit ] where: Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 250 • 11 cycles for a software, that is, a TCDn_CSR[START] bit, request • 12 cycles for a hardware, that is, an eDMA peripheral request signal, request Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 251: Initialization/Application Information
The eDMA engine reads the entire TCD, including the TCD control and status fields, as shown in the following table, for the selected channel into its internal address path module. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 252 (BITER). Current major loop iteration Source or destination memory count (CITER) DMA request DMA request DMA request Figure 13-5. Example of multiple loop iterations Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 253: Programming Errors
The hardware service request handshake signals, error interrupts, and error reporting is associated with the selected channel. 13.5.3 Arbitration mode considerations This section discusses arbitration considerations for the eDMA. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 254: Performing Dma Transfers
TCDn_DOFF = 4 TCDn_ATTR[DSIZE] = 2 TCDn_DLAST_SGA= –16 TCDn_CSR[INT_MAJ] = 1 TCDn_CSR[START] = 1 (Should be written last after all other fields have been initialized) All other TCDn fields = 0 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 255 TCDn_CITER = 1 (TCDn_BITER). 7. The eDMA engine writes: TCDn_CSR[ACTIVE] = 0, TCDn_CSR[DONE] = 1, INT[n] = 1. 8. The channel retires and the eDMA goes idle or services the next channel. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 256 Write 32-bits to location 0x200C → last iteration of the minor loop. 6. eDMA engine writes: TCDn_SADDR = 0x1010, TCDn_DADDR = 0x2010, TCDn_CITER = 1. 7. eDMA engine writes: TCDn_CSR[ACTIVE] = 0. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 257 TCDn_CITER = 2 (TCDn_BITER). 15. eDMA engine writes: TCDn_CSR[ACTIVE] = 0, TCDn_CSR[DONE] = 1, INT[n] = 16. The channel retires → major loop complete. The eDMA goes idle or services the next channel. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 258: Monitoring Transfer Descriptor Status
Polling the TCDn_CSR[ACTIVE] bit may be inconclusive, because the active status may be missed if the channel execution is short in duration. The TCD status bits execute the following sequence for a software activated channel: Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 259 DADDR, and NBYTES, which decrement to zero as the transfer progresses, can give an indication of the progress of the transfer. All other values are read back from the TCD local memory. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 260: Channel Linking
1. Minor loop done → set TCD12_CSR[START] bit 2. Minor loop done → set TCD12_CSR[START] bit 3. Minor loop done → set TCD12_CSR[START] bit 4. Minor loop done, major loop done→ set TCD7_CSR[START] bit Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 261: Dynamic Programming
1. Switch to Round-Robin Channel Arbitration mode, change the channel priorities, then switch back to Fixed Arbitration mode, 2. Disable all the channels, change the channel priorities, then enable the appropriate channels. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 262 TCD is fetched from system memory and loaded into that channel’s descriptor location in eDMA programmer’s model, thus replacing the current descriptor. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 263 (written in the next step) instead of a dlast final offest value. 3. Write the TCD.dlast_sga field with the scatter/gather address. 4. Write 1b to the TCD.e_sg bit. 5. Read back the 16 bit TCD control/status field. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 264 If e_sg = 0b and the dlast_sga did not change, the attempted dynamic link did not succeed (the channel was already retiring). If e_sg = 0b and the dlast_sga changed, the dynamic link attempt was successful (the new TCD’s e_sg value cleared the e_sg bit). Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 265: Suspend/Resume A Dma Channel With Active Hardware Service Requests
DMA_HRS[HRSn] is 0 for the appropriate channel. If no service request is present, disable the DMA channel by clearing the channel’s ERQ bit. If a service request is present, wait until the request has been processed and the HRS bit reads zero. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 266: Usage Guide
Using DMA for pulse counting on Kinetis • Using DMA and GPIO to emulate timer functionality on Kinetis Family devices • Using DMA to Emulate ADC Flexible Scan Mode on Kinetis K Series Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 267: Memory And Memory Map
4G bytes (32-bit address) contiguous memory space. This chapter describes the memory and peripheral locations within that memory space. The following figure shows the system memory and peripheral locations. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 268 0x4006_B000 0xF000_3000 LPUART1 peripheral 0x4006_C000 LPUART2 0x4006_D000 0xF000_4000 Reserved MMDVSQ 0x4007_3000 CMP0 0xF000_5000 0x4007_4000 CMP1 0xFFFF_FFFF Reserved 0x4007_5000 Reserved 0xF800_0000 0x4007_D000 IOPORT 0x4007_E000 0xFFFF_FFFF 0x4007_F000 0x4007_FFFF Figure 14-1. Memory map Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 269: Flash Memory
Address range (KB) KE1xZ256VLL7 0x0000_0000–0x0003_FFFF (P-Flash) 0x1000_0000–0x1000_7FFF (FlexNVM) 0x1400_0000–0x1400_07FF (FlexRAM) KE1xZ256VLH7 0x0000_0000–0x0003_FFFF (P-Flash) 0x1000_0000–0x1000_7FFF (FlexNVM) 0x1400_0000–0x1400_07FF (FlexRAM) KE1xZ128VLL7 0x0000_0000–0x0001_FFFF (P-Flash) 0x1000_0000–0x1000_7FFF (FlexNVM) 0x1400_0000–0x1400_07FF (FlexRAM) KE1xZ128VLH7 0x0000_0000–0x0001_FFFF (P-Flash) 0x1000_0000–0x1000_7FFF (FlexNVM) 0x1400_0000–0x1400_07FF (FlexRAM) Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 270: Sram Memory
The following table shows the high-level device memory map. This map provides the complete architectural address space definition for the various sections. Based on the physical sizes of the memories and peripherals, the actual address regions used may be smaller. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 271 Cortex-M0+ core only 0xF000_3000–0xF000_3FFF Miscellaneous Control Module (MCM) Cortex-M0+ core only 0xF000_4000–0xF000_4FFF Memory Mapped Divide and Square Root (MMDVSQ) Cortex-M0+ core only 0xF000_5000–0xF7FF_FFFF Reserved – Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 272: Aliased Bit-Band Regions
A 32-bit read in the alias region returns either: • a value of 0x0000_0000 to indicate the target bit is clear • a value of 0x0000_0001 to indicate the target bit is set Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 273: Bit Manipulation Engine
The peripheral memory map is accessible via a crossbar slave port and the AIPS peripheral bridge. The peripheral bridge converts register access from AHB bus domain to peripheral bus domain. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 274: Peripheral Bridge (Aips-Lite) Memory Map
0x4001_0000 — 0x4001_1000 — 0x4001_2000 — 0x4001_3000 — 0x4001_4000 — 0x4001_5000 — 0x4001_6000 — 0x4001_7000 — 0x4001_8000 — 0x4001_9000 — 0x4001_A000 — 0x4001_B000 — Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 275 FlexTimer (FTM) 2 0x4003_B000 Analog-to-digital converter (ADC) 0 0x4003_C000 — 0x4003_D000 Real-time clock (RTC) 0x4003_E000 — 0x4003_F000 — 0x4004_0000 Low-power timer (LPTMR0) 0x4004_1000 — 0x4004_2000 — Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 276 Peripheral Clock Control (PCC) 0x4006_6000 Low Power I C (LPI C 0) 0x4006_7000 Low Power I C (LPI C 1) 0x4006_8000 — 0x4006_9000 — Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 277: Private Peripheral Bus (Ppb) Memory Map
Table 14-3. PPB memory map System 32-bit Address Range Resource Additional Range Detail Resource 0xE000_0000–0xE000_DFFF Reserved 0xE000_E000–0xE000_EFFF System Control Space 0xE000_E000–0xE000_E00F Reserved (SCS) 0xE000_E010–0xE000_E0FF SysTick 0xE000_E100–0xE000_ECFF NVIC Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 278 Table 14-3. PPB memory map (continued) System 32-bit Address Range Resource Additional Range Detail Resource 0xE000_ED00–0xE000_ED8F System Control Block 0xE000_ED90–0xE000_EDEF Reserved 0xE000_EDF0–0xE000_EEFF Debug 0xE000_EF00–0xE000_EFFF Reserved 0xE000_F000–0xE00F_EFFF Reserved 0xE00F_F000–0xE00F_FFFF Core ROM Space (CRS) Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 279: Flash Acceleration Unit (Fau)
• For any power mode where the program flash memory or FlexMemory cannot be accessed, the FAU is disabled. 15.1.3 External signal description The FAU has no external (off-chip) signals. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 280: Memory Map And Register Descriptions
(FAU) is the interface between the flash memory blocks and the system. In a typical configuration, the core and system bus clock speeds are clock significantly faster than the flash memory clock. The FAU includes features designed to accelerate flash accesses. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 281: Fau Features
This can be changed so that only instructions or only data accesses initiate a speculative prefetch. Instruction only prefetching might be desired if random data accesses are mixed in with mostly sequential instruction accesses to the same bank of flash. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 282 0-1 or ways 0-2 are dedicated for instructions and remaining ways are used for data. NOTE The FAU registers should not be modified while accessing the flash. It is recommended executing any code that modifies the FAU settings from the on-chip SRAM. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 283: Flash Memory Module (Ftfe)
• FlexRAM for high-endurance data store or traditional RAM Flash memory is ideal for single-supply applications, permitting in-the-field erase and reprogramming operations without the need for any external high voltage power sources. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 284: Features
• Section programming for faster bulk programming times • Read access to the program flash block is possible while programming or erasing data in the data flash block or FlexRAM Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 285 • When configured for traditional RAM: • Read and write access possible to the FlexRAM while programming or erasing data in the program or data flash memory Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 286: Block Diagram
Data flash sector — The data flash sector is the smallest portion of the data flash memory that can be erased. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 287 EEPROM, valid writes to the FlexRAM generates a new EEPROM backup data record stored in the EEPROM backup flash memory. FTFE Module — All flash blocks plus a flash management unit providing high-level control and an interface to MCU buses. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 288: External Signal Description
Secure — An MCU state conveyed to the FTFE module as described in the Chip Configuration details for this device. In the secure state, reading and changing NVM contents is restricted. 16.3 External signal description The FTFE module contains no signals that connect off-chip. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 289: Memory Map And Registers
Register (FEPROT). 0x0_040D Flash nonvolatile option byte. Refer to the description of the Flash Option Register (FOPT). 0x0_040C Flash security byte. Refer to the description of the Flash Security Register (FSEC). Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 290: Data Flash 0 Ifr Map
The Program Once field can be read any number of times. This section of the program flash 0 IFR is accessed in 8 byte records using the Read Once and Program Once commands (see Read Once Command Program Once command). Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 291 '1' = FlexRAM is loaded with valid EEPROM data during the flash reset sequence This read-only bitfield is reserved and each bit will always read as one. EEESPLIT Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 292 = Unimplemented or Reserved Table 16-4. FlexNVM partition code field description Field Description This read-only bitfield is reserved and must always be written as one. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 293: Register Descriptions
CCIF. During this initialization period the user may write any register. All register writes are also disabled (except for registers FCNFG and FSTAT) whenever an erase suspend request is active (FCNFG[ERSSUSP]=1). Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 294 Undefined 16.4.4.6/ 4002_0013 Program Flash Protection Registers (FTFE_FPROT0) Undefined 16.4.4.7/ 4002_0016 EEPROM Protection Register (FTFE_FEPROT) Undefined 16.4.4.8/ 4002_0017 Data Flash Protection Register (FTFE_FDPROT) Undefined Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 295 The FSTAT register reports the operational status of the FTFE module. The CCIF, RDCOLERR, ACCERR, and FPVIOL bits are readable and writable. The MGSTAT0 bit is read only. The unassigned bits read 0 and are not writable. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 296 The FPVIOL bit is cleared by writing a 1 to FPVIOL while CCIF is set. Writing a 0 to the FPVIOL bit has no effect. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 297 Read collision error interrupt enabled. An interrupt request is generated whenever an FTFE read collision error is detected (see the description of FSTAT[RDCOLERR]). Erase All Request ERSAREQ Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 298 • reads from the FlexRAM return data previously written to the FlexRAM in EEPROM mode and • writes launch an EEPROM operation to store the written data in the FlexRAM and EEPROM backup Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 299 When the SEC field is set to unsecure, the FSLACC setting does not matter. Factory access granted Factory access denied Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 300 Field Description Nonvolatile Option These bits are loaded from flash to this register at reset. Refer to the device's Chip Configuration details for the definition and use of these bits. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 301 Flash address [15:8] Flash address [7:0] Data Byte 0 Data Byte 1 Data Byte 2 Data Byte 3 Data Byte 4 Data Byte 5 Data Byte 6 Data Byte 7 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 302 To change the program flash protection that is loaded during the reset sequence, unprotect the sector of program flash memory that contains the Flash Configuration Field. Then, reprogram the program flash protection byte. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 303 Unprotected regions can be changed by writing to the FlexRAM. Address: 4002_0000h base + 16h offset = 4002_0016h Read EPROT Write Reset * Notes: • x = Undefined at reset. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 304 Unprotected regions can be changed by both program and erase operations. Address: 4002_0000h base + 17h offset = 4002_0017h Read DPROT Write Reset * Notes: • x = Undefined at reset. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 305 The eight XACC registers allow up to 64 restricted segments of equal memory size. Execute-only access register Program flash execute-only access bits XACCH0 XA[63:56] XACCH1 XA[55:48] XACCH2 XA[47:40] XACCH3 XA[39:32] XACCL0 XA[31:24] XACCL1 XA[23:16] XACCL2 XA[15:8] XACCL3 XA[7:0] Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 306 The eight SACC registers allow up to 64 restricted segments of equal memory size. Supervisor-only access register Program flash supervisor-only access bits SACCH0 SA[63:56] SACCH1 SA[55:48] Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 307 = Undefined at reset. FTFE_SACCn field descriptions Field Description Supervisor-only access control Associated segment is accessible in supervisor mode only Associated segment is accessible in user or supervisor mode Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 308 The flash access segment number register provides the number of program flash segments that are available for XACC and SACC permissions. All bits in the register are read-only. The contents of this register are loaded during the reset sequence. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 309: Functional Description
Individual regions within the flash memory can be protected from program and erase operations. Protection is controlled by the following registers: • FPROTn — Four registers protect 32 regions of the program flash memory as shown in the following figure Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 310 EEPROM backup Last FlexNVM address Figure 16-3. Data flash protection (2 data flash sizes) • FEPROT — Protects eight regions of the EEPROM memory as shown in the following figure Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 311: Flash Access Protection
Access is controlled by the following registers: • FXACC — • eight registers control 64 segments of the program flash memory as shown in the following figure Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 312: Flexnvm Description
Program flash size / 64 SACCH0[SA62] Program flash size / 64 SACCH0[SA63] Last program flash address Figure 16-6. Program flash supervisor access control 16.5.3 FlexNVM Description This section describes the FlexNVM memory. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 313 16-2). The remainder of the FlexRAM not used for EEPROM is not accessible while the FlexRAM is configured for EEPROM (see Set FlexRAM Function command). The EEPROM partition grows upward from the bottom of the FlexRAM address space. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 314 EEPROM data records is copied to the FlexRAM. After the CCIF bit is set, the FlexRAM is available for read or write access. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 315 • EEPROM — allocated FlexNVM based on DEPART; entered with the Program Partition command • EEESIZE — allocated FlexRAM based on DEPART; entered with the Program Partition command • Write_efficiency — Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 316: Interrupts
Table 16-5. FTFE Interrupt Sources FTFE Event Readable Interrupt Status Bit Enable Bit FTFE Command Complete FSTAT[CCIF] FCNFG[CCIE] FTFE Read Collision Error FSTAT[RDCOLERR] FCNFG[RDCOLLIE] Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 317: Flash Operation In Low-Power Modes
The block arbitration logic detects any simultaneous access and reports this as a read collision error (see the FSTAT[RDCOLERR] bit). 16.5.7 Read while write (RWW) The following simultaneous accesses are allowed: Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 318: Flash Program And Erase
FTFE commands are specified using a command write sequence illustrated in Figure 16-10. The FTFE module performs various checks on the command (FCCOB) content and continues with command execution if all requirements are fulfilled. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 319 Program and erase commands also check the address to determine if the operation is requested to execute on protected areas. If the protection check fails, the FSTAT[FPVIOL] (protection error) flag is set. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 320 FCCOB and FSTAT registers. 4. The FTFE sets the FSTAT[CCIF] bit signifying that the command has completed. The flow for a generic command write sequence is illustrated in the following figure. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 321 Program flash 0 Data flash FlexRAM Function 0x00 Read 1s Block × × Verify that a program flash or data flash block is erased. FlexNVM Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 322 IFR are erased then release MCU security. 0x41 Read Once Read 8 bytes of a dedicated 64 byte field in the program flash 0 IFR. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 323 0x4B Erase All Execute- Erase all program only Segments flash execute-only (XA) segments then release flash access control. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 324 FlexRAM Erase Erase Program Program Read Flash Read Flash Read E-Write R-Write Phrase Phrase Sector Sector Read Program Program Phrase flash Erase Flash Sector Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 325: Margin Read Commands
The 'user' and 'factory' levels become, in effect, a minimum safety margin; i.e. if the reads pass at the tighter tolerances of the 'user' and 'factory' margins, then the 'normal' reads have at least this much safety margin before they experience data loss. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 326: Flash Command Descriptions
The FTFE may return invalid data to the MCU with the collision error flag (FSTAT[RDCOLERR]) set. When required by the command, address bit 23 selects between program flash memory (=0) and data flash memory (=1). Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 327 Table 16-9. Read 1s Block Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] An invalid margin choice is specified FSTAT[ACCERR] Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 328 Margin Level Description 0x00 Use the 'normal' read level for 1s 0x01 Apply the 'User' margin to the normal read-1 level 0x02 Apply the 'Factory' margin to the normal read-1 level Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 329 FCCOB. If the comparison at margin-0 fails, the MGSTAT0 bit will be set. The CCIF flag will set after the Program Check operation has completed. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 330 The Version ID field contains an 8 byte code that indicates a specific FTFE implementation. Table 16-16. Read Resource Command FCCOB Requirements FCCOB Number FCCOB contents [7:0] 0x03 (RDRSRC) Flash address [23:16] Flash address [15:8] Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 331 Flash address is not 64-bit aligned FSTAT[ACCERR] 16.5.11.5 Program Phrase command The Program Phrase command programs eight previously-erased bytes in the program flash memory or in the data flash memory using an embedded algorithm. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 332 • Byte 1 data is programmed to byte address start+0b01, • Byte 2 data is programmed to byte address start+0b10, and • Byte 3 data is programmed to byte address start+0b11, etc. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 333 Program flash is selected and the address is out of program flash range FSTAT[ACCERR] Data flash is selected and the address is out of data flash range FSTAT[ACCERR] Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 334 Blocks, Erase All Blocks Unsecure or the Read 1s All Blocks command has not successfully FSTAT[FPVIOL] completed since the last reset Any errors have been encountered during the verify operation FSTAT[MGSTAT0] Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 335 The user may choose to abort a suspended Erase Flash Sector operation by clearing the ERSSUSP bit prior to clearing CCIF for the next command launch. When a suspended operation is aborted, the FTFE starts the new command using the new FCCOB contents. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 336 Data in this sector is not reliable until a new erase command fully completes. The following figure shows how to suspend and resume the Erase Flash Sector operation. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 337 ERSSCR Suspended Resume Erase? ERSSUSP: Bit in FCNFG register No, Abort SUSPACK: Internal Suspend Acknowledge Clear ERSSUSP User Cmd Interrupt/Suspend Figure 16-11. Suspend and Resume of Erase Flash Sector Operation Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 338 After the Program Section operation has completed, the CCIF flag will set and normal access to the FlexRAM is restored. The contents of the Section Program Buffer are not changed by the Program Section operation. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 339 6. To program additional flash sectors, repeat steps through 5. 7. To restore EEPROM functionality, execute the Set FlexRAM Function command to make the FlexRAM available for EEPROM. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 340 Table 16-29. Read 1s All Blocks Command Error Handling Error Condition Error Bit Command not available in current mode/security FSTAT[ACCERR] An invalid margin choice is specified FSTAT[ACCERR] Read-1s fails FSTAT[MGSTAT0] Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 341 IFR (see Program flash 0 IFR map Program Once field). Access to the Program Once field is via 12 records, each 8 bytes long. The Program Once field can be Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 342 Any errors have been encountered during the verify operation. FSTAT[MGSTAT0] 1. If a Program Once record is initially programmed to 0xFFFF_FFFF_FFFF_FFFF, the Program Once command is allowed to execute again on that same record. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 343 Any errors have been encountered during the verify operation FSTAT[MGSTAT0] 1. User margin read may be run using the Read 1s All Blocks command to verify all bits are erased. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 344 Key Byte 0 0x0_0003 Key Byte 1 0x0_0002 Key Byte 2 0x0_0001 Key Byte 3 0x0_0000 Key Byte 4 0x0_0007 Key Byte 5 0x0_0006 Key Byte 6 0x0_0005 Key Byte 7 0x0_0004 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 345 FSEC[SEC] field to the unsecure state, the security byte (see Flash configuration field description) is programmed to the unsecure state by the Erase All Blocks Unsecure command, and the Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 346 : • sets the read margin for 1s according to Table 16-41, • checks the contents of the program flash execute-only segments are in the erased state. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 347 Read 1s All Execute-only Segments command is executed and fails with the FSTAT[MGSTAT0] bit set. The Erase All Execute-only Segments command aborts if Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 348 FlexRAM load during reset option (only bit 0 used): 0 - FlexRAM loaded with valid EEPROM data during reset sequence 1 - FlexRAM not loaded during reset sequence Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 349 IFR using the values provided. The Program Partition command also verifies that the partition codes read back correctly after programming. The CCIF flag is set after the Program Partition operation completes. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 350 16-50) Table 16-50. FlexRAM Function Control FlexRAM Function Action Control Code Make FlexRAM available as RAM: 0xFF • Clear the FCNFG[RAMRDY] and FCNFG[EEERDY] flags Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 351: Security
FSTAT[ACCERR] FlexRAM Function Control Code is not defined FSTAT[ACCERR] FlexRAM Function Control Code is set to make the FlexRAM available for EEPROM, but FSTAT[ACCERR] FlexNVM is not partitioned for EEPROM Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 352: Security
If the keys match, the FSEC[SEC] bits are changed to unsecure the MCU. The entire 8-byte key cannot be all 0s or all 1s, i.e. 0x0000_0000_0000_0000 and 0xFFFF_FFFF_FFFF_FFFF are not accepted by the Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 353 Access Key command) can be run which allows the user to present prospective keys for comparison to the stored keys. If the keys match, the FSEC[SEC] bits are changed to Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 354: Reset Sequence
On each system reset the FTFE module executes a sequence which establishes initial values for the flash block configuration parameters, FPROT, FDPROT, FEPROT, FOPT, FSEC, FXACC, FSACC, and FACNFG registers and the FCNFG[RAMRDY, EEERDY] bits. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 355: Usage Guide
• Using the Kinetis Family Enhanced EEPROM Functionality • Robust Over-the-Air Firmware Updates Using Program Flash Memory Swap on Kinetis Microcontrollers • Using the Kinetis Flash Execute-Only Access Control Feature Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 356 Usage Guide Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 357: Clock Distribution
Various modules have module-specific clocks that can be generated from the FIRC_CLK, SIRC_CLK, SOSC_CLK, FLL_CLK clock. In addition, there are various other module-specific clocks that have other alternate sources. While clock selection for Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 358: High-Level Clocking Diagram
SYS_CLK Clocks the Crossbar, NVIC, Flash controller, FTM and PDB, etc. SYS_CLK can run up to CORE_CLK and divided by DIVCORE bits inside SCG. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 359: Typical Clock Configuration
In default out of reset, the CPU is clocked from internal Fast IRC (IRC48M). The clocks, e.g. core clock and bus clock, are programmed via the SCG module. For the default reset value of divider, please refer to SCG chapter for details. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 360: Vlpr Mode Clocking
Clocks controlled Clocks controlled by bit of PCC by [PCS] bits of registers inside module Communications LPUART0 – LPUART2 Yes FIRC_CLK, Max: 72 MHz SIRC_CLK, Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 361 BUS_CLK, LPO_CLK Max: BUS_CLK LPO_CLK: 1kHz Port Control BUS_CLK, LPO_CLK Max: BUS_CLK LPO_CLK: 128kHz BUS_CLK Max: BUS_CLK BUS_CLK Max: BUS_CLK GPIOC SYS_CLK Max: SYS_CLK Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 362: Lpo Clock Distribution
17.6.2 EWM clocks This table shows the EWM clocks and the corresponding chip clocks. Table 17-2. EWM clock connections Module clock Chip clock Low Power Clock 128 kHz LPO Clock (LPO_CLK) Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 363: Adc Clocking Information
ADCx module PCC module Peripheral Interface Clock PCC_ADCx[CGC] Registers PCC_ADCx[PCS]: see PCC chapter for FLLDIV2_CLK detailed setting DIV2 SOSCDIV2_CLK SOSC DIV2 ALTCLK1 SIRC SIRCDIV2_CLK ALTCLK2 DIV2 ALTCLK3 FIRCDIV2_CLK FIRC ALTCLK4 DIV2 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 364: Pdb Clock Options
The external clock are synchronized by FTM system clock (SYS_CLK). Therefore, to meet Nyquist criteria considering also jitter, the frequency of the external clock source must not exceed 1/4 of the system clock frequency. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 365: Lptmr Prescaler/Glitch Filter Clocking Options
The chosen clock must remain enabled if the LPTMR is to continue operating in all required low-power modes. 17.6.8 RTC Clocking Information The following figure shows the input clock sources available for this module. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 366: Tsi Clocking Information
17.6.9 TSI Clocking Information This following figure shows the TSI clocks. SIM_FTMOPT0[FTMnCLKSEL] Peripheral Clocking - TSI TSI module PCC module SCG module Peripheral Interface Clock BUS_CLK SCG DIVSLOW PCC_TSI[CGC] Registers Main Clock (internal) Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 367: Module Clocking Information For Lpuart, Lpspi, Lpi2C, Flexio And Lpit
PCC_LPUARTx[CGC] Registers PCC_LPUARTx[PCS]: see PCC chapter for FLLDIV2_CLK detailed setting DIV2 SOSCDIV2_CLK SOSC DIV2 SIRC SIRCDIV2_CLK ASYNCH MODULE CLOCK DIV2 (only for LPUART, not in other modules) FIRCDIV2_CLK FIRC DIV2 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 368 Module clocks Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 369: System Clock Generator (Scg)
Clock Distribution chapter. 18.1.1.1.1 SCG clock mode transitions The following figure shows the valid clock mode transitions supported by SCG, for this device. For more information, see the Functional description section. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 370 VLPRUN Valid SCS Modes SIRC SOSC Figure 18-1. SCG Valid Mode Transition Diagram 18.1.1.1.2 Clocking configuration on SCG The following figure shows the clocking configuration on SCG, for this device. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 371 Chapter 18 System Clock Generator (SCG) Figure 18-2. Clocking configuration on SCG Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 372: Introduction
• Either the slow or the fast clock can be selected as the clock source for the MCU system clocks • 2 programmable post-divider clock outputs for each IRC, which can be used as clock sources for other on-chip peripherals • System Crystal Oscillator: Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 373: Memory Map/Register Definition
Fast IRC Configuration Register (SCG_FIRCCFG) 0000_0000h 18.3.15/393 4006_430C Fast IRC Trim Configuration Register (SCG_FIRCTCFG) 0000_0000h 18.3.16/394 4006_4318 Fast IRC Status Register (SCG_FIRCSTAT) See section 18.3.17/395 Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 374: Version Id Register (Scg_Verid)
DIVPRES field: The reset value is controlled by which SCG System Dividers are used by Soc. • CLKPRES field: The reset value is controlled by which SCG Clock Sources are used by Soc. Please reference the Reference manual clocking chapter. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 375: Clock Status Register (Scg_Csr)
RUN mode or div-by-4 or div-by-8 when resetting into VLPR mode. SCG_CSR field descriptions Field Description 31–28 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 376 This read-only field is reserved and always has the value 0. DIVSLOW Slow Clock Divide Ratio 0000 Reserved 0001 Divide-by-2 0010 Divide-by-3 0011 Divide-by-4 0100 Divide-by-5 0101 Divide-by-6 0110 Divide-by-7 0111 Divide-by-8 Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 377: Run Clock Control Register (Scg_Rccr)
0000 Reserved 0001 System OSC (SOSC_CLK) 0010 Slow IRC (SIRC_CLK) 0011 Fast IRC (FIRC_CLK) Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 378 0010 Divide-by-3 0011 Divide-by-4 0100 Divide-by-5 0101 Divide-by-6 0110 Divide-by-7 0111 Divide-by-8 1000 Reserved 1001 Reserved 1010 Reserved 1011 Reserved 1100 Reserved 1101 Reserved Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 379: Vlpr Clock Control Register (Scg_Vccr)
0000 Reserved 0001 System OSC (SOSC_CLK) 0010 Slow IRC (SIRC_CLK) 0011 Reserved 0100 Reserved 0101 Reserved 0110 Reserved 0111 Reserved Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 380 0001 Divide-by-2 0010 Divide-by-3 0011 Divide-by-4 0100 Divide-by-5 0101 Divide-by-6 0110 Divide-by-7 0111 Divide-by-8 1000 Reserved 1001 Reserved 1010 Reserved 1011 Reserved 1100 Reserved 1101 Reserved 1110 Reserved 1111 Reserved Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 381: Scg Clkout Configuration Register (Scg_Clkoutcnfg)
Fast IRC (FIRC_CLK) 0100 Reserved 0101 Low Power FLL (LPFLL_CLK) 0110 Reserved 0111 Reserved 1111 Reserved Reserved This field is reserved. This read-only field is reserved and always has the value 0. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 382: System Osc Control Status Register (Scg_Sosccsr)
This flag is reset on Chip POR only, software can also clear this flag by writing a logic one. System OSC Clock Monitor is disabled or has not detected an error System OSC Clock Monitor is enabled and detected an error Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 383 System OSC Stop Enable SOSCSTEN System OSC is disabled in Stop modes System OSC is enabled in Stop modes if SOSCEN=1. System OSC Enable SOSCEN Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 384: System Osc Divide Register (Scg_Soscdiv)
Clock divider 2 for System OSC. Used by modules that need an asynchronous clock source. Output disabled Divide by 1 Divide by 2 Divide by 4 Divide by 8 Divide by 16 Divide by 32 Divide by 64 Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 385: System Oscillator Configuration Register (Scg_Sosccfg)
This bit is reserved. Software should write 0 to this bit field. 7–6 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 386 OSC (SOSC) into the SCG, thus either the crystal oscillator or from an external clock input External reference clock selected Internal crystal oscillator of OSC selected. Reserved This field is reserved. This read-only field is reserved and always has the value 0. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 387: Slow Irc Control Status Register (Scg_Sirccsr)
Slow IRC is not enabled or clock is not valid Slow IRC is enabled and output clock is valid Lock Register This bit field can be cleared/set at any time. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 388: Slow Irc Divide Register (Scg_Sircdiv)
15–11 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 10–8 Slow IRC Clock Divide 2 SIRCDIV2 Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 389: Slow Irc Configuration Register (Scg_Sirccfg)
The SIRCCFG register cannot be changed when the slow IRC clock is enabled. When the slow IRC clock is enabled, writes to this register are ignored, and there is no transfer error. Address: 4006_4000h base + 208h offset = 4006_4208h Reset Reset Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 390: Fast Irc Control Status Register (Scg_Firccsr)
Slow IRC low range clock (2 MHz) Slow IRC high range clock (8 MHz ) 18.3.13 Fast IRC Control Status Register (SCG_FIRCCSR) Address: 4006_4000h base + 300h offset = 4006_4300h Reset Reset Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 391 Fast IRC is enabled in Stop modes Fast IRC Enable FIRCEN If this bit written during clock switching, it should be read back and confirmed before proceeding. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 392: Fast Irc Divide Register (Scg_Fircdiv)
Clock divider 1 for Fast IRC. Used to generate the clock source for modules that need an asynchronous clock source. Output disabled Divide by 1 Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 393: Fast Irc Configuration Register (Scg_Firccfg)
See chip-specific information for supported frequency ranges. Fast IRC is trimmed to 48 MHz Fast IRC is trimmed to 52 MHz Fast IRC is trimmed to 56 MHz Fast IRC is trimmed to 60 MHz Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 394: Fast Irc Trim Configuration Register (Scg_Firctcfg)
This read-only field is reserved and always has the value 0. TRIMSRC Trim Source Configures the external clock source to tune the Fast IRC. TRMSRC must be configured before programming FIRCSTAT register for trim update Reserved Reserved System OSC Reserved Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 395: Fast Irc Status Register (Scg_Fircstat)
FIRC is enabled and auto trimming is enabled (FIRCTREN=1 and FIRCTRUP=1), TRIMFINE register gets uploaded with the trimmed fine value. When FIRCTRUP=0, TRIMFINE register is writeable, to allow user programming of fine trim values. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 396: Low Power Fll Control Status Register (Scg_Lpfllcsr)
Memory Map/Register Definition 18.3.18 Low Power FLL Control Status Register (SCG_LPFLLCSR) Address: 4006_4000h base + 500h offset = 4006_4500h Reset Reset Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 397 LPFLL Trim LOCK LPFLLTRMLOCK Asserts only when LPFLLTREN=1 and LPFLLTRUP=1 and LPFLL has locked to target frequency. LPFLL not Locked LPFLL trimmed and Locked Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 398: Low Power Fll Divide Register (Scg_Lpflldiv)
This bit field is reserved. Software should write 0 to this bit field to maintain compatibility. 15–11 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 399: Low Power Fll Configuration Register (Scg_Lpfllcfg)
SCG_LPFLLCFG field descriptions Field Description 31–2 This field is reserved. Reserved This read-only field is reserved and always has the value 0. FSEL Frequency Select Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 400: Low Power Fll Trim Configuration Register (Scg_Lpflltcfg)
LPFLL locks within 2LSB (0.8%) 15–13 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 12–8 LPFLL Trim Predivide TRIMDIV Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 401: Low Power Fll Status Register (Scg_Lpfllstat)
Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. AUTOTRIM Auto Tune Trim Status Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 402: Functional Description
• SOSCEN = 1 • SOSCVLD = 1 In SOSC mode, SCGCLKOUT and system clocks are derived from the external System Oscillator Clock (SOSC). Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 403 Stop recovery. Entering Stop mode, all SCG clock signals are static except the following clocks which can continue to run and stay enabled in the following cases: SIRCCLK is available in Normal Stop and VLPS mode when all the following conditions become true: Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 404 SOSCLK is available in following low power stop modes (Normal Stop, VLPS) when all the below conditions are true. • SOSCCSR[SOSCEN] = 1 • SOSCCSR[SOSCSTEN] = 1 • SOSCCSR[SOSCLPEN] = 1 (required only for Low Power Stop modes (VLPS) Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 405: Rtc Oscillator (Osc32)
• Automatic Gain Control (AGC) to optimize power consumption The RTC oscillator operations are described in detail in Functional Description 19.1.2 Block Diagram The following is the block diagram of the RTC oscillator. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 406: Rtc Signal Descriptions
19.2.1 EXTAL32 — Oscillator Input This signal is the analog input of the RTC oscillator. 19.2.2 XTAL32 — Oscillator Output This signal is the analog output of the RTC oscillator module. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 407: External Crystal Connections
(hex) 4006_0000 RTC Oscillator Control Register (OSC32_CR) 19.4.1/407 19.4.1 RTC Oscillator Control Register (OSC32_CR) Address: 4006_0000h base + 0h offset = 4006_0000h Read ROSCSTB ROSCEREF ROSCSTPE ROSCEN Write Reset Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 408: Functional Description
RTC digital core. The oscillator includes an internal feedback resistor of approximately 100 MΩ between EXTAL32 and XTAL32. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 409: Reset Overview
Chapter 19 RTC Oscillator (OSC32) 19.6 Reset Overview There is no reset state associated with the RTC oscillator. 19.7 Interrupts The RTC oscillator does not generate any interrupts. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 410 Interrupts Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 411: Peripheral Clock Controller (Pcc)
Stop, Doze, and Debug signals. 20.2.1 Features The PCC module enables software to configure the following clocking options for each peripheral: Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 412: Functional Description
Control and Config Registers Figure 20-1. PCC Clock Source Selection and Gating 20.3 Functional description The Peripheral Clock Control (PCC) module provides clock gating and clock source selection to each peripheral. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 413: Memory Map And Register Definition
PCC PDB0 (PCC_PDB0) 80000000h 400650DCh PCC LPIT0 (PCC_LPIT0) 80000000h 400650E0h PCC FLEXTMR0 (PCC_FLEXTMR0) 80000000h 400650E4h PCC FLEXTMR1 (PCC_FLEXTMR1) 80000000h 400650E8h PCC FLEXTMR2 (PCC_FLEXTMR2) 80000000h Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 414 80000000h 400651B0h PCC LPUART2 (PCC_LPUART2) 80000000h 400651CCh PCC CMP0 (PCC_CMP0) 80000000h 400651D0h PCC CMP1 (PCC_CMP1) 80000000h 20.4.1.2 PCC DMA0 (PCC_DMA0) 20.4.1.2.1 Address Register Offset PCC_DMA0 40065020h 20.4.1.2.2 Function PCC Register Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 415 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 416 This read-only bit field is reserved and always has the value 0. — 26-24 This read-only bit field is reserved and always has the value 0. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 417 Reset 20.4.1.4.3 Fields Field Function Enable This bit shows whether the peripheral is present on this device. 0 - Peripheral is not present. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 418 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 20.4.1.5 PCC ADC1 (PCC_ADC1) 20.4.1.5.1 Address Register Offset PCC_ADC1 4006509Ch PCC Register Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 419 101 - Low-power FLL (LPFLL) clock. 110 - Reserved. 111 - Reserved. 23-4 This read-only bit field is reserved and always has the value 0. — Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 420 This bit shows whether the peripheral is present on this device. 0 - Peripheral is not present. 1 - Peripheral is present. Clock Control This read/write bit enables the clock for the peripheral. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 421 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 20.4.1.7 PCC LPSPI1 (PCC_LPSPI1) 20.4.1.7.1 Address Register Offset PCC_LPSPI1 400650B4h PCC Register Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 422 101 - Low-power FLL (LPFLL) clock. 110 - Reserved. 111 - Reserved. 23-4 This read-only bit field is reserved and always has the value 0. — Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 423 This bit shows whether the peripheral is present on this device. 0 - Peripheral is not present. 1 - Peripheral is present. Clock Control This read/write bit enables the clock for the peripheral. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 424 This read-only bit field is reserved and always has the value 0. — 20.4.1.9 PCC PDB0 (PCC_PDB0) 20.4.1.9.1 Address Register Offset PCC_PDB0 400650D8h PCC Register 20.4.1.9.2 Diagram Bits INUS Reserved Reserved Reserved Reset Bits Rese Reserved Reserved rved Reset Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 425 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 20.4.1.10 PCC LPIT0 (PCC_LPIT0) 20.4.1.10.1 Address Register Offset PCC_LPIT0 400650DCh PCC Register Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 426 101 - Low-power FLL (LPFLL) clock. 110 - Reserved. 111 - Reserved. 23-4 This read-only bit field is reserved and always has the value 0. — Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 427 This bit shows whether the peripheral is present on this device. 0 - Peripheral is not present. 1 - Peripheral is present. Clock Control This read/write bit enables the clock for the peripheral. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 428 This read-only bit field is reserved and always has the value 0. — 20.4.1.12 PCC FLEXTMR1 (PCC_FLEXTMR1) 20.4.1.12.1 Address Register Offset PCC_FLEXTMR1 400650E4h PCC Register 20.4.1.12.2 Diagram Bits INUS Reserved Reserved Reserved Reset Bits Rese Reserved Reserved rved Reset Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 429 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 20.4.1.13 PCC FLEXTMR2 (PCC_FLEXTMR2) 20.4.1.13.1 Address Register Offset PCC_FLEXTMR2 400650E8h PCC Register Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 430 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 431 1 - Peripheral is being used. Software cannot modify the existing clocking configuration. 28-27 This read-only bit field is reserved and always has the value 0. — 26-24 Peripheral Clock Source Select Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 432 This read-only bit field is reserved and always has the value 0. — 20.4.1.15 PCC RTC (PCC_RTC) 20.4.1.15.1 Address Register Offset PCC_RTC 400650F4h PCC Register 20.4.1.15.2 Diagram Bits INUS Reserved Reserved Reserved Reset Bits Reserved Reset Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 433 This read-only bit field is reserved and always has the value 0. — 23-0 This read-only bit field is reserved and always has the value 0. — 20.4.1.16 PCC LPTMR0 (PCC_LPTMR0) 20.4.1.16.1 Address Register Offset PCC_LPTMR0 40065100h PCC Register Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 434 011 - Fast IRC Clock. 100 - Reserved. 101 - Low-power FLL (LPFLL) clock. 110 - Reserved. 111 - Reserved. 23-0 This read-only bit field is reserved and always has the value 0. — Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 435 1 - Peripheral is being used. Software cannot modify the existing clocking configuration. 28-27 This read-only bit field is reserved and always has the value 0. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 436 Reserved Reset Bits Rese Reserved Reserved rved Reset 20.4.1.18.3 Fields Field Function Enable This bit shows whether the peripheral is present on this device. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 437 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 20.4.1.19 PCC PORTB (PCC_PORTB) 20.4.1.19.1 Address Register Offset PCC_PORTB 40065128h PCC Register Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 438 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 439 This read-only bit field is reserved and always has the value 0. — 26-24 This read-only bit field is reserved and always has the value 0. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 440 Reset 20.4.1.21.3 Fields Field Function Enable This bit shows whether the peripheral is present on this device. 0 - Peripheral is not present. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 441 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 20.4.1.22 PCC PORTE (PCC_PORTE) 20.4.1.22.1 Address Register Offset PCC_PORTE 40065134h PCC Register Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 442 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 443 This read-only bit field is reserved and always has the value 0. — 26-24 This read-only bit field is reserved and always has the value 0. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 444 Reset 20.4.1.24.3 Fields Field Function Enable This bit shows whether the peripheral is present on this device. 0 - Peripheral is not present. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 445 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 20.4.1.25 PCC OSC32 (PCC_OSC32) 20.4.1.25.1 Address Register Offset PCC_OSC32 40065180h PCC Register Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 446 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 447 This read-only bit field is reserved and always has the value 0. — 26-24 This read-only bit field is reserved and always has the value 0. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 448 Reset 20.4.1.27.3 Fields Field Function Enable This bit shows whether the peripheral is present on this device. 0 - Peripheral is not present. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 449 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 20.4.1.28 PCC LPI2C1 (PCC_LPI2C1) 20.4.1.28.1 Address Register Offset PCC_LPI2C1 4006519Ch PCC Register Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 450 101 - Low-power FLL (LPFLL) clock. 110 - Reserved. 111 - Reserved. 23-4 This read-only bit field is reserved and always has the value 0. — Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 451 This bit shows whether the peripheral is present on this device. 0 - Peripheral is not present. 1 - Peripheral is present. Clock Control This read/write bit enables the clock for the peripheral. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 452 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 20.4.1.30 PCC LPUART1 (PCC_LPUART1) 20.4.1.30.1 Address Register Offset PCC_LPUART1 400651ACh PCC Register Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 453 101 - Low-power FLL (LPFLL) clock. 110 - Reserved. 111 - Reserved. 23-4 This read-only bit field is reserved and always has the value 0. — Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 454 This bit shows whether the peripheral is present on this device. 0 - Peripheral is not present. 1 - Peripheral is present. Clock Control This read/write bit enables the clock for the peripheral. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 455 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — 20.4.1.32 PCC CMP0 (PCC_CMP0) 20.4.1.32.1 Address Register Offset PCC_CMP0 400651CCh PCC Register Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 456 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 457 This read-only bit field is reserved and always has the value 0. — 26-24 This read-only bit field is reserved and always has the value 0. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 458 This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — This read-only bit field is reserved and always has the value 0. — Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 459: Reset And Boot
The MCU exits reset in functional mode where the CPU is executing code. See Boot options for more details. The following figure shows a block diagram of the reset sources for this device. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 460: Reset
System reset begins with the on-chip regulator in full regulation and system clocking generation from an internal reference. When the processor exits reset, it performs the following: • Reads the start SP (SP_main) from vector-table offset 0 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 461 (POR) circuit and an LVD circuit. The LVD system can always be enabled in normal Run, or Wait mode. The LVD system is disabled (LVR active only) when entering VLPx modes or Stop mode. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 462 The SCG module contains a loss-of-lock detector, to indicate a reset has been caused by a loss of lock in the SCG PLL/FLL. NOTE This reset source does not cause a reset if the chip is in VLPR/ VLPW/VLPS mode. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 463: Mcu Resets
Set the core hold reset bit in the MDM-AP control register to hold the core in reset as the rest of the chip comes out of system reset. 21.2.3 MCU Resets A variety of resets are generated by the MCU to reset different modules. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 464: Reset Pin
Chip Reset negates after the RESET_b pin is pulled high. Keeping the RESET_b pin asserted externally delays the negation of the internal Chip Reset. 21.3 Boot This section describes the boot sequence, including sources and options. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 465: Boot Options
MDM-AP register. RESET_b pin is dedicated. The port is configured with pullup enabled, open drain, passive filter enabled. NMI_DIS Enables/disables control for the NMI function. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 466 The boot source remains set until the next System Reset or software can write logic one to clear one or both of the mode bits. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 467: Boot Sequence
EEERDY flag. Subsequent system resets follow this same reset flow. The following figure shows the boot sequence. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 468 Flash reset 22~50us end system reset System reset release driving RESET pin Reset_b Core start ftfx initialization complete release core hold FOPT load IFR(include FOPT) load Figure 21-2. Boot Sequence Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 469: Kinetis Rom Bootloader
Visit nxp.com/KPYW for more details. NOTE For this device, ROM does not check the flash FAC function. So it is not recommended to access memory protected by FAC via ROM. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 470: Introduction
This chapter describes Kinetis Bootloader features, functionality, command structure and which peripherals are supported. Features supported by the Kinetis Bootloader in Kinetis ROM: Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 471: Functional Description
Erase the entire flash array, including protected Supported sectors 22.3 Functional Description The following sub-sections describe the Kinetis Bootloader in ROM functionality. 22.3.1 Memory Maps While executing, the Kinetis Bootloader uses ROM and RAM memory. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 472: The Kinetis Bootloader Configuration Area (Bca)
Bitfield of peripherals to enable. bit 0 LPUART bit 1 LPI2C bit 2 LPSPI Kinetis bootloader will enable the peripheral if corresponding bit is set to Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 473 The tag value is treated as a character string, so bytes 0-3 must be set as shown in the table. Table 22-3. tag Configuration Field Offset tag Byte Value 'k' (0x6B) 'c' (0x63) 'f' (0x66) 'g' (0x67) Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 474: Start-Up Process
'kcfg' value. If the tag is incorrect, then the configuration values are set to default, as if the data was all 0xFF bytes. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 475 The flash sector containing the vector table should not be located in the execute-only region, because the Kinetis bootloader cannot read the PC and SP addresses in an execute-only region. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 476: Clock Configuration
• Alternate clock configurations are supported, by setting fields in the Bootloader Configuration Area (BCA) shown in Table 22-2. • If the HighSpeed flag of the clockFlags configuration value is cleared, the bootloader will enable the internal 48 MHz reference clock. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 477: Bootloader Entry Point / Api Tree
Example: code to get the entry pointer address from the ROM and start the bootloader. NOTE This entry must be called in supervisor (privileged) mode. // Variables Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 478: Bootloader Protocol
Command/Data packet has processed. 22.3.6.1 Command with no data phase The protocol for a command with no data phase contains: • Command packet (from host) • Generic response command packet (to host) Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 479 The protocol for a command with an incoming data phase contains: • Command packet (from host) • Generic response command packet (to host) • Incoming data packets (from host) • Generic response command packet (to host) Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 480 • Data phases may be aborted by the receiving side by sending the final Generic Response early with a status of Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 481: Bootloader Packet Types
A Ping packet must be sent before any other communications. In response to a Ping packet, the target sends a Ping Response packet. Table 22-5. Ping Packet Format Byte # Value Name 0x5A start byte 0xA6 ping Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 482 Byte # Value Parameter 0x5A start byte 0xA7 Ping response code Protocol bugfix Protocol minor Protocol major Protocol name = 'P' (0x50) Options low Options high CRC16 low CRC16 high Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 483 The framing packet contains a data packet payload. 0xA6 kFramingPacketType_Ping Sent to verify the other side is alive. Also used for UART autobaud. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 484 Table 22-12. Commands that are supported Command Name 0x01 FlashEraseAll 0x02 FlashEraseRegion 0x03 Reserved Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 485 The data transfer direction is determined by the last command sent from the host. The data packet is also wrapped within a framing packet, to ensure the correct packet data is received. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 486 The parameter count field in the header is set to greater than 1, to always include the status code and one or many property values. Table 22-15. GetPropertyResponse Parameters Byte # Value Parameter 0 - 3 Status code Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 487: Bootloader Command Api
Table 22-16. Parameters for Execute Command Byte # Command 0 - 3 Jump address 4 - 7 Argument word 8 - 11 Stack pointer address The Execute command has no data phase. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 488 0x5A packetType 0xA4, kFramingPacketType_Command length 0x04 0x00 crc16 0x6F 0x46 Command packet commandTag 0x0B - reset flags 0x00 reserved 0x00 parameterCount 0x00 The Reset command has no data phase. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 489 Generic Response: 0x5a a4 0c 00 07 7a a7 00 00 02 00 00 00 00 00 00 01 4 b ACK: 0x5a a1 Figure 22-7. Protocol Sequence for GetProperty Command Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 490 0x5A packetType 0xA4, kFramingPacketType_Command length 0x0c 0x00 (12 bytes) crc16 0x07 0x7a Command packet responseTag 0xA7 flags 0x00 reserved 0x00 parameterCount 0x02 status 0x00000000 propertyValue 0x0000014b - CurrentVersion Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 491 0x5A packetType 0xA4, kFramingPacketType_Command length 0x0C 0x00 crc16 0x67 0x8D Command packet commandTag 0x0C – SetProperty with property tag 10 flags 0x00 Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 492 The Command tag for FlashEraseAll command is 0x01 set in the commandTag field of the command packet. The FlashEraseAll command requires no parameters. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 493 22.3.8.6 FlashEraseRegion command The FlashEraseRegion command performs an erase of one or more sectors of the flash memory or a specified range of flash within the connected SPI flash devices. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 494 0x0C 0x00 crc16 0xF9 0x A6 Command packet commandTag 0x02, kCommandTag_FlashEraseRegion flags 0x00 reserved 0x00 parameterCount 0x02 startAddress 0x00 0x00 0x00 0x00 (0x0000_0000) byte count 0x00 0x04 0x00 0x00 (0x400) Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 495 Generic Response: 0x5a a4 0c 00 61 2c a0 00 04 02 00 00 00 00 0d 00 00 00 ACK: 0x5a a1 Figure 22-11. Protocol Sequence for FlashEraseAll Command Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 496 The backdoor low and high words are the only parameters required for FlashSecurityDisable command. Table 22-29. Parameters for FlashSecurityDisable Command Byte # Command 0 - 3 Backdoor key low word 4 - 7 Backdoor key high word Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 497 The WriteMemory command writes data provided in the data phase to a specified range of bytes in memory (flash or RAM). However, if flash protection is enabled, then writes to protected sectors will fail. Special care must be taken when writing to flash. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 498 The start address and number of bytes are the 2 parameters required for WriteMemory command. Table 22-31. Parameters for WriteMemory Command Byte # Command 0 - 3 Start address 4 - 7 Byte count Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 499 Framing packet start byte 0x5A packetType 0xA4, kFramingPacketType_Command length 0x0C 0x00 crc16 0x06 0x5A Command packet commandTag 0x04 - writeMemory flags 0x00 reserved 0x00 parameterCount 0x02 startAddress 0x20000400 byteCount 0x00000064 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 500: Bootloader Exit State
The MCU ROM bootloader provides a flash driver API tree entry (flashDriver) that a user application can use to get the entry points for the whole flash API set that is supported by the bootloader. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 501: Flash Driver Api Tree
} B; uint32_t version; //!lt; combined version numbers } standard_version_t; //! @brief Interface for the flash driver. typedef struct FlashDriverInterface #if !defined(FLASH_API_TREE_1_0) standard_version_t version; //!lt; flash driver API version number. #endif Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 502: Quick Demo Using Kinetis Flash Driver Api
For more code examples, get the latest Kinetis bootloader package at http:// www.nxp.com/KBOOT/ bootloader_tree_t* tree; // pointer points to bootloader tree flash_config_t flash_config; // variable used to keep runtime state of flash driver Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 503: Flash Driver Data Structures
• FlexNVM device: FlexNVM memory total size • non-FlexNVM device: unused EEpromTotalSize • FlexNVM device: the size (in bytes) of the EEPROM area that was partitioned from FlexRAM • non-FlexNVM device: unused Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 504: Flash Driver Api
This section describes each function supported in the flash driver API. 22.4.5.1 FLASH_Init Checks and initializes the flash module for the other flash API functions. NOTE FLASH_Init must be always called before calling other API functions. Prototype: Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 505 Config pointer is NULL. kStatus_FLASH_AccessError Command is not available under current mode/ security. kStatus_FLASH_ProtectionViolation Any region of the program flash memory is protected. kStatus_FLASH_EraseKeyError Key is incorrect. kStatus_Success This function has performed successfully. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 506 This function has performed successfully. Example: status_t status = FLASH_EraseAllUnsecure(&flashInstance, kFLASH_ApiEraseKey); 22.4.5.4 FLASH_Erase Erases expected flash sectors specified by parameters. For Kinetis devices, the minimum erase unit is one sector. Prototype: Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 507 FLASH_Program(flash_config_t *config, uint32_t start, uint32_t *src, uint32_t lengthInBytes); Table 22-43. Parameters Parameter Description Config Pointer to flash_config_t data structure in memory, to store driver runtime state. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 508 Prototype: status_t FLASH_GetSecurityState(flash_config_t *config, flash_security_state_t *state); Table 22-45. Parameters Parameters Description Config Pointer to flash_config_t data structure in memory, to store driver runtime state. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 509 FLASH_SecurityBypass(flash_config_t *config, const uint8_t *backdoorKey); Table 22-48. Parameters Parameter Description Config Pointer to flash_config_t data structure in memory, to store driver runtime state. backdoorKey Pointer to the user buffer containing the backdoor key. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 510 • kFLASH_MarginValueNormal 0 • kFLASH_MarginValueUser 1 • kFLASH_MarginValueFactory 2 Table 22-51. Possible status response Value Constant Description kStatus_InvalidArgument Config or backdoorKey pointers are NULL. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 511 The start address of the desired flash memory to be verified. lengthInBytes The length, given in bytes (not words or long words) to be verified. Must be word-aligned. margin Read margin choice as follows: kFLASH_MarginValueNormal 0 kFLASH_MarginValueUser 1 kFLASH_MarginValueFactory 2 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 512 Command), and compares it with expected data for a given flash area (as determined by the start address and length). FLASH_VerifyProgram is often called after successfully doing FLASH_Program(). Prototype: status_t FLASH_VerifyProgram(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, const uint32_t *expectedData, Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 513 = FLASH_VerifyProgram (&flashInstance, 0x800, 8, &expectedData[0], kFlashMargin_User, NULL, NULL); NOTE For the choice of margin, see the FTFA chapter in the reference manual for detailed information. 22.4.5.11 FLASH_GetProperty Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 514 = FLASH_GetProperty (&flashInstance, kFLASH_PropertyPflashSectorSize, &propertyValue); 22.4.5.12 FLASH_ProgramOnce Programs a certain Program Once Field with the expected data for a given IFR region (as determined by the index and length). Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 515 Assume the Program Once Field has not been programmed before. uint32_t expectedData = 0x78563412; status_t status = FLASH_ProgramOnce(&flashInstance, 0, &expectedData, 4); NOTE For the choice of index and length, see the FTFA chapter in RM for detailed information. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 516 This function has performed successfully. Example: uint32_t temp; status_t status = FLASH_ReadOnce(&flashInstance, 0, &temp, 4); NOTE For the choice of index and length, see the FTFA chapter in RM for detailed information. 22.4.5.14 FLASH_ReadResource Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 517 This function has performed successfully. Example: uint32_t temp[256]; status_t status = FLASH_ReadResource(&flashInstance, 0, &temp[0], 256, 0); NOTE See the FTFA chapter in RM for detailed information regarding the start, length, and option choices. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 518: Peripherals Supported
The Kinetis Bootloader in ROM supports loading data into flash via the I2C peripheral, where the I2C peripheral serves as the I2C slave. A 7-bit slave address is used during the transfer. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 519 Read 1 byte packet from target Read 1 byte 0x7A 0x5A Report Error received? received? from target Figure 22-14. Host reads ping response from target via I2C Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 520: Spi Peripheral
Figure 22-16. Host reads response from target via I2C 22.5.2 SPI Peripheral The Kinetis Bootloader in ROM supports loading data into flash via the SPI peripheral, where the SPI peripheral serves as a SPI slave. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 521 "dummy" 0x00 bytes (which do not have framing packets). The following flowcharts demonstrate how the host reads a ping response, an ACK and a command response from target via SPI. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 522 Send 0x00 to 0x5A 0xA1 shift out 1 byte received? received? from target Report a Next action timeout error Figure 22-18. Host reads ACK from target via SPI Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 523: Uart Peripheral
(8-bit data, no parity bit and 1 stop bit). If the bytes of the ping packet are sent one-by-one with more than 80 ms delay between them, then the autobaud Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 524 Reached Wait for 1 byte 0x5A 0xA1 maximum received? received? from target retries? Report a timeout error Figure 22-20. Host reads an ACK from target via UART Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 525: Get/Setproperty Command Properties
Table 22-67. Properties used by Get/SetProperty Commands, sorted by Value Property Writable Tag Value Size Description CurrentVersion Current bootloader version. AvailablePeripherals The set of peripherals supported on this chip. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 526 Identification registers (16 for K series devices, 12 for KL series devices) FacSupport FAC (Flash Access Control) support flag 0 - FAC not supported Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 527: Property Definitions
Reserved SPI Slave I2C Slave UART If the peripheral is available, then the corresponding bit will be set in the property value. All reserved bits must be set to 0. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 528: Kinetis Bootloader Status Error Codes
Requested value cannot be changed because it is read-only. kStatus_OutOfRange Requested value is out of range. kStatus_InvalidArgument The requested command's argument is undefined. kStatus_Timeout A timeout occurred. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 529 The call command in the SB file failed. kStatusRomLdrKeyNotFound 10112 A matching key was not found in the SB file's key dictionary to unencrypt the section. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 530 CRC check is invalid, because the BCA is invalid or the CRC parameters are unset (all 0xFF bytes). kStatus_AppCrcCheckOutOfRange 10404 CRC check is valid but addresses are out of range. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 531: Chip-Specific Information For This Module
RCM implements many of the reset functions for the chip. See the chip's reset chapter for more information. AN4503: Power Management for Kinetis and ColdFire+ MCUs for further details on using the RCM. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 532: Reset Memory Map And Register Descriptions
Field Description 31–24 Major Version Number MAJOR This read only field returns the major version number for the specification. 23–16 Minor Version Number MINOR Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 533 Description This read only field returns the minor version number for the specification. FEATURE Feature Specification Number This read only field returns the feature set number. 0x0003 Standard feature set. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 534: Parameter Register (Rcm_Param)
31–17 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Existence of SRS[CORE1] status indication feature ECORE1 Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 535 The feature is available. Existence of SRS[WDOG] status indication feature EWDOG This static bit states whether or not the feature is available on the device. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 536: System Reset Status Register (Rcm_Srs)
The reset value of this register depends on the reset source: • POR (including LVD) — 0x82 • LVD (without POR) — 0x02 • Other reset — a bit is set if its corresponding reset source caused the reset Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 537 Reset caused by peripheral failure to acknowledge attempt to enter stop mode This field is reserved. Reserved This read-only field is reserved and always has the value 0. MDM-AP System Reset Request MDM_AP Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 538 Indicates a reset has been caused by a loss of lock in the SCG PLL/FLL. Reset not caused by a loss of lock in the PLL/FLL Reset caused by a loss of lock in the PLL/FLL Loss-of-Clock Reset Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 539: Reset Pin Control Register (Rcm_Rpc)
The bus clock filter is reset when disabled or when entering stop mode. The LPO filter is reset when disabled. Address: 4007_F000h base + Ch offset = 4007_F00Ch Reset RSTFLTSR RSTFLTSEL Reset Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 540: Mode Register (Rcm_Mr)
This register includes status flags to indicate the state of the mode pins during the last Chip Reset. Address: 4007_F000h base + 10h offset = 4007_F010h Reset BOOTROM Reset * Notes: • BOOTROM field: The reset state of this register depends on the boot mode. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 541: Force Mode Register (Rcm_Fm)
When either bit is set, will force boot from ROM during all subsequent system resets. No effect Force boot from ROM with RCM_MR[1] set. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 542: Sticky System Reset Status Register (Rcm_Ssrs)
Software can clear the status flags by writing a logic one to a flag. Address: 4007_F000h base + 18h offset = 4007_F018h Reset Reset Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 543 Reset caused by POR Sticky External Reset Pin SPIN Indicates a reset has been caused by an active-low level on the external RESET (RESET_b) pin. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 544: System Reset Interrupt Enable Register (Rcm_Srie)
The SRS updates only after the system reset occurs. NOTE This register is reset on Chip POR only, it is unaffected by other reset types. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 545 NOTE: The LOCKUP bit is useful only in devices with more than one core processor. Interrupt disabled. Interrupt enabled. This field is reserved. Reserved This read-only field is reserved and always has the value 0. Global Interrupt Enable Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 546 Reset Delay Time Configures the maximum reset delay time from when the interrupt is asserted and the system reset occurs. 10 LPO cycles 34 LPO cycles 130 LPO cycles 514 LPO cycles Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 547: Introduction
Following stated are general power modes, which are supported additionally by certain clocking mode options. Clock gating technique is used for general power modes and for the additional clocking mode options. Figure 24-1. Power Infrastructure Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 548: Power Modes Description
VLPS (Very Low Same as Stop mode, but PMC_REGSC register provides options to Sleep Deep Interrupt Power Stop)-via gate off unused modules and further reduce power in low power mode. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 549: Run Mode
Compute Operation, including generation of asynchronous interrupts and DMA requests. When enabling Compute Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 550: Wait Mode
Wait mode refers to a power modes in which the CPU execution is halted. The core clock is gated off. The system clock continues to operate. Bus clocks, if enabled, continue to operate. Depending on the on-chip regulator settings, Wait mode has the following configurations: Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 551: Stop Mode
The clock generators in the SCG and the on-chip regulator in the PMC also remain in Run (or VLP Run) mode. Exit from PSTOP2 can be initiated by a reset, an asynchronous Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 552 Stop mode and then requesting bus slaves to enter Stop mode. In STOP and VLPS modes, SCG and PMC would then also enter their appropriate modes. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 553: Power Domains
1.2V domain is powered by the PMC 1.2V regulator. It contains all digital logics and SRAM. Table 24-3. Module power domain summary VDD (5V) GPIOx (all ports) VDDA ADCx CMPx 3V CORE Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 554: Entering And Exiting Power Modes
In run, wait, and stop modes active power regulation is enabled. The VLPx modes offer a lower power operating mode than normal modes. VLPR and VLPW are limited in frequency. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 555: Power Modes Shutdown Sequencing
• System level wait and VLPW modes equate to: SLEEPING & SLEEPDEEP • All other low power modes equate to: SLEEPING & SLEEPDEEP When entering the non-wait modes, the chip performs the following sequence: Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 556: Module Operation In Low Power Modes
• static = Module register states and associated memories are retained. • powered = Memory is powered to retain contents. • low power = Memory is powered to retain contents in a lower power state Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 557 SRAM_L) FlexMemory low power low power low power low power Communication interfaces LPUART Async operation Async operation Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 558 3. CMP in stop or VLPS supports low speed external pin to pin or external pin to DAC compares. Windowed, sampled and filtered modes of operation are not available while in stop or VLPS modes. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 559: Peripheral Doze
Flash Doze mode can be used to reduce power consumption, at the expense of a slightly longer wake-up when executing code and vectors from flash. It can also be used to reduce power consumption during Compute Operation when executing code and vectors from SRAM. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 560: Low-Power Wake-Up Sources
Functional in Stop mode Reset wakeup Touch sense wakeup Non-maskable interrupt 24.7 Power supply supervisor This device integrates the following power supervisor circuits: • Power-on reset (POR) • Low voltage detection (LVD) Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 561 See PMC chapters for details. For more details on the POR/LVD reset and the LVW interrupt thresholds, see the electrical characteristics section in the Data Sheet. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 562 Power supply supervisor Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 563: Introduction
Stop are the common terms used for the primary operating modes of Kinetis microcontrollers. The following table shows the translation between the Arm CPU modes and the Kinetis MCU power modes. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 564 VLPS The core clock is gated off. System clocks to other masters and bus clocks are gated off after all stop acknowledge signals from supporting peripherals are valid. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 565: Memory Map And Register Descriptions
Stop Control Register (SMC_STOPCTRL) 0000_0003h 25.3.5/570 4007_E014 Power Mode Status register (SMC_PMSTAT) 0000_0001h 25.3.6/572 25.3.1 SMC Version ID Register (SMC_VERID) Address: 4007_E000h base + 0h offset = 4007_E000h MAJOR MINOR FEATURE Reset Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 566: Smc Parameter Register (Smc_Param)
Feature Specification Number This read only field returns the feature set number. 0x0000 Standard features implemented 25.3.2 SMC Parameter Register (SMC_PARAM) Address: 4007_E000h base + 4h offset = 4007_E004h Reset Reset Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 567: Power Mode Protection Register (Smc_Pmprot)
For example, if the MCU is in normal RUN mode and AVLP is 0, an attempt to enter VLPR mode using PMCTRL[RUNM] is blocked and PMCTRL[RUNM] remains 00b, indicating the MCU is still in Normal Run mode. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 568 This field is reserved. Reserved This read-only field is reserved and always has the value 0. This field is reserved. Reserved This read-only field is reserved and always has the value 0. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 569: Power Mode Control Register (Smc_Pmctrl)
When written, causes entry into the selected run mode. Writes to this field are blocked if the protection level has not been enabled using the PMPROT register. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 570: Stop Control Register (Smc_Stopctrl)
This register is reset on Chip POR and by reset types that trigger Chip POR. It is unaffected by reset types that do not trigger Chip POR. See the Reset section details for more information. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 571 This bit is reserved for future expansion. Software should write 0 to this bit to maintain compatibility. Reserved This field is reserved. This read-only field is reserved and always has the value 0. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 572: Power Mode Status Register (Smc_Pmstat)
0000_0010 Current power mode is STOP. 0000_0100 Current power mode is VLPR. 0000_1000 Current power mode is VLPW. 0001_0000 Current power mode is VLPS. 0010_0000 Reserved 0100_0000 Reserved 1000_0000 Reserved 25.4 Functional description Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 573: Power Mode Transitions
Interrupt or Reset STOP PMCTRL[RUNM]=00, PMCTRL[STOPM]=000 Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in Arm core. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 574: Power Mode Entry/Exit Sequencing
PMCTRL[STOPM]=000 and STOPCTRL[PSTOPO]=01 or 10, then only a Partial Stop mode is entered instead of VLPS 25.4.2 Power mode entry/exit sequencing When entering or exiting low-power modes, the system must conform to an orderly sequence to manage transitions safely. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 575 Stop mode. 4. After all slaves have acknowledged they are ready to enter Stop mode, all system and bus clocks are gated off. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 576: Run Modes
Halted state when the debugger has been enabled. As part of this transition, system clocking is re-established and is equivalent to the normal RUN and VLPR mode clocking configuration. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 577 In addition, do not modify the clock source in the SCG module or any clock divider registers. Module clock enables in the PCC can be set, but not cleared. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 578: Wait Modes
To further reduce power in this mode, disable the clocks to unused modules. VLPR mode restrictions also apply to VLPW. When an interrupt from VLPW occurs, the device returns to VLPR mode to execute the interrupt service routine. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 579: Stop Modes
A system reset will cause an exit from STOP mode, returning the device to normal RUN mode via an MCU reset. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 580: Debug In Low Power Modes
• the SCG-generated clock source is enabled, • all system clocks, except the core clock, are disabled, • the debug module has access to core registers, and • access to the on-chip peripherals is blocked. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 581: Chip-Specific Information For This Module
• Low voltage reset (LVR) • Low voltage detect supporting two low voltage trip points and interrupt • Low power oscillator (LPO) with a typical frequency of 128 kHz 26.4 Modes of Operation Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 582: Full Performance Mode (Fpm)
If the supply voltage falls below the reset trip point (V ), a system reset will be generated. If PMC_LVDSC1[LVDRE] is set and the supply voltage falls below V , a system reset will be generated. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 583: Lvd Interrupt Operation
Each register's description provides details. NOTE The PMC registers can be written only in supervisor mode. Write accesses in user mode are blocked and will result in a bus error. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 584: Low Voltage Detect Status And Control 1 Register (Pmc_Lvdsc1)
This write-only bit is used to acknowledge low voltage detection errors. Write 1 to clear LVDF. Read always return 0. Low Voltage Detect Interrupt Enable LVDIE Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 585: Low Voltage Detect Status And Control 2 Register (Pmc_Lvdsc2)
Low-Voltage Warning Acknowledge LVWACK This write-only bit is used to acknowledge low voltage warning errors. Write 1 to clear LVWF. Reads always return 0. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 586: Regulator Status And Control Register (Pmc_Regsc)
Low power oscillator in low phase Low power oscillator in high phase 5–3 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 587: Low Power Oscillator Trim Register (Pmc_Lpotrim)
Table 26-1. Trimming effect of LPOTRIM[4:0] LPOTRIM[4:0] Decimal Period of LPO clock 10000 –16 lowest 10001 –15 increasing 11110 –2 11111 –1 00000 typical 128 kHz 00001 increasing 01110 01111 highest Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 588 This read-only field is reserved and always has the value 0. LPOTRIM LPO trimming bits These bits are used for trimming the frequency of the low power oscillator. See the table above for trimming effect. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 589: Introduction
MCU after presenting the correct backdoor key with Verify Backdoor Access Key command. The MEEN bit of FSEC byte can be used to disable the mass erase capability from debug port and the FlashEraseAllUnsecure command from ROM bootloader. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 590: Flash Access Protection (Fac)
FTFE chapter for more details. 27.3 Security hardware accelerators 27.3.1 CRC This device contain one cyclic redundancy check (CRC) module which can generates 16/32-bit CRC code for error detection. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 591: General Security Features
0x00 ~ 0x07. The data can no longer be erased nor modified after programming. The Program Once Field can be read through Read Once commands. Please refer to Program Once field section in the FTFE chapter for more details. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 592 General security features Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 593: Introduction
• Independent LPO_CLK clock source • Programmable time-out period specified in terms of number of EWM LPO_CLK clock cycles. • Windowed refresh option • Provides robust check that program flow is faster than expected. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 594: Modes Of Operation
EWM refresh instructions. 28.1.2.2 Wait Mode The EWM module treats the stop and wait modes as the same. EWM functionality remains the same in both of these modes. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 595: Block Diagram
Cell Reset to Enable Counter Reset EWM_CLKPRESCALER[CLK_DIV] EWM_CTRL[EWMEN] EWM Refreshed Counter overflow EWM Refresh EWM_CMPH[COMPAREH] EWM_out /EWM_out Output EWM_CMPL[COMPAREL] Control EWM_in Mechanism EWM Service Register Figure 28-1. EWM Block Diagram Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 596: Ewm Signal Descriptions
INEN, ASSIN and EWMEN bits can be written once after a CPU reset. Modifying these bits more than once, generates a bus transfer error. Address: 4006_1000h base + 0h offset = 4006_1000h Read INTEN INEN ASSIN EWMEN Write Reset Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 597: Service Register (Ewm_Serv)
This fixed number of cycles is called EWM_refresh_time. 28.3.3 Compare Low Register (EWM_CMPL) The CMPL register is reset to zero after a CPU reset. This provides no minimum time for the CPU to refresh the EWM counter. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 598: Compare High Register (Ewm_Cmph)
Field Description COMPAREH To prevent runaway code from changing this field, software should write to this field after a CPU reset even if the (default) maximum refresh time is required. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 599: Clock Prescaler Register (Ewm_Clkprescaler)
The EWM_out is a digital output signal used to gate an external circuit (application specific) that controls critical safety functions. For example, the EWM_out could be connected to the high voltage transistors circuits that control an AC motor in a large appliance. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 600: The Ewm_In Signal
(setting the CTRL[INEN] bit), the EWM_in signal must be in the deasserted state prior to the CPU start refreshing the EWM. This ensures that the EWM_out stays in the deasserted state; otherwise, the EWM_out output signal is asserted. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 601: Ewm Counter
EWM Service Register. The CPU must access the EWM service register with correct write of unique data within the windowed time frame as determined by the CMPL and CMPH registers for correct EWM refresh operation. Therefore, three possible conditions can occur: Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 602: Ewm Interrupt
The divided clock used to run the EWM counter must be no more than half the frequency of the bus clock. 28.5 Usage Guide 28.5.1 EWM low-power modes This table shows the EWM low-power modes and the corresponding chip low-power modes. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 603: Ewm_Out Pin State In Low Power Modes
The following code segment shows the refresh write sequence of the EWM module. // Refresh EWM DisableInterrupts; // disable global interrupt EWM_SERV= 0xB4; // write the 1st refresh words EWM_SERV= 0x2C; // write the 2nd refresh words EnableInterrupts; // enable global interrupt Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 604 Usage Guide Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 605: Chip-Specific Information For This Module
Peripheral Interface Clock BUS_CLK SCG DIVSLOW Registers WDOG_CS[CLK] LPO_CLK SOSC_CLK SOSC SIRC SIRC_CLK 29.1.2 WDOG low-power modes This table shows the WDOG low-power modes and the corresponding chip low-power modes. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 606: Introduction
• Programmable 16-bit window value • Provides robust check that program flow is faster than expected • Early refresh attempts trigger a reset. • Optional timeout interrupt to allow post-processing diagnostics Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 607: Block Diagram
SCG) 0xC520 128 Bus Cycle Control Status 16-bit Window Register Disable Protect Bit Write Control 0xD928 UPDATE PRES WIN Figure 29-1. WDOG block diagram 29.3 Memory map and register definition Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 608: Watchdog Control And Status Register (Wdog_Cs)
DBG WAIT STOP Reset WDOG_CS field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 609 System oscillator clock (SOSC, from SCG) Slow internal reference clock (SIRC, from SCG) Watchdog Enable This write-once bit enables the watchdog counter to start counting. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 610 Stop Enable STOP This write-once bit enables the watchdog to operate when the chip is in stop mode. Watchdog disabled in chip stop mode. Watchdog enabled in chip stop mode. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 611: Watchdog Counter Register (Wdog_Cnt)
The watchdog counter (CNT) is continuously compared with the timeout value (TOVAL). If the counter reaches the timeout value, the watchdog forces a reset triggering event. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 612: Watchdog Window Register (Wdog_Win)
31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 15–8 High byte of Watchdog Window WINHIGH WINLOW Low byte of Watchdog Window Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 613: Functional Description
Pass through 125 ns–8.1925 ms Internal 8 MHz (SIRC) ÷256 32 µs–2.09728 s 1 MHz (from bus or external) Pass through 1 µs–65.54 ms Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 614: Watchdog Refresh Mechanism
In addition, if window mode is used, software must not start the refresh sequence until after the time value set in the WIN register. See the following figure. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 615 The refresh write sequence can be • either two 16-bit writes ( 0xA602, 0xB480) or four 8-bit writes (0xA6, 0x02, 0xB4, 0x80) if WDOG_CS[CMD32EN] is 0; • one 32-bit write (0xB480_A602) if WDOG_CS[CMD32EN] is 1. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 616: Configuring The Watchdog
• Conversely, if CS[UPDATE] remains 0, the only way to reconfigure the watchdog is by initiating a reset. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 617: Using Interrupts To Delay Resets
WDOG logic loses its clock (the bus clock) and can no longer monitor the counter. If the watchdog counter overflows twice in succession (without an intervening reset), the backup reset function takes effect and generates a reset. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 618: Functionality In Debug And Low-Power Modes
(such as the bus clock) for the counter reference. On a power-on reset, the POR bit in the system reset register is set, indicating the user should perform the WDOG fast test. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 619: Application Information
It is suggested to disable or reconfigure the watchdog at the very beginning of the software code, e.g. beginning of the startup or main function. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 620: Disable Watchdog
Configure for reconfigurable DisableInterrupts; //disable global interrupt WDOG_CNT = 0xD928C520; //unlock watchdog while(WDOG_CS[ULK]==0); //wait until registers are unlocked WDOG_TOVAL = 256; //set timeout value WDOG_CS = WDOG_CS_EN(1) | WDOG_CS_CLK(1) | WDOG_CS_INT(1) | Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 621: Refreshing The Watchdog
To refresh the watchdog and reset the watchdog counter to zero, a refresh sequence is required: DisableInterrupts; // disable global interrupt WDOG_CNT = 0xB480A602; // refresh watchdog EnableInterrupts; // enable global interrupt Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 622 Application Information Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 623: Introduction
• Option for inversion of final CRC result • 32-bit CPU register programming interface 30.1.2 Block diagram The following is a block diagram of the CRC. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 624: Modes Of Operation
Register name Access Reset value (in bits) page (hex) 4003_2000 CRC Data register (CRC_DATA) FFFF_FFFFh 30.2.1/625 4003_2004 CRC Polynomial register (CRC_GPOLY) 0000_1021h 30.2.2/626 4003_2008 CRC Control register (CRC_CTRL) 0000_0000h 30.2.3/626 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 625: Crc Data Register (Crc_Data)
When CTRL[WAS] is 1, values written to this field are part of the seed value. When CTRL[WAS] is 0, data written to this field is used for CRC checksum generation. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 626: Crc Polynomial Register (Crc_Gpoly)
CRC calculation. A new CRC calculation is initialized by asserting CTRL[WAS] and then writing the seed into the CRC data register. Address: 4003_2000h base + 8h offset = 4003_2008h TOTR FXOR WAS Reset Reset Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 627: Functional Description
Width of CRC protocol. TCRC 16-bit CRC protocol. 32-bit CRC protocol. Reserved This field is reserved. This read-only field is reserved and always has the value 0. 30.3 Functional description Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 628: Crc Initialization/Reinitialization
8. When all values have been written, read the final CRC result from CRC_DATA[LU:LL]. Transpose and complement operations are performed on the fly while reading or writing values. See Transpose feature CRC result complement for details. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 629: Transpose Feature
CTRL[TOT] or CTRL[TOTR] fields, according to the CRC calculation being used. The following types of transpose functions are available for writing to and reading from the CRC data register: 1. CTRL[TOT] or CTRL[TOTR] is 00. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 630 = {reg[0:7], reg[8:15],reg[16:23], reg[24:31]} Figure 30-3. Transpose type 10 4. CTRL[TOT] or CTRL[TOTR] is 11. Bytes are transposed, but bits are not transposed. reg[31:0] becomes {reg[7:0], reg[15:8], reg[23:16], reg[31:24]} Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 631: Crc Result Complement
The DATA register is written with MSB of data value first, thus the application with little-endian configured, the data write bytes transpose should be enabled when writing a 32bit value from variable to DATA register. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 632: Bit Posix Crc
-= sizeof(uint32_t); data = (uint8_t *)data32; // 8-bit reads and writes till end of data buffer while (dataSize) CRC_DATA = *data; data++; dataSize--; // read 32bit checksum result checksum32 = CRC_DATA; Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 633: Bit Kermit Crc
// due to the transport option TOTR >= 2 // read 16bit checksum result from CRC_DATA[HU:HL] // otherwise, read checksum from CRC_DATA[LU:LL] checksum16 = (CRC_DATA & 0xFFFF0000) >> 16; Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 634 Usage Guide Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 635: Introduction
Through the ARM Debug Access Port (DAP), the debugger has access to the status and control elements, implemented as registers on the DAP bus as shown in Figure 31-1. These registers provide additional control and status for low-power mode recovery and Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 636 Access Port 1 with the available registers shown in the table below. Table 31-2. MDM-AP register summary Address Register Description 0x0100_0000 Status MDM-AP status register 0x0100_0004 Control MDM-AP Control register 0x0100_00FC Read-only identification register that always reads as 0x001C_0020 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 637: Mdm-Ap Status Register
Indicates that flash memory has been initialized and debugger can be configured even if system is continuing to be held in reset via the debugger. 0 Flash is under initialization. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 638: Mdm-Ap Control Register
Configuration field to control core operation at the end of system reset sequencing. 0 Normal operation—release the core from reset along with the rest of the system at the end of system reset sequencing. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 639: Debug Resets
SRAM controller. The system bus masters, including the processor, have read/write access to all of the SRAM via the AHB-Lite interface, allowing the memory to also be used to store program and data information. The MTB simultaneously stores the trace Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 640: Debug In Low-Power Modes
In the case of a secure device, the debugger has the capability of performing only a mass erase operation. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 641: Introduction
This document details the functionality of both the MTB_RAM and MTB_DWT capabilities. 32.1.1 Overview A generic block diagram of the processor core and platform for this class of ultra low-end microcontrollers is shown as follows: Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 642 PC value changes non-sequentially. A non-sequential PC change can occur during branch instructions or during exception entry. The processor can cause a trace packet to be generated for any instruction. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 643 For an exception return operation, two packets are generated: • The first packet has the: • Source address field set to the address of the instruction that causes the exception return, BX or POP. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 644: Features
• Program trace information in RAM available to MCU's application code or external debugger • Program trace watchpoint configuration accessible by MCU's application code or debugger • Location and size of RAM trace buffer is configured by software Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 645: Modes Of Operation
PC >> 1. ATOMIC Input Indicates the processor is performing non-instruction related activities. EDBGRQ Output Request for the processor to enter the Debug state, if enabled, and halt. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 646: Memory Map And Register Definition
See section 32.3.1.3/ F000_0008 MTB Flow Register (MTB_FLOW) Undefined 32.3.1.4/ F000_000C MTB Base Register (MTB_BASE) Undefined 32.3.1.5/ F000_0F00 Integration Mode Control Register (MTB_MODECTRL) 0000_0000h Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 647 F000_0FF0 Component ID Register (MTB_COMPID0) See section 32.3.1.15/ F000_0FF4 Component ID Register (MTB_COMPID1) See section 32.3.1.15/ F000_0FF8 Component ID Register (MTB_COMPID2) See section 32.3.1.15/ F000_0FFC Component ID Register (MTB_COMPID3) See section Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 648 See the MTB_FLOW register description for more details. Address: F000_0000h base + 0h offset = F000_0000h POINTER Reset POINTER Reset Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 649 If MTB_FLOW[WATERMARK] is used to stop tracing or to halt the processor, MTB_MASTER[MASK] must still be set to a value that prevents MTB_POSITION[POINTER] from wrapping before it reaches the MTB_FLOW[WATERMARK] value. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 650 1, then only privileged AHB read and write accesses to the RAM are permitted and user accesses are RAZ/WI. The HPROT[1] signal determines if an access is a user or privileged mode reference. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 651 Cortex-M0+ processor to enter the Debug state. To enter Debug state, the Cortex-M0+ processor might have to perform additional branch type operations. Therefore, the MTB_FLOW[WATERMARK] field must be set below the final entry in the trace buffer region. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 652 Cortex-M0+ processor by asserting the EDBGRQ signal. AUTOSTOP AUTOSTOP If this field is 1 and WATERMARK is equal to MTB_POSITION[POINTER], then MTB_MASTER[EN] is automatically set to 0. This stops tracing. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 653 It is hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_0000h base + F00h offset = F000_0F00h MODECTRL Reset MTB_MODECTRL field descriptions Field Description MODECTRL MODECTRL Hardwired to 0x0000_0000 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 654 0. It is hardwired to specific values used during the auto- discovery process by an external debug agent. Address: F000_0000h base + FA4h offset = F000_0FA4h TAGCLEAR Reset MTB_TAGCLEAR field descriptions Field Description TAGCLEAR TAGCLEAR Hardwired to 0x0000_0000 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 655 Where functionality changes on a given security level, this change must be reported in this register. It is connected to specific signals used during the auto-discovery process by an external debug agent. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 656 This register indicates the device architecture. It is hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_0000h base + FBCh offset = F000_0FBCh DEVICEARCH Reset Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 657 This register indicates the device type ID. It is hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_0000h base + FCCh offset = F000_0FCCh DEVICETYPID Reset MTB_DEVICETYPID field descriptions Field Description DEVICETYPID DEVICETYPID Hardwired to 0x0000_0031. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 658: Mtb_Dwt Memory Map
Component ID0 is hardwired to 0x0000_000D; ID1 to 0x0000_0090; ID2 to 0x0000_0005; ID3 to 0x0000_00B1. 32.3.2 MTB_DWT Memory Map The MTB_DWT programming model supports a very simplified subset of the v7M debug architecture and follows the standard Arm DWT definition. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 659 F000_1FF0 Component ID Register (MTBDWT_COMPID0) See section 32.3.2.10/ F000_1FF4 Component ID Register (MTBDWT_COMPID1) See section 32.3.2.10/ F000_1FF8 Component ID Register (MTBDWT_COMPID2) See section 32.3.2.10/ F000_1FFC Component ID Register (MTBDWT_COMPID3) See section Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 660 MTBDWT_CTRL[8:5] = POSTINIT = 0, cycle counter is not supported MTBDWT_CTRL[4:1] = POSTPRESET = 0, cycle counter is not supported MTBDWT_CTRL[0] = CYCCNTENA = 0, cycle counter is not supported Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 661 [31:x]. The maximum MASK value is 24, producing a 16 Mbyte mask. An attempted write of a MASK value > 24 is limited by the MTBDWT hardware to 24. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 662 FUNCTION Reset MTBDWT_FCT0 field descriptions Field Description 31–25 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 663 Disabled. 0100 Instruction fetch. 0101 Data operand read. 0110 Data operand write. 0111 Data operand (read + write). others Reserved. Any attempts to use this value results in UNPREDICTABLE behavior. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 664 If this read-only flag is asserted, it indicates the operation defined by the FUNCTION field occurred since the last read of the register. Reading the register clears this bit. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 665 MTB's control logic by setting the appropriate enable bits, MTB_MASTER[TSTARTEN, TSTOPEN]. In the event of simultaneous assertion of both TSTART and TSTOP, TSTART takes priority. Address: F000_1000h base + 200h offset = F000_1200h NUMCOMP Reset Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 666 • Data match in MTBDWT_COMP0 and address match in MTBDWT_COMP1 when MTBDWT_FCT0[DATAVMATCH, DATAVADDR0] = {1,1} Trigger TSTOP based on the assertion of MTBDWT_FCT0[MATCHED]. Trigger TSTART based on the assertion of MTBDWT_FCT0[MATCHED]. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 667 This register indicates the device type ID. It is hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_1000h base + FCCh offset = F000_1FCCh DEVICETYPID Reset MTBDWT_DEVICETYPID field descriptions Field Description DEVICETYPID DEVICETYPID Hardwired to 0x0000_0004. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 668: System Rom Memory Map
Component ID0 is hardwired to 0x0000_000D; ID1 to 0x0000_0090; ID2 to 0x0000_0005; ID3 to 0x0000_00B1. 32.3.3 System ROM Memory Map The System ROM Table registers are also mapped into a sparsely-populated 4 KB address space. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 669 32.3.3.2/ F000_200C End of Table Marker Register (ROM_TABLEMARK) 0000_0000h 32.3.3.3/ F000_2FCC System Access Register (ROM_SYSACCESS) 0000_0001h 32.3.3.4/ F000_2FD0 Peripheral ID Register (ROM_PERIPHID4) See section Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 670 Reset ROM_ENTRYn field descriptions Field Description ENTRY ENTRY Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 671 This register indicates system access. It is hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_2000h base + FCCh offset = F000_2FCCh SYSACCESS Reset ROM_SYSACCESS field descriptions Field Description SYSACCESS SYSACCESS Hardwired to 0x0000_0001 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 672: Usage Guide
Reset ROM_COMPIDn field descriptions Field Description COMPID Component ID Component ID0 is hardwired to 0x0000_000D; ID1 to 0x0000_0010; ID2 to 0x0000_0005; ID3 to 0x0000_00B1. 32.4 Usage Guide Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 673: Arm Reference
Chapter 32 Micro Trace Buffer (MTB) 32.4.1 ARM reference For more information about MTB, please refer to the ARM document ARM Debug Interface Architecture Specification Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 674 Usage Guide Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 675: Introduction
PTB0 can be sampled by both ADC0 and ADC1. The interleaved mode is enabled by SIM_CHIPCTL[ADC_INTERLEAVE_EN] bits. For more information, see "ADC Hardware Interleaved Channels" in the ADC chapter of Reference Manual. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 676 PTE8 FTM0_CH6 TSI0_CH11 TSI0_CH11 PTB5 TSI0_CH9 TSI0_CH9 PTB5 FTM0_CH5 LPSPI0_PCS1 TRGMUX_IN0 ACMP1_OUT PTB4 ACMP1_IN2/ ACMP1_IN2/ PTB4 FTM0_CH4 LPSPI0_SOUT TRGMUX_IN1 TSI0_CH8 TSI0_CH8 PTC3 ADC0_SE11/ ADC0_SE11/ PTC3 FTM0_CH3 ACMP0_IN4/ ACMP0_IN4/ EXTAL32 EXTAL32 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 677 PTC9 LPUART1_TX LPUART0_ PTC8 DISABLED PTC8 LPUART1_RX LPUART0_ PTA7 ADC0_SE3/ ADC0_SE3/ PTA7 FTM0_FLT2 RTC_CLKIN LPUART1_ ACMP1_IN1 ACMP1_IN1 PTA6 ADC0_SE2/ ADC0_SE2/ PTA6 FTM0_FLT1 LPSPI1_PCS1 LPUART1_ ACMP1_IN0 ACMP1_IN0 PTE7 DISABLED PTE7 FTM0_CH7 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 678 LPI2C1_SCLS PTA12 DISABLED PTA12 LPI2C1_SDAS PTA11 DISABLED PTA11 LPUART0_RX FXIO_D1 PTA10 DISABLED PTA10 LPUART0_TX FXIO_D0 PTE1 TSI0_CH14 TSI0_CH14 PTE1 LPSPI0_SIN LPI2C0_HREQ LPI2C1_SCL PTE0 TSI0_CH13 TSI0_CH13 PTE0 LPSPI0_SCK TCLK1 LPI2C1_SDA FTM1_FLT2 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 679: Pin Properties
PTB6 Hi-Z — — — — PTE14 Hi-Z — — — — PTE3 Hi-Z — — — — PTE12 Hi-Z — — — — Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 680 PTB0 Hi-Z — — — — PTC9 Hi-Z — — — — PTC8 Hi-Z — — — — PTA7 Hi-Z — — — — Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 681 — — PTA10 Hi-Z — — — — PTE1 Hi-Z — — — — PTE0 Hi-Z — — — — PTC5 — — — Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 682: Pinout Diagram
The following figure shows the pinout diagram for the devices supported by this document. Many signals may be multiplexed onto a single pin. To determine what signals can be used on which pin, see the previous table of Pin Assignments. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 683 PTB16 VREFL PTB17 PTA17 PTB7 PTB6 PTE7 PTE14 PTA6 PTE3 PTA7 PTE12 PTC8 PTD17 PTC9 PTD16 PTB0 PTD15 PTB1 PTE9 PTC10 PTD14 PTC11 PTD13 Figure 33-1. 100 LQFP Pinout Diagram Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 684: Module Signal Description Tables
33.3 Module Signal Description Tables The following sections correlate the chip-level signal name with the signal name used in the module's chapter. They also briefly describe the signal function and direction. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 685: Core Modules
EWM reset out signal 33.3.3 Clock Modules Table 33-4. OSC (in SCG) Signal Descriptions Chip Module signal name Description signal name EXTAL EXTAL External clock/Oscillator input XTAL XTAL Oscillator output Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 686: Analog
Analog voltage inputs ACMP0_OUT CMPO Comparator output DAC0_OUT DAC_OUT DAC output Table 33-9. ACMP1 Signal Descriptions Chip signal name Module signal Description name ACMP1_IN[5:0] IN[5:0] Analog voltage inputs ACMP1_OUT CMPO Comparator output Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 687 FTM channel (n), where n can be 1-0 FTM2_FLT[3:2] FAULTj Fault input (j), where j can be 3-2 TCLK[2:0] EXTCLK External clock. FTM external clock can be selected to drive the FTM counter. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 688 LPUART_CTS Clear to send LPUARTn_RTS LPUART_RTS Request to send Table 33-18. FlexIO Signal Descriptions Chip signal name Module signal Description name FXIO_D[7:0] FXIO_D[7:0] Bidirectional FlexIO Shifter and Timer pin inputs/outputs Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 689 PORTC17–PORTC0 General-purpose input/output PTD[17:0] PORTD17–PORTD0 General-purpose input/output PTE[16:0] PORTE16–PORTE0 General-purpose input/output Table 33-20. TSI0 Signal Descriptions Chip signal name Module signal Description name TSI0_CH[24:0] TSI[24:0] TSI sensing pins or GPIO pins Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 690 Module Signal Description Tables Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 691: Chip-Specific Information For This Module
ALT6 out en ALT7 out en ALT2 out data ALT3 out data ALT4 out data ALT5 out data ALT6 out data ALT7 out data ALT0 input/output (analog) Figure 34-1. Normal I/O structure Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 692: Port Control And Interrupt Module Features
Disabled Disabled Disabled enable at reset Pin mux control Pin mux at reset PTA4/PTA5=ALT7; ALT0 PTC4=ALT7; PTD3=ALT7; ALT0 Others=ALT0 Others=ALT0 Others=ALT0 Lock bit Interrupt and DMA request Digital glitch filter Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 693: Application-Related Information
• Pin interrupt is functional in all digital pin muxing modes • Digital input filter • Digital input filter for each pin, usable by any digital peripheral muxed onto the • Individual enable or bypass control field per pin Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 694: Modes Of Operation
In Stop mode, the digital input filters are bypassed unless they are configured to run from the LPO clock source. 34.3.2.4 Debug mode In Debug mode, PORT operates normally. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 695: External Signal Description
Pin Control Register n (PORTA_PCR0) See section 34.6.1/702 4004_9004 Pin Control Register n (PORTA_PCR1) See section 34.6.1/702 4004_9008 Pin Control Register n (PORTA_PCR2) See section 34.6.1/702 Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 696 Interrupt Status Flag Register (PORTA_ISFR) 0000_0000h 34.6.4/706 4004_90C0 Digital Filter Enable Register (PORTA_DFER) 0000_0000h 34.6.5/706 4004_90C4 Digital Filter Clock Register (PORTA_DFCR) 0000_0000h 34.6.6/707 4004_90C8 Digital Filter Width Register (PORTA_DFWR) 0000_0000h 34.6.7/707 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 697 0000_0000h 34.6.2/705 reads 0) 4004_A084 Global Pin Control High Register (PORTB_GPCHR) (always 0000_0000h 34.6.3/705 reads 0) 4004_A0A0 Interrupt Status Flag Register (PORTB_ISFR) 0000_0000h 34.6.4/706 Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 698 See section 34.6.1/702 4004_B07C Pin Control Register n (PORTC_PCR31) See section 34.6.1/702 4004_B080 Global Pin Control Low Register (PORTC_GPCLR) (always 0000_0000h 34.6.2/705 reads 0) Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 699 4004_C070 Pin Control Register n (PORTD_PCR28) See section 34.6.1/702 4004_C074 Pin Control Register n (PORTD_PCR29) See section 34.6.1/702 4004_C078 Pin Control Register n (PORTD_PCR30) See section 34.6.1/702 Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 700 4004_D064 Pin Control Register n (PORTE_PCR25) See section 34.6.1/702 4004_D068 Pin Control Register n (PORTE_PCR26) See section 34.6.1/702 4004_D06C Pin Control Register n (PORTE_PCR27) See section 34.6.1/702 Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 701 4004_D0A0 Interrupt Status Flag Register (PORTE_ISFR) 0000_0000h 34.6.4/706 4004_D0C0 Digital Filter Enable Register (PORTE_DFER) 0000_0000h 34.6.5/706 4004_D0C4 Digital Filter Clock Register (PORTE_DFCR) 0000_0000h 34.6.6/707 4004_D0C8 Digital Filter Width Register (PORTE_DFWR) 0000_0000h 34.6.7/707 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 702: Pin Control Register N (Portx_Pcrn)
PE field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port. • PS field: Varies by port. See Signal Multiplexing and Signal Descriptions chapter for reset values per port. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 703 The corresponding pin is configured in the following pin muxing slot as follows: Pin disabled (Alternative 0) (analog). Alternative 1 (GPIO). Alternative 2 (chip-specific). Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 704 Internal pulldown resistor is enabled on the corresponding pin, if the corresponding PE field is set. Internal pullup resistor is enabled on the corresponding pin, if the corresponding PE field is set. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 705: Global Pin Control Low Register (Portx_Gpclr)
Corresponding Pin Control Register is updated with the value in GPWD. GPWD Global Pin Write Data Write value that is written to all Pin Control Registers bits [15:0] that are selected by GPWE. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 706: Interrupt Status Flag Register (Portx_Isfr)
The digital filter configuration is valid in all digital pin muxing modes. The output of each digital filter is reset to zero at system reset and whenever the digital filter is disabled. Each bit in the field enables the digital filter of the same number as the field. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 707: Digital Filter Clock Register (Portx_Dfcr)
Digital filters are clocked by the LPO clock. 34.6.7 Digital Filter Width Register (PORTx_DFWR) The digital filter configuration is valid in all digital pin muxing modes. Address: Base address + C8h offset FILT Reset Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 708: Functional Description
When locked, writes to the lower half of that pin control register are ignored, although a bus error is not generated on an attempted write to a locked register. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 709: Global Pin Control
• Interrupt disabled, default out of reset • Active high level sensitive interrupt • Active low level sensitive interrupt • Rising edge sensitive interrupt • Falling edge sensitive interrupt • Rising and falling edge sensitive interrupt Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 710: Digital Filter
After a digital filter is enabled, the input is synchronized to the filter clock, either the bus clock or the LPO clock. If the synchronized input and the output of Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 711 The maximum latency through a digital filter equals three filter clock cycles plus the filter width configuration register. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 712 Functional description Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 713: Chip-Specific Information For This Module
(15) at address 0x4000_F000. Only some of the BME operations can be accomplished referencing GPIO at address 0x400F_F000. 35.2 Introduction The GPIO registers support 8-bit, 16-bit or 32-bit accesses. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 714: Features
35.2.3 GPIO signal descriptions Table 35-2. GPIO signal descriptions GPIO signal descriptions Description PORTA31–PORTA0 General-purpose input/output PORTB31–PORTB0 General-purpose input/output PORTC31–PORTC0 General-purpose input/output PORTD31–PORTD0 General-purpose input/output Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 715: Memory Map And Register Definition
35.3 Memory map and register definition Any read or write access to the GPIO memory space that is outside the valid memory map results in a bus error. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 716 0000_0000h 35.3.1/717 400F_F0C4 Port Set Output Register (GPIOD_PSOR) (always 0000_0000h 35.3.2/718 reads 0) 400F_F0C8 Port Clear Output Register (GPIOD_PCOR) (always 0000_0000h 35.3.3/718 reads 0) Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 717: Port Data Output Register (Gpiox_Pdor)
Register bits for unbonded pins return a undefined value when read. Logic level 0 is driven on pin, provided pin is configured for general-purpose output. Logic level 1 is driven on pin, provided pin is configured for general-purpose output. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 718: Port Set Output Register (Gpiox_Psor)
Writing to this register will update the contents of the corresponding bit in the Port Data Output Register (PDOR) as follows: Corresponding bit in PDORn does not change. Corresponding bit in PDORn is cleared to logic 0. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 719: Port Toggle Output Register (Gpiox_Ptor)
0. If the Port Control and Interrupt module is disabled, then the corresponding bit in PDIR does not update. Pin logic level is logic 0, or is not configured for use by digital function. Pin logic level is logic 1. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 720: Port Data Direction Register (Gpiox_Pddr)
0000_0000h 35.4.1/722 F800_0004 Port Set Output Register (FGPIOA_PSOR) (always 0000_0000h 35.4.2/722 reads 0) F800_0008 Port Clear Output Register (FGPIOA_PCOR) (always 0000_0000h 35.4.3/723 reads 0) Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 721 F800_00D0 Port Data Input Register (FGPIOD_PDIR) 0000_0000h 35.4.5/724 F800_00D4 Port Data Direction Register (FGPIOD_PDDR) 0000_0000h 35.4.6/724 F800_0100 Port Data Output Register (FGPIOE_PDOR) 0000_0000h 35.4.1/722 Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 722: Port Data Output Register (Fgpiox_Pdor)
Logic level 1 is driven on pin, provided pin is configured for general-purpose output. 35.4.2 Port Set Output Register (FGPIOx_PSOR) This register configures whether to set the fields of the PDOR. Address: Base address + 4h offset PTSO Reset Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 723: Port Clear Output Register (Fgpiox_Pcor)
Address: Base address + Ch offset PTTO Reset FGPIOx_PTOR field descriptions Field Description PTTO Port Toggle Output Writing to this register will update the contents of the corresponding bit in the PDOR as follows: Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 724: Port Data Input Register (Fgpiox_Pdir)
Port Data Direction Configures individual port pins for input or output. Pin is configured as general-purpose input, for the GPIO function. Pin is configured as general-purpose output, for the GPIO function. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 725: Functional Description
The corresponding Port Control and Interrupt module does not need to be enabled to update the state of the port data direction registers and port data output registers including the set/clear/toggle registers. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 726: Ioport
If the DMA attempts to access the GPIO registers on the same cycle as an IOPORT access, then the DMA access will stall until any IOPORT accesses have completed. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 727: Chip-Specific Information For This Module
1. This package for the product is not yet available. However, it is included in Package Your Way program for Kinetis MCU. Visit nxp.com/KPYW for more details. 36.1.1.2 ADC Connections/Channel Assignment Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 728 CMP1 8-bit DAC out 11000 AD24 Reserved 11001 AD25 Reserved 11010 AD26 Temperature Sensor 11011 AD27 Bandgap (1V reference voltage) 11100 AD28 Reserved 11101 AD29 VREFH 11110 AD30 VREFL 11111 Module disabled None Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 729 Reserved 11000 AD24 Reserved 11001 AD25 Reserved 11010 AD26 Temperature Sensor 11011 AD27 Bandgap (1V reference voltage) 11100 AD28 Reserved 11101 AD29 VREFH 11110 AD30 VREFL 11111 Module disabled None Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 730: Adc Clocking Information
DIV2 ALTCLK1 SIRC SIRCDIV2_CLK ALTCLK2 DIV2 ALTCLK3 FIRCDIV2_CLK FIRC ALTCLK4 DIV2 NOTE ALTCLK2~4 are not connected on this chip. 36.1.3 Inter-connectivity Information The ADC inter-connectivity is shown in following diagram. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 731: Application-Related Information
PTB0 can be sampled by both ADC0 and ADC1. The interleaved mode is enabled by SIM_CHIPCTL[ADC_INTERLEAVE_EN] bits. The hardware interleave implementation on this device is as follows: • ADC0_SE4 and ADC1_SE14 channels are interleaved on PTB0 pin Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 732 • ADC1_SE9 and ADC0_SEx channels are interleaved on PTB14 pin Figure 36-1. ADC0 and ADC1 hardware interleaved channels integration 36.1.4.2 ADC Reference Options The ADC supports the following references: • VREFH/VREFL - connected as the primary reference option Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 733 ADC0 ADHWTSA~ADHWTSB and the another two are for ADC1 ADHWTSA~ADHWTSB. • RTC capable to trigger each ADC • LPTMR capable to trigger each ADC • Software trigger capable to trigger each ADC Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 734 PDB0_ADC0_trig adhwtsA pretrig0 ADC0 adhwtsB pretrig1 cocoA cocoA cocoB cocoB PDB0 ADHWT ch1_trig pretrig0 adhwtsA pretrig1 adhwtsB ADC1 cocoA cocoA cocoB cocoB SIM_ADCOPT[ADC0SWPRETRG] Software SIM_ADCOPT[ADC0SWPRETRG] SIM_ADCOPT[ADC0PRETRGSEL] SIM_ADCOPT[ADC1PRETRGSEL] PDB triggering scheme: Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 735 ADC conversion. • With TRGMUX, a single LPIT could be used to trigger 2 ADCs at same time. This is one of the benefits for TRGMUX triggering, compared with PDB triggering. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 736: Introduction
36.2.1 Features Following are the features of the ADC module: • Linear successive approximation algorithm with up to 12-bit resolution • Up to 16 single-ended external analog inputs • Output modes: Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 737: Block Diagram
• Temperature sensor • Hardware average function • Selectable voltage reference: external or alternate • Self-Calibration mode 36.2.2 Block diagram The following figure is the ADC module block diagram. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 738: Adc Signal Descriptions
The ADC also requires four supply/reference/ground connections. NOTE For the number of channels supported on this device, see the chip-specific ADC information. The ADC does not produce any output signals. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 739: Voltage Reference Select
SC2[REFSEL]. The alternate voltage reference, V may select additional external pin ALTH or internal source depending on MCU configuration. See the chip configuration information on the Voltage References specific to this MCU. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 740: Analog Channel Inputs (Adx)
USER Offset Correction Register (ADC1_USR_OFS) 0000_0000h 36.4.11/ 4002_70A4 ADC X Offset Correction Register (ADC1_XOFS) 0000_0030h 36.4.12/ 4002_70A8 ADC Y Offset Correction Register (ADC1_YOFS) 0000_0037h Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 741 Status and Control Register 2 (ADC0_SC2) 0000_0000h 36.4.6/749 4003_B094 Status and Control Register 3 (ADC0_SC3) 0000_0000h 36.4.7/751 4003_B098 BASE Offset Register (ADC0_BASE_OFS) 0000_0040h 36.4.8/752 Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 742: Adc Status And Control Register 1 (Adcx_Sc1N)
ADC Plus-Side General Calibration Offset Value Register 9 36.4.28/ 4003_B0E8 0000_0240h (ADC0_CLP9_OFS) 36.4.1 ADC Status and Control Register 1 (ADCx_SC1n) SC1A is used for both software and hardware trigger modes of operation. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 743 This is a read-only field that is set each time a conversion is completed when one or more of the following is true: • The compare function is disabled Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 744 00110 Exernal channel 6 is selected as input. 00111 Exernal channel 7 is selected as input. 01000 Exernal channel 8 is selected as input. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 745: Adc Configuration Register 1 (Adcx_Cfg1)
ADICLK Reset ADCx_CFG1 field descriptions Field Description 31–9 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 746: Adc Configuration Register 2 (Adcx_Cfg2)
Configuration Register 2 (CFG2) selects the long sample time duration during long sample mode. NOTE Writing 0 is not supported on this register. Address: Base address + 44h offset SMPLTS Reset Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 747: Adc Data Result Registers (Adcx_Rn)
Address: Base address + 48h offset + (4d × i), where i=0d to 1d Reset ADCx_Rn field descriptions Field Description 31–12 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Data result Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 748: Compare Value Registers (Adcx_Cvn)
Address: Base address + 88h offset + (4d × i), where i=0d to 1d Reset ADCx_CVn field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Compare Value. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 749: Status And Control Register 2 (Adcx_Sc2)
Indicates that a conversion or hardware averaging is in progress. ADACT is set when a conversion is initiated and cleared when a conversion is completed or aborted. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 750 . This voltage may be additional external pin or internal ALTH source depending on the MCU configuration. See the chip configuration information for details specific to this MCU. Reserved Reserved Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 751: Status And Control Register 3 (Adcx_Sc3)
Continuous conversions will be performed (or continuous sets of conversions, if AVGE is set) after a conversion is initiated. Hardware Average Enable AVGE Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 752: Base Offset Register (Adcx_Base_Ofs)
Rn. If the result is greater than the maximum or less than the minimum result value, it is forced to the appropriate limit for the current mode of operation. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 753: User Offset Correction Register (Adcx_Usr_Ofs)
USR_OFS Reset ADCx_USR_OFS field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. USR_OFS USER Offset Error Correction Value Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 754: Adc X Offset Correction Register (Adcx_Xofs)
Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. YOFS Y offset error correction value 36.4.13 ADC Gain Register (ADCx_G) Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 755: Adc User Gain Register (Adcx_Ug)
CLPx are automatically set when the self-calibration sequence is done, that is, CAL is cleared. If these registers are written by the user after calibration, the linearity error specifications may not be met. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 756: Adc Plus-Side General Calibration Value Register 3 (Adcx_Clp3)
CLP3 field: Reset values are loaded out of IFR. ADCx_CLP3 field descriptions Field Description 31–10 This field is reserved. Reserved This read-only field is reserved and always has the value 0. CLP3 Calibration Value Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 757: Adc Plus-Side General Calibration Value Register 2 (Adcx_Clp2)
CLP1 field: Reset values are loaded out of IFR. ADCx_CLP1 field descriptions Field Description 31–9 This field is reserved. Reserved This read-only field is reserved and always has the value 0. CLP1 Calibration Value Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 758: Adc Plus-Side General Calibration Value Register 0 (Adcx_Clp0)
CLPX field: Reset values are loaded out of IFR. ADCx_CLPX field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 759: Adc Plus-Side General Calibration Value Register 9 (Adcx_Clp9)
ADCx_CLP9 field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. This field is reserved. Reserved CLP9 Calibration Value Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 760: Adc General Calibration Offset Value Register S (Adcx_Clps_Ofs)
Reset ADCx_CLP3_OFS field descriptions Field Description 31–4 This field is reserved. Reserved This read-only field is reserved and always has the value 0. CLP3_OFS CLP3 Offset Capacitor offset correction value Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 761: Adc Plus-Side General Calibration Offset Value Register 2 (Adcx_Clp2_Ofs)
This read-only field is reserved and always has the value 0. CLP1_OFS CLP1 Offset Capacitor offset correction value 36.4.26 ADC Plus-Side General Calibration Offset Value Register 0 (ADCx_CLP0_OFS) Address: Base address + E0h offset CLP0_OFS Reset Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 762: Adc Plus-Side General Calibration Offset Value Register X (Adcx_Clpx_Ofs)
Reset ADCx_CLP9_OFS field descriptions Field Description 31–12 This field is reserved. Reserved This read-only field is reserved and always has the value 0. CLP9_OFS CLP9 Offset Capacitor offset correction value Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 763: Functional Description
This clock source is then divided by a configurable value to generate the input clock ADCK, to the module. The clock is selected from one of the following sources by means of CFG1[ADICLK]. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 764: Voltage Reference Selection
ADC continues to do conversions on the same SCn register that initiated the conversion. The hardware trigger function operates in conjunction with any of the conversion modes and configurations. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 765: Conversion Control
• Low-power operation • Long sample time • Continuous conversion • Hardware average • Automatic compare of the conversion result to a software-determined compare value 36.5.4.1 Initiating conversions A conversion is initiated: Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 766 36.5.4.2 Completing conversions A conversion is completed when the result of the conversion is transferred into the data result registers, Rn, as indicated in the following table. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 767 If the conversion was aborted by a reset, RA and Rn return to their reset states. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 768 The number of conversions is determined by the AVGS[1:0] bits, which can select 4, 8, 16, or 32 conversions to be averaged. While the hardware average function is in progress, SC2[ADACT] will be set. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 769: Automatic Compare Function
Inside range, inclusive Compare true if the result is greater than or equal to CV1 And the result is less than or equal equal to CV2. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 770: Calibration Function
• Calibrate only one ADC instance at a time. So, when calibrating instance ADC0, the instances ADC1, ADC2, etc. are required to be idle. • Set ADCK (ADC clock) to half the maximum specified frequency. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 771: User-Defined Offset Function
For example, in 8-bit single-ended mode, OFS[14:7] are subtracted from D[7:0]; OFS[15] indicates the sign (negative numbers are effectively added to the result) and OFS[6:0] are ignored. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 772: Mcu Wait Mode Operation
If a single conversion is selected and the compare trigger is not met, the ADC will return to its idle state and cannot wake the MCU from Wait mode unless a new conversion is initiated by the hardware trigger. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 773: Mcu Normal Stop Mode Operation
2. Update CFG to select the input clock source and the divide ratio used to generate ADCK. 3. Update SC2 to select the conversion trigger, hardware or software, and compare function options, if enabled. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 774: Pseudo-Code Example
// Bit 4:0 ADCH 00001 Input channel 1 selected as ADC input channel. ADC_RA = 0xxx // Holds results of conversion. ADC_CV = 0xxx // Holds compare value when compare function enabled. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 775: Calibration
• Set ADCK (ADC clock) to half the maximum specified frequency, e.g. 25 MHz. • Start ADC calibration by writing ADC_SC3 register with: CAL=1, AVGE=1, AVGS=11. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 776: Application Hints
36.6.6 ADC low-power modes The ADC will be available in STOP, VLPR, VLPW, and VLPS mode. NOTE When in VLPx mode, the ADC clock source is only limited to OSC and SIRC. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 777: Adc Trigger Concept – Use Case
. . . match_trig ch1_trig ADC1 ch1_pretrig0 TRGMUX pretrig0 result0 ch1_pretrig1 pretrig1 result1 COCO DMA_REQ INTERRUPT Figure 36-3. PWM Load Diagnosis – ADC Trigger Concept (block diagram) Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 778: Adc Self-Test And Calibration Scheme
Not doing this can result in ADC conversion results with lower than specified accuracy. Calibration needs to be initiated manually by setting the CAL bit. For more details, please refer to "Calibration" section. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 779: Chip-Specific Information For This Module
The following table shows the input connections to the CMP. Table 37-1. CMP input connections CMP Inputs CMP0 CMP1 ACMP0_IN0 ACMP1_IN0 ACMP0_IN1 ACMP1_IN1 ACMP0_IN2 ACMP1_IN2 ACMP0_IN3 ACMP1_IN3 ACMP0_IN4 ACMP1_IN4 ACMP0_IN5 ACMP1_IN5 Reserved Reserved Reserved Reserved Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 780: Cmp Clocking Information
8-bit DAC1 output could be used as ADC0 reference input. CMP0 ANL0 8-bit DAC0 DAC_OUT Buffer CMP1 ANL1 8-bit DAC1 ADC0 37.1.2 CMP Clocking Information The CMP clocking input is as below. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 781: Inter-Connectivity Information
Peripheral Clocking - CMP CMPn module PCC module SCG module Peripheral Interface Clock BUS_CLK SCG DIVSLOW PCC_CMPn[CGC] Registers Main Clock (internal) 37.1.3 Inter-connectivity Information The CMP inter-connectivity is shown in following diagram. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 782: Application-Related Information
The 8-bit DAC sub-block supports selection of two references. For this device, the references are connected as follows: • VDDA -- connected to V of CMP • PMC bandgap buffer out (1V reference voltage) -- connected to V of CMP Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 783 The LPTMR only offers single wire trigger to CMP. And the configuration must be done by LPTMR itself (round robin) before entering low power mode. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 784: Introduction
• Selectable inversion on comparator output • Capability to produce a wide range of outputs such as: • Sampled • Windowed, which is ideal for certain PWM zero-crossing-detection applications • Digitally filtered: Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 785: Bit Dac Key Features
• Option to route the output to internal comparator input 37.3.3 ANMUX key features The ANMUX has the following features: • Two 8-to-1 channel MUXes • Operational over the entire supply range Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 786: Cmp, Dac, And Anmux Diagram
Reference Input 3 Reference Input 4 Reference Input 5 Sample input Reference Input 6 Reference Input 7 ANMUX Window and filter control CMPO MSEL[2:0] INNSEL[1:0] Figure 37-1. CMP high level diagram Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 787: Cmp Block Diagram
WINDOW=1 to generate COUTA. Sampling does NOT occur when WINDOW = 0. • The Filter block is bypassed when not in use. FILT_PER = 0x00 FILTER_CNT = 0x00 bypass_Filter_Block Figure 37-3. Filter block bypass logic Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 788: Cmp Pin Descriptions
For such case, the software workaround is to configure the DAC side SEL[2:0] same as the non-DAC side, i.e. configuration of MSEL and PSEL register bits must be the same. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 789: External Pins
Individual modes are discussed below. Table 37-3. Comparator sample/filter controls C0[FILTER_CN Mode # C0[EN] C0[WE] C0[SE] C0[FPR] Operation Disabled See the Disabled mode (# 0x00 Continuous Mode Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 790 Note Filtering and sampling settings must be changed only after setting C0[SE]=0, C0[FPR] =0 and C0[FILTER_CNT]=0x00. This resets the filter to a known state. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 791: Disabled Mode (# 1)
The path from comparator input pins to output pin is operating in combinational unclocked mode. COUT and COUTA are identical. For control configurations that result in disabling the filter block, see Figure 37-3. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 792: Sampled, Non-Filtered Mode (#S 3A & 3B)
#3B, the clock to filter block is internally derived. The comparator filter has no other function than sample/hold of the comparator output in this mode (# 3B). Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 793: Sampled, Filtered Mode (#S 4A & 4B)
In Sampled, Filtered mode, the analog comparator block is powered and active. The path from analog inputs to COUTA is combinational unclocked. Windowing control is completely bypassed. COUTA is sampled whenever a rising edge is detected on the filter block clock input. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 794 CMPO COUT To other SOC functions WINDOW/SAMPLE bus clock Clock COUTA CMPO to prescaler divided FILT_PER CGMUX clock SE=1 Figure 37-8. Sampled, Filtered (# 4A): sampling point externally driven Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 795: Windowed Mode (#S 5A & 5B)
WINDOW signal is high. In actual operation, COUTA may lag the analog inputs by up to one bus clock cycle plus the combinational path delay through the comparator and polarity select logic. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 796 For control configurations which result in disabling the filter block, see Figure 37-3. When any windowed mode is active, COUTA is clocked by the bus clock whenever WINDOW = 1. The last latched value is held when WINDOW = 0. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 797 Configuration for this mode is virtually identical to that for the Windowed/Filtered Mode shown in the next section. The only difference is that the value of C0[FILTER_CNT] must be 1. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 798: Windowed/Filtered Mode (#7)
FILT_PER CGMUX clock SE=0 Figure 37-13. Windowed/Filtered mode The following figure shows the operation timing for this mode, considering uncertainty is introduced by the internal synchronization for the filter block. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 799: Memory Map/Register Definitions
37.8.1/799 4007_4004 CMP Control Register 1 (CMP1_C1) 0000_0000h 37.8.2/803 4007_4008 CMP Control Register 2 (CMP1_C2) 0000_0000h 37.8.3/806 37.8.1 CMP Control Register 0 (CMPx_C0) Access: • Supervisor read/write • User read/write Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 800 Enables the CFR interrupt from the CMP. When this field is set, an interrupt will be asserted when CFR is set. Interrupt is disabled. Interrupt is enabled. Comparator Interrupt Enable Falling Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 801 Low Speed (LS) comparison mode is selected. High Speed (HS) comparison mode is selected, in VLPx mode, or Stop mode switched to Low Speed (LS) mode. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 802 This read-only field is reserved and always has the value 0. Comparator hard block offset control. See chip data sheet to get the actual offset value with each level OFFSET Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 803: Cmp Control Register 1 (Cmpx_C1)
CMPx_C1 field descriptions Field Description 31–30 This field is reserved. Reserved This read-only field is reserved and always has the value 0. DAC output Enable DACOE Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 804 If the same channel is selected as the reference voltage, this bit has no effect. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 805 Note: For the round robin mode of operation, the MSEL and PSEL bitfields in CMPx_C1 register must have different values. 10–8 Minus Input MUX Control MSEL Determines which input is selected for the minus mux. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 806: Cmp Control Register 2 (Cmpx_C2)
DACO range is from Vin/256 to Vin. 37.8.3 CMP Control Register 2 (CMPx_C2) Access: • Supervisor read/write • User read/write Address: Base address + 8h offset RRE RRIE FXMXCH Reset Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 807 Channel 7 input changed flag. This bit is set if the channel 7 input changed from the last comparison with CH7F the fixed mux port. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 808: Cmp Functional Description
C0[CFF] is set on a falling edge, and C0[CFR] is set on a rising edge of the comparator output. The optionally filtered CMPO can be read directly through C0[COUT]. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 809: Initialization
COUTA when the selected INM and INP input voltages differ by less than the offset voltage of the differential comparator. 37.9.2.1 Enabling filter modes Filter modes can be enabled by: Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 810 The following table summarizes maximum latency values for the various modes of operation in the absence of noise. Filtering latency is restarted each time an actual output transition is masked by noise. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 811: Interrupts
The interrupt request is asserted C0[IER] and C0[CFR] are cleared for a rising-edge interrupt The interrupt request is deasserted C0[IEF] and C0[CFF] are cleared for a falling-edge interrupt The interrupt request is deasserted Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 812: Dma Support
1 (CMP_C1). Its supply reference source can be selected from two sources V and V . The module can be powered down or disabled when not in use. When in the Disabled mode, DACO is connected to the analog ground. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 813: Dac Resets
CMP and DAC prior to performing a CMP operation and capturing the output. A fixed channel for either the plus-side mux or the minus-side mux is selected by software via C2[FXMP] and Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 814 C0[PMODE]. It is also required to not select the internal reserved channels for round-robin by INPSEL and INNSEL. NOTE In round-robin mode, it is suggested to always configure the DAC output as the fixed port reference. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 815 Trigger Channel Channel 0~7 Mode sweep can be swept (CHNx) with DAC Channel Channel 0~7 sweep can be swept with DAC (CHNx) Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 816: Usage Guide
CMPx_C1 = (CMPx_C1 & ~(CMP_C1_ INPSEL_MASK | CMP_C1_PSEL_MASK)) | CMP_C1_INPSEL(1) | CMP_C1_PSEL(3); Then, the CMP output interrupts with their flags would be used to indicate the event of Zero Crossing Detection. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 817: Window Mode
This mode compares multiple input channels with the reference input channel (fixed) in a round-robin manner. It is commonly used to provide a trigger mode to wake up the MCU in STOP mode. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 818 All channel0~7 as the round robin checker channel in non-fixed port. The comparison result is sampled as soon as the active channel is scanned in one round-robin clock. The initialization delay modulus is set to 64. Enable round robin mode. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 819 SoC. */ /* Set SoC enter into STOP mode. See the power management chapter. */ /* Change the voltage of input channel to wake up the SoC. */ Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 820 Usage Guide Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 821: Chip-Specific Information For This Module
Number of Pulse Out Pulse Out connects to TRGMUX Number of DAC interval triggers 38.1.2 PDB Clocking Information The PDB module is only clocked by system clock shown in following diagram. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 822: Inter-Connectivity Information
ADHWTS A ch0_pretrig1 pre-trig1 ADHWTS B PDB0_PULSE0 Pulse 0 PDB0_PULSE1 ADC1 Pulse 1 PDB0_CH1 ADC1_CHx ch1_trigger trigger ADHWT . . . ch1_pretrig0 pre-trig0 ADHWTS A ch1_pretrig1 pre-trig1 ADHWTS B Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 823 • PDB channel 0 trigger/pre-trigger 1 acknowledgement input: ADC0SC1A_COCO • PDB channel 1 trigger/pre-trigger 0 acknowledgement input: ADC0SC1B_COCO • PDB channel 1 trigger/pre-trigger 1 acknowledgement input: ADC1SC1A_COCO The back-to-back chain diagram is as follows: Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 824: Introduction
• Operation in One-Shot or Continuous modes • Optional back-to-back mode operation, which enables the ADC conversions complete to trigger the next PDB channel • One programmable delay interrupt • One sequence error interrupt Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 825: Implementation
For module to core output triggers implementation, see the chip configuration information. 38.2.3 Back-to-back acknowledgment connections PDB back-to-back operation acknowledgment connections are chip-specific. For implementation, see the chip configuration information. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 826: Block Diagram
PDB Counter CONT MULT PRESCALER Trigger-In 0 Trigger-In 1 POyDLY1 Pulse Pulse-Out y Trigger-In 14 Generation SWTRIG PDBPOEN[y] POyDLY2 TRIGSEL Pulse-Out y PDB interrupt PDBIDLY TOEx Figure 38-1. PDB block diagram Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 827: Modes Of Operation
If the PDB is enabled and external trigger input source is selected, a positive edge on the EXTRG signal resets and starts the counter. 38.4 Memory map and register definition Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 828 Channel n Delay 1 register (PDB0_CH1DLY1) 0000_0000h 38.4.8/836 4003_6190 Pulse-Out n Enable register (PDB0_POEN) 0000_0000h 38.4.9/836 38.4.10/ 4003_6194 Pulse-Out n Delay register (PDB0_PO0DLY) 0000_0000h 38.4.10/ 4003_6198 Pulse-Out n Delay register (PDB0_PO1DLY) 0000_0000h Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 829: Status And Control Register (Pdbx_Sc)
Enables the PDB sequence error interrupt. When PDBEIE is set, any of the PDB channel sequence error flags generates a PDB sequence error interrupt. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 830 Trigger-In 11 is selected. 1100 Trigger-In 12 is selected. 1101 Trigger-In 13 is selected. 1110 Trigger-In 14 is selected. 1111 Software trigger is selected. PDB Enable PDBEN Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 831 • LDOK is automatically cleared when the values in the internal buffers are loaded into the registers or when PDBEN bit (PDB Enable) is cleared. • Writing 0 to LDOK has no effect. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 832: Modulus Register (Pdbx_Mod)
PDB. 38.4.3 Counter register (PDBx_CNT) NOTE Writing to this read-only register will generate a transfer error (and possibly a hard fault). Address: 4003_6000h base + 8h offset = 4003_6008h Reset Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 833: Interrupt Delay Register (Pdbx_Idly)
Each PDB channel has one control register, CHnC1. The bits in this register control the functionality of each PDB channel operation. Address: 4003_6000h base + 10h offset + (40d × i), where i=0d to 1d Reset Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 834: Channel N Status Register (Pdbx_Chns)
PDB Channel Flags The CF[m] field is set when the PDB counter (PDB_CNT) matches the value CHnDLYm + 1. Write 0 to clear CF. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 835: Channel N Delay 0 Register (Pdbx_Chndly0)
Specifies the delay value for the channel's corresponding pre-trigger. The pre-trigger asserts when the counter is equal to DLY. Reading this field returns the value of internal register that is effective for the current PDB cycle. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 836: Channel N Delay 1 Register (Pdbx_Chndly1)
This read-only field is reserved and always has the value 0. POEN PDB Pulse-Out Enable Enables the pulse output. Only lower 8 bits are implemented in this MCU. PDB Pulse-Out disabled PDB Pulse-Out enabled Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 837: Pulse-Out N Delay Register (Pdbx_Pondly)
(SC[SWTRIG]) is written with 1. For each channel, a delay m determines the time between assertion of the trigger input event to the time at which changes in the pre- trigger m output signal are started. The time is defined as: Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 838 ADC conversions can be triggered on the next set of configuration and results registers. When back-to-back operation is enabled by setting the PDB Channel Pre-Trigger Back-to-Back Operation Enable (CHnC1[BB[m]]), then the delay m Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 839 If the Continuous Mode Enable (SC[CONT]) is set, then the counter will then resume a new count; otherwise, the counter operation will stop until the next trigger input event occurs. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 840: Pdb Trigger Input Source Selection
ADC pre-trigger/trigger outputs and Pulse-Out generation have the same time base, because they both share the PDB counter. The pulse-out connections implemented in this MCU are described in the device's chip configuration details. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 841: Updating The Delay Registers
The following registers control the timing of the PDB operation; and in some of the applications, they may need to become effective at the same time. • PDB Modulus register (MOD) • PDB Interrupt Delay register (IDLY) Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 842 The following diagrams show the cases of the internal registers being updated with SC[LDMOD] is 00 and x1. CHnDLY1 CHnDLY0 PDB counter SC[LDOK] Ch n pre-trigger 0 Ch n pre-trigger 1 Figure 38-4. Registers update with SC[LDMOD] = 00 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 843: Interrupts
38.5.6 DMA If SC[DMAEN] is set, PDB can generate a DMA transfer request when SC[PDBIF] is set. When DMA is enabled, the PDB interrupt is not issued. 38.6 Application information Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 844: Impact Of Using The Prescaler And Multiplication Factor On Timing Resolution
Therefore, use the lowest possible prescaler and multiplication factor for a given application. 38.7 Usage Guide 38.7.1 Using PDB to precisely control ADC conversion For detailed information, see the ADC trigger sections in the ADC chapter. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 845: Chip-Specific Information For This Module
Compared with the FTM0 configuration, the FTM1 and FTM2 configuration adds the Quadrature decoder feature. 39.1.2 FTM Clocking Information The following figure shows the input clock sources available for this module. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 846: Inter-Connectivity Information
1/4 of the system clock frequency. 39.1.3 Inter-connectivity Information The FTM inter-connectivity is shown in the following diagram. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 847 • FTM0 FAULT1 = FTM0_FLT1 pin or TRGMUX output • FTM0 FAULT2 = FTM0_FLT2 pin or TRGMUX output • FTM0 FAULT3 = FTM0_FLT3 pin • FTM1 FAULT0 = TRGMUX output • FTM1 FAULT1 = TRGMUX output Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 848 The FlexTimer support external hardware trigger input which can be used for timer dynamic synchronization between multiple FlexTimers or counter reset. The FlexTimer hardware trigger are implemented as following. FTM0: Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 849 TRGMUX module. hw_trig init_trig hw_trig init_trig FTM0 FTM0 ext_trig ext_trig hw_trig init_trig hw_trig init_trig FTM1 FTM1 ext_trig ext_trig hw_trig init_trig hw_trig init_trig FTM2 FTM2 ext_trig ext_trig TRGMUX ADC0 PDB0 ADC1 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 850: Introduction
TPM module. Several key enhancements are made: • Signed up counter Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 851: Features
• Selecting external clock connects FTM clock to a chip level input pin therefore allowing to synchronize the FTM counter with an off chip clock source • Prescaler divide-by 1, 2, 4, 8, 16, 32, 64, or 128 • 16-bit counter Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 852 • Half cycle and Full cycle register reload capacity • Write protection for critical registers • Backwards compatible with TPM • Testing of input capture mode • Direct access to input pin states Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 853: Modes Of Operation
The following figure shows the FTM structure. The central component of the FTM is the 16-bit counter with programmable initial and final values and its counting can be up or up-down. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 854 7 input output mask, fault control and polarity control) CH7F channel 7 channel 7 interrupt CH7TRIG match trigger CH7IE Figure 39-3. FTM Block Diagram Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 855: Ftm Signal Descriptions
This section presents a high-level summary of the FTM registers and how they are mapped. The registers and bits of an unavailable function in the FTM remain in the memory map and in the reset value, but they have no active function. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 856: Register Descriptions
39.4.6/867 4003_8040 Channel (n) Value (FTM0_C6V) 0000_0000h 39.4.7/869 4003_8044 Channel (n) Status And Control (FTM0_C7SC) 0000_0000h 39.4.6/867 4003_8048 Channel (n) Value (FTM0_C7V) 0000_0000h 39.4.7/869 Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 857 4003_809C Half Cycle Register (FTM0_HCR) 0000_0000h 39.4.29/ 4003_8200 Mirror of Modulo Value (FTM0_MOD_MIRROR) 0000_0000h 39.4.30/ 4003_8204 Mirror of Channel (n) Match Value (FTM0_C0V_MIRROR) 0000_0000h Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 858 Capture And Compare Status (FTM1_STATUS) 0000_0000h 39.4.9/870 39.4.10/ 4003_9054 Features Mode Selection (FTM1_MODE) 0000_0004h 39.4.11/ 4003_9058 Synchronization (FTM1_SYNC) 0000_0000h 39.4.12/ 4003_905C Initial State For Channels Output (FTM1_OUTINIT) 0000_0000h Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 859 4003_920C Mirror of Channel (n) Match Value (FTM1_C2V_MIRROR) 0000_0000h 39.4.30/ 4003_9210 Mirror of Channel (n) Match Value (FTM1_C3V_MIRROR) 0000_0000h 39.4.30/ 4003_9214 Mirror of Channel (n) Match Value (FTM1_C4V_MIRROR) 0000_0000h Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 860 Output Mask (FTM2_OUTMASK) 0000_0000h 39.4.14/ 4003_A064 Function For Linked Channels (FTM2_COMBINE) 0000_0000h 39.4.15/ 4003_A068 Deadtime Configuration (FTM2_DEADTIME) 0000_0000h 39.4.16/ 4003_A06C FTM External Trigger (FTM2_EXTTRIG) 0000_0000h Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 861 39.4.30/ 4003_A218 Mirror of Channel (n) Match Value (FTM2_C5V_MIRROR) 0000_0000h 39.4.30/ 4003_A21C Mirror of Channel (n) Match Value (FTM2_C6V_MIRROR) 0000_0000h 39.4.30/ 4003_A220 Mirror of Channel (n) Match Value (FTM2_C7V_MIRROR) 0000_0000h Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 862: Status And Control (Ftmx_Sc)
This read-only field is reserved and always has the value 0. 27–24 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Channel 7 PWM enable bit PWMEN7 Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 863 This bit enables the PWM channel output. This bit should be set to 0 (output disabled) when an input mode is used. Channel output port is disabled Channel output port is enabled Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 864 This field is write protected. It can be written only when MODE[WPDIS] = 1. No clock selected. This in effect disables the FTM counter. FTM input clock Fixed frequency clock External clock Prescale Factor Selection Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 865: Counter (Ftmx_Cnt)
(TOF) becomes set at the next clock cycle, and the next value of FTM counter depends on the selected counting method; see Counter. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 866 Address: Base address + 8h offset Reset FTMx_MOD field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Modulo Value Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 867: Channel (N) Status And Control (Ftmx_Cnsc)
(n) filter is enabled) both them are inside the FTM. NOTE: The CHIS bit should be ignored when the channel (n) is not in an input mode. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 868 Used on the selection of the channel (n) mode. See Channel Modes. This field is write protected. It can be written only when MODE[WPDIS] = 1. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 869: Channel (N) Value (Ftmx_Cnv)
Captured FTM counter value of the input modes or the match value for the output modes 39.4.8 Counter Initial Value (FTMx_CNTIN) The Counter Initial Value register contains the initial value for the FTM counter. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 870: Capture And Compare Status (Ftmx_Status)
If another event occurs between the read and write operations, the write operation has no effect; therefore, CHF remains set indicating an event has occurred. In this case, a CHF interrupt request is not lost due to the clearing sequence for a previous CHF. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 871 Channel 5 Flag CH5F See the register description. No channel event has occurred. A channel event has occurred. Channel 4 Flag CH4F See the register description. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 872: Features Mode Selection (Ftmx_Mode)
• Capture Test mode • PWM synchronization • Write protection • Channel output initialization These controls relate to all channels within this module. Address: Base address + 54h offset Reset Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 873 WPEN bit. WPDIS is cleared when 1 is written to WPEN. WPDIS is set when WPEN bit is read as a 1 and then 1 is written to WPDIS. Writing 0 to WPDIS has no effect. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 874: Synchronization (Ftmx_Sync)
0 and hardware trigger selection, TRIG0, TRIG1, or TRIG2 bits, is likely to result in unpredictable behavior. The synchronization event selection also depends on the PWMSYNC (MODE register) and SYNCMODE (SYNCONF register) bits. See synchronization. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 875 0 input signal. Trigger is disabled. Trigger is enabled. Output Mask Synchronization SYNCHOM Selects when the OUTMASK register is updated with the value of its buffer. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 876: Initial State For Channels Output (Ftmx_Outinit)
Reset Reset FTMx_OUTINIT field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 877 Channel 0 Output Initialization Value CH0OI Selects the value that is forced into the channel output when the initialization occurs. The initialization value is 0. The initialization value is 1. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 878: Output Mask (Ftmx_Outmask)
Channel output is masked. It is forced to its inactive state. Channel 5 Output Mask CH5OM Defines if the channel output is masked or unmasked. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 879 Defines if the channel output is masked or unmasked. Channel output is not masked. It continues to operate normally. Channel output is masked. It is forced to its inactive state. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 880: Function For Linked Channels (Ftmx_Combine)
The deadtime insertion in this pair of channels is disabled. The deadtime insertion in this pair of channels is enabled. Dual Edge Capture Mode Captures For n = 6 DECAP3 Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 881 Enables the capture of the FTM counter value according to the channel (n) input event and the configuration of the dual edge capture bits. This field applies only when DECAPEN = 1. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 882 DECAP bit is cleared automatically by hardware if Dual Edge Capture – One-Shot mode is selected and when the capture of channel (n+1) event is made. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 883 DECAP bit is cleared automatically by hardware if dual edge capture – one-shot mode is selected and when the capture of channel (n+1) event is made. The dual edge captures are inactive. The dual edge captures are active. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 884: Deadtime Configuration (Ftmx_Deadtime)
Divide the FTM input clock by 1. Divide the FTM input clock by 4. Divide the FTM input clock by 16. DTVAL Deadtime Value Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 885: Ftm External Trigger (Ftmx_Exttrig)
• Selects which channels are used in the generation of the channel triggers Several channels can be selected to generate multiple triggers in one PWM period. See External Trigger Initialization trigger Address: Base address + 6Ch offset Reset Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 886 Enables the generation of the trigger when the FTM counter is equal to the CNTIN register. The generation of initialization trigger is disabled. The generation of initialization trigger is enabled. Channel 1 Trigger Enable CH1TRIG Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 887: Channels Polarity (Ftmx_Pol)
That is, the safe value of a channel is the value of its POL bit. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 888 This field is write protected. It can be written only when MODE[WPDIS] = 1. The channel polarity is active high. The channel polarity is active low. Channel 2 Polarity POL2 Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 889 Defines the polarity of the channel output. This field is write protected. It can be written only when MODE[WPDIS] = 1. The channel polarity is active high. The channel polarity is active low. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 890: Fault Mode Status (Ftmx_Fms)
FAULTF remains set after the clearing sequence is completed for the earlier fault condition. FAULTF is also cleared when FAULTFj bits are cleared individually. No fault condition was detected. A fault condition was detected. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 891 Writing a 1 to FAULTF1 has no effect. FAULTF1 bit is also cleared when FAULTF bit is cleared. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 892: Input Capture Filter Control (Ftmx_Filter)
This read-only field is reserved and always has the value 0. 15–12 Channel 3 Input Filter CH3FVAL Selects the filter value for the channel input. The filter is disabled when the value is zero. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 893: Fault Control (Ftmx_Fltctrl)
This configuration allows to put the FTM outputs tri-stated when a fault event is ongoing. This field is write protected. It can be written only when MODE[WPDIS] = 1. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 894 Fault input is enabled. Fault Input 2 Enable FAULT2EN Enables the fault input. This field is write protected. It can be written only when MODE[WPDIS] = 1. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 895 Fault Input 0 Enable FAULT0EN Enables the fault input. This field is write protected. It can be written only when MODE[WPDIS] = 1. Fault input is disabled. Fault input is enabled. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 896: Quadrature Decoder Control And Status (Ftmx_Qdctrl)
CH0FVAL field of FILTER. The phase A filter is also disabled when CH0FVAL is zero. Phase A input filter is disabled. Phase A input filter is enabled. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 897 The Quadrature Decoder mode has precedence over the other modes. See Channel Modes. This field is write protected. It can be written only when MODE[WPDIS] = 1. Quadrature Decoder mode is disabled. Quadrature Decoder mode is enabled. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 898: Configuration (Ftmx_Conf)
Configures the FTM to use an external global time base signal that is generated by another FTM. Use of an external global time base is disabled. Use of an external global time base is enabled. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 899: Ftm Fault Input Polarity (Ftmx_Fltpol)
Fault Input 3 Polarity FLT3POL Defines the polarity of the fault input. This field is write protected. It can be written only when MODE[WPDIS] = 1. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 900: Synchronization Configuration (Ftmx_Synconf)
CNTIN registers synchronization, if FTM clears the TRIGj bit, where j = 0, 1, 2, when the hardware trigger j is detected. Address: Base address + 8Ch offset Reset INVC Reset Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 901 The software trigger does not activate the FTM counter synchronization. The software trigger activates the FTM counter synchronization. Synchronization Mode SYNCMODE Selects the PWM Synchronization mode. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 902: Ftm Inverting Control (Ftmx_Invctrl)
This register has a write buffer. The INVmEN bit is updated by the INVCTRL register synchronization. Address: Base address + 90h offset Reset Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 903: Ftm Software Output Control (Ftmx_Swoctrl)
• The CH(n)OCV bits select the value that is forced at the corresponding channel (n) output. This register has a write buffer. The fields are updated by the SWOCTRL register synchronization. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 904 The software output control forces 0 to the channel output. The software output control forces 1 to the channel output. Channel 0 Software Output Control Value CH0OCV Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 905 The channel output is affected by software output control. Channel 0 Software Output Control Enable CH0OC The channel output is not affected by software output control. The channel output is affected by software output control. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 906: Ftm Pwm Load (Ftmx_Pwmload)
The global load mechanism depends on SoC specific information. Refer to FTM SoC specific information to more details. No action. LDOK bit is set. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 907 Channel match is included as a reload opportunity. Channel 1 Select CH1SEL Channel match is not included as a reload opportunity. Channel match is included as a reload opportunity. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 908: Half Cycle Register (Ftmx_Hcr)
Half Cycle Value 39.4.29 Mirror of Modulo Value (FTMx_MOD_MIRROR) This register contains the integer and fractional modulo value for the FTM counter. Address: Base address + 200h offset FRACMOD Reset Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 909: Mirror Of Channel (N) Match Value (Ftmx_Cnv_Mirror)
This read-only field is reserved and always has the value 0. 39.5 Functional description The notation used in this document to represent the counters and the generation of the signals is shown in the following figure. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 910: Clock Source
Refer to the chip specific documentation for further information. Due to FTM hardware implementation limitations, the frequency of the fixed frequency clock must not exceed 1/2 of the FTM input clock frequency. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 911: Prescaler
The FTM counter has these modes of operation: • Up counting • Up-down counting • Quadrature Decoder mode 39.5.3.1 Up counting Up counting is selected when: • QUADEN = 0, and • CPWMS = 0 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 912 FTM counting is up and signed. CNTIN[15] = 0 and CNTIN ≠ 0x0000 The initial value of the FTM counter is a positive number, so the FTM counting is up and unsigned. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 913 FTM operation difficult to comprehend. However, there is no restriction on this configuration, and an example is shown in the following figure. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 914 The TOF bit is set when the FTM counter changes from MOD to (MOD – 1). If (CNTIN = 0x0000), the FTM counting is equivalent to TPM up-down counting, that is, up-down and unsigned counting. See the following figure. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 915 = 2 x (MOD - CNTIN) x period of FTM counter clock = 2 x MOD x period of FTM counter clock Figure 39-10. Example of counter events in up-down counting mode when CNTIN = 0x0000 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 916 • A channel in Input Capture mode with ICRST = 1 (FTM Counter Reset in Input Capture Mode). Note that reseting the counter also generates a counter event. See Counter events more details. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 917: Channel Modes
Pin not used for FTM—revert the channel pin to general purpose I/O or other peripheral control Input Capture Capture on Rising Edge Only Capture on Falling Edge Only Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 918 Table 39-6. Dual Edge Capture Mode — Edge Polarity Selection ELSB ELSA Channel Port Enable Detected Edges Disabled No edge Enabled Rising edge Enabled Falling edge Enabled Rising and falling edges Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 919: Input Capture Mode
* Filtering function is only available in the inputs of channel 0, 1, 2, and 3 FTM counter Figure 39-12. Input Capture mode Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 920 (CHnFVAL[3:0] × 4 FTM input clocks) plus a further 4 rising edges of the FTM input clock: two rising edges to the Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 921 CnV register, the CHF bit is set, the channel (n) interrupt is generated (if CHIE = 1) and the FTM counter is reset to the CNTIN register value. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 922: Output Compare Mode
When the counter matches the value in the CnV register of an output compare channel, the channel (n) output can be set, cleared, or toggled. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 923 If (ELSB:ELSA = 0:0) when the counter reaches the value in the CnV register, the CHF bit is set and the channel (n) interrupt is generated if CHIE = 1, however the channel (n) output is not modified and controlled by FTM. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 924: Edge-Aligned Pwm (Epwm) Mode
If (ELSB:ELSA = 1:0), then the channel (n) output is forced high at the counter overflow when the CNTIN register value is loaded into the FTM counter, and it is forced low at the channel (n) match (FTM counter = CnV). See the following figure. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 925 • 0% EPWM signal if CnV = CNTIN, • EPWM signal between 0% and 100% if CNTIN < CnV <= MOD, • 100% EPWM signal when CNTIN > CnV or CnV > MOD. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 926: Center-Aligned Pwm (Cpwm) Mode
If (ELSB:ELSA = 1:0), then the channel (n) output is forced high at the channel (n) match (FTM counter = CnV) when counting down, and it is forced low at the channel (n) match when counting up. See the following figure. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 927: Combine Mode
The CPWM mode must not be used when the FTM counter is a free running counter. 39.5.9 Combine mode The Combine mode is selected when: • QUADEN = 0 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 928 (n) match channel (n) output with ELSB:ELSA = 1:0 channel (n) output with ELSB:ELSA = X:1 Figure 39-26. Combine mode The following figures illustrate the PWM signals generation using Combine mode. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 929 C(n)V = CNTIN channel (n) output with ELSB:ELSA = 1:0 channel (n) output with ELSB:ELSA = X:1 Figure 39-29. Channel (n) output if (C(n)V = CNTIN) and (CNTIN < C(n+1)V < MOD) Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 930 0% duty cycle with ELSB:ELSA = X:1 Figure 39-31. Channel (n) output if (C(n)V = CNTIN) and (CNTIN < C(n+1)V < MOD) and (C(n+1)V is Almost Equal to MOD) Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 931 (n) output 100% duty cycle with ELSB:ELSA = X:1 Figure 39-33. Channel (n) output if (CNTIN < C(n)V < MOD) and (CNTIN < C(n+1)V < MOD) and (C(n)V = C(n+1)V) Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 932 (n) output 100% duty cycle with ELSB:ELSA = X:1 Figure 39-36. Channel (n) output if (CNTIN < C(n)V < MOD) and (CNTIN < C(n+1)V < MOD) and (C(n)V > C(n+1)V) Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 933 C(n+1)V channel (n) output with ELSB:ELSA = 1:0 channel (n) output with ELSB:ELSA = X:1 Figure 39-38. Channel (n) output if (C(n+1)V < CNTIN) and (CNTIN < C(n)V < MOD) Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 934 CNTIN channel (n) output with ELSB:ELSA = 1:0 channel (n) output with ELSB:ELSA = X:1 Figure 39-40. Channel (n) output if (C(n+1)V > MOD) and (CNTIN < C(n)V < MOD) Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 935: Complementary Mode
PWM second edge (channel (n+1) match: FTM counter = C(n+1)V). 39.5.10 Complementary Mode The Complementary mode is selected when: • QUADEN = 0 • DECAPEN = 0 • COMP = 1 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 936: Registers Updated From Write Buffers
FTM has many ways to synchronize PWM registers. Current implementation allows to bypass the buffers, use legacy and PWM synchronization (hardware and software trigger) and it is also possible to use a half or full cycle reload strategy. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 937 The following table describes when CnV register is updated: Table 39-9. CnV register update When Then CnV register is updated CLKS[1:0] = 0:0 When CnV register is written, independent of FTMEN bit. Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 938: Pwm Synchronization
FTM input clock. The PWM synchronization with hardware trigger is initiated when a rising edge is detected at the enabled hardware trigger inputs. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 939 PWMSYNC and REINIT bits. In this case if (PWMSYNC = 1) or (PWMSYNC = 0 and REINIT = 0) then SWSYNC bit is cleared at the next selected loading point after that the Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 940 • if (CNTMAX = 1), when the FTM counter changes from (MOD - 1) to MOD; • if (CNTMIN = 1), when the FTM counter changes from (CNTIN + 1) to CNTIN. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 941 = 0). However, it is expected that the MOD register be synchronized only by the enhanced PWM synchronization. In the case of enhanced PWM synchronization, the MOD register synchronization depends on SWWRBUF, SWRSTCNT, HWWRBUF, and HWRSTCNT bits according to this flowchart: Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 942 If the trigger event was a software trigger, then the SWSYNC bit is cleared on the next selected Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 943 SWSYNC bit is cleared according to the following example. If the trigger event was a hardware trigger, then the TRIGn bit is cleared according to Hardware trigger. Examples with software and hardware triggers follow. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 944 FTM input clock write 1 to SWSYNC bit SWSYNC bit software trigger event selected loading point MOD register is updated Figure 39-53. MOD synchronization with (SYNCMODE = 0) and (PWMSYNC = 1) Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 945 SYNCMODE = 0). However, it is expected that the OUTMASK register be synchronized only by the enhanced PWM synchronization. In the case of enhanced PWM synchronization, the OUTMASK register synchronization depends on SWOM and HWOM bits. See the following flowchart: Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 946 ? clear TRIGn bit Figure 39-54. OUTMASK register synchronization flowchart In the case of legacy PWM synchronization, the OUTMASK register synchronization depends on PWMSYNC bit according to the following description. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 947 If (SYNCMODE = 0), (SYNCHOM = 1), and (PWMSYNC = 1), then this synchronization is made on the next enabled hardware trigger. The TRIGn bit is cleared according to Hardware trigger. An example with a hardware trigger follows. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 948 0) or by the enhanced PWM synchronization (INVC = 1 and SYNCMODE = 1) according to the following flowchart. In the case of enhanced PWM synchronization, the INVCTRL register synchronization depends on SWINVC and HWINVC bits. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 949 HWTRIGMODE bit ? clear TRIGn bit Figure 39-58. INVCTRL register synchronization flowchart 39.5.12.9 SWOCTRL register synchronization The SWOCTRL register synchronization updates the SWOCTRL register with its buffer value. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 950 ? wait hardware trigger n update SWOCTRL with its buffer value update SWOCTRL with its buffer value HWTRIGMODE bit ? clear TRIGn bit Figure 39-59. SWOCTRL register synchronization flowchart Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 951 = 0). However, the FTM counter must be synchronized only by the enhanced PWM synchronization. In the case of enhanced PWM synchronization, the FTM counter synchronization depends on SWRSTCNT and HWRSTCNT bits according to the following flowchart. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 952 SWSYNC bit is cleared according to the following example. If the trigger event was a hardware trigger then the TRIGn bit is cleared according to Hardware trigger. Examples with software and hardware triggers follow. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 953 Figure 39-64. FTM counter synchronization with (SYNCMODE = 0), (HWTRIGMODE = 0), (REINIT = 1), (PWMSYNC = 1), and a hardware trigger was used Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 954: Inverting
NOTE INV(m) bit selects the inverting to the pair channels (n) and (n+1). Figure 39-65. Channels (n) and (n+1) outputs after the inverting in High-True (ELSB:ELSA = 1:0) Combine mode Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 955: Software Output Control Mode
The software output control forces the channel output according to software defined values at a specific time in the PWM generation. The software output control is selected when: • QUADEN = 0 • DECAPEN = 0, and • CH(n)OC = 1 Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 956 Software output control forces the following values on channels (n) and (n+1) when the COMP bit is one. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 957: Deadtime Insertion
(FTM counter = C(n)V) occurs, the channel (n) output remains at the high value until the end of the deadtime delay when the channel (n) output is cleared. Similarly, Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 958 • The deadtime feature must be used only in Complementary mode. • The deadtime feature is not available in Output Compare mode. 39.5.15.1 Deadtime insertion corner cases If (PS[2:0] is cleared), (DTPS[1:0] = 0:0 or DTPS[1:0] = 0:1): Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 959 Figure 39-71. Example of the deadtime insertion (ELSB:ELSA = 1:0, POL(n) = 0, and POL(n+1) = 0) when the deadtime delay is comparable to channels (n) and (n+1) duty cycle Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 960: Output Mask
Table 39-12. Output mask result for channel (n) before the polarity control CH(n)OM Output Mask Input Output Mask Result inactive state inactive state active state active state inactive state inactive state active state Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 961: Fault Control
FAULTFn* control detector Fault filter (5-bit counter) FTM input clock * where n = 3, 2, 1, 0 Figure 39-73. Fault input n control block diagram Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 962 If the automatic fault clearing is selected (FAULTM[1:0] = 1:1), then the channels output disabled by fault control is again enabled when the fault input signal (FAULTIN) returns to zero and a new PWM cycle begins. See the following figure. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 963 If the manual fault clearing is selected (FAULTM[1:0] = 0:1 or 1:0), then the channels output disabled by fault control is again enabled when the FAULTF bit is cleared and a new PWM cycle begins. See the following figure. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 964: Polarity Control
• If POLn = 1, the channel (n) output polarity is low, so the logical zero is the active state and the logical one is the inactive state. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 965: Initialization
See the description of the CLKS field in the Status and Control register. 39.5.20 Features priority The following figure shows the priority of the features used at the generation of channels (n) and (n+1) outputs signals. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 966: External Trigger
0, 1, 2, 3, 4, 5, 6 or 7, then the FTM generates a trigger when the channel (j) match occurs (FTM counter = C(j)V). The external trigger feature provides a trigger signal which has one FTM clock period width and is used for on-chip modules. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 967: Channel Trigger Output
(d) CH0TRIG = 1, CH1TRIG = 1, CH2TRIG = 1, CH3TRIG = 1, CH4TRIG = 1, CH5TRIG = 1 Figure 39-78. External Trigger 39.5.22 Channel trigger output The channel trigger output provides a trigger signal which has one FTM clock period width in the channel output signal. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 968: Initialization Trigger
INITTRIGEN = 1 and ITRIGR = 0, then FTM generates a trigger when the FTM counter is updated with the CNTIN register value in the following cases: • In all cycles that FTM counter is automatically updated with CNTIN register value. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 969 0x04 0x05 0x06 0x00 0x01 0x02 0x03 0x04 0x05 0x06 FTM counter write to CNT initialization trigger Figure 39-82. Initialization trigger is generated when there is a write to CNT register Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 970 Figure 39-85. Initialization trigger is generated if the channel (n) is in Input Capture mode, ICRST = 1 and the selected input capture event occurs in the channel (n) input Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 971: Capture Test Mode
FTM counter. The next reads of CnV registers return the written value to the FTM counter and the next reads of CNT register return FTM counter next value. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 972 If DMA = 1, the CHF bit is cleared either by channel DMA transfer done or reading CnSC while CHF is set and then writing a zero to CHF bit according to CHIE bit. See the following table. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 973: Dual Edge Capture Mode
If these bits select different edges, then it is a pulse width measurement. In the Dual Edge Capture mode, only channel (n) input is used and channel (n+1) input is ignored. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 974 (n+1) is captured. Therefore, while DECAP bit is set, the one-shot capture is in process. When this bit is cleared, both edges were captured and the captured values are ready for reading in the C(n)V and C(n+1)V registers. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 975 (n) ELSB:ELSA bits. The channel (n+1) CHF bit is set and DECAP bit is cleared when the second edge of this pulse is Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 976 (n+1) ELSB:ELSA bits. The channel (n+1) CHF bit indicates when two edges of the pulse were captured and the C(n)V and C(n+1)V registers are ready for reading. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 977 (channel (n) ELSB:ELSA = 1:0 and channel (n+1) ELSB:ELSA = 1:0), then the period between two consecutive falling edges is measured. The period measurement can be made in One-Shot Capture mode Continuous Capture mode. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 978 Dual Edge Capture mode, so it remains set. While the DECAP bit is set the configured measurements are made. The channel (n) CHF bit is set when the first rising Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 979 (n) input signal, and channel (n+1) to capture the FTM counter value when there is a falling edge at channel (n) input signal. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 980: Quadrature Decoder Mode
The Quadrature Decoder mode is selected if (QUADEN = 1). The Quadrature Decoder mode uses the input signals phase A and B to control the FTM counter increment and decrement. The following figure shows the quadrature decoder block diagram. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 981 An edge at phase A must not occur together an edge at phase B and vice-versa. The PHAPOL bit selects the polarity of the phase A input, and the PHBPOL bit selects the polarity of the phase B input. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 982 • there is a rising edge at phase B signal and phase A signal is at logic zero; • there is a rising edge at phase A signal and phase B signal is at logic one. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 983 FTM counter changes from CNTIN to MOD, TOF bit is set and TOFDIR bit is cleared. TOF bit indicates the FTM counter overflow occurred. TOFDIR indicates the counting was down when the FTM counter overflow occurred. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 984 FTM counter CNTIN 0x0000 Time Figure 39-98. Motor position jittering in a mid count value The following figure shows motor jittering produced by the phase B and A pulses respectively: Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 985: Debug Mode
Stopped is not set The channels outputs are frozen Writes to these registers bypass the registers when the chip enters in Debug buffers mode Table continues on the next page... Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 986: Reload Points
For example, if the load frequency is zero, then any reload opportunity is also a reload point. Note that when a reload point is Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 987 Note that the example below also uses a channel match as reload opportunity, but generally applications uses only the half cycle match if a non full cycle reload is needed. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 988 After enabling the reload opportunities, the LDOK bit must be set for the reload to occur. In this case, the reload occurs at the next enabled reload point considering the Load Frequency according to the following conditions: Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 989: Global Load
The figure below shows an example of connection between FTM global load inputs and outputs considering that GLDOK bit is implemented outside from FTM module. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 990: Global Time Base (Gtb)
FTM counters enabled if at least one of the gtb_out signals from one of the FTM modules is 1. There are several possible configurations for the interconnection of the gtb_in and Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 991: Output Logic
PWM_EN is enabled and there is no fault event ongoing configured to tri-state the outputs by FSTATE bit at FTM_FLTCTRL register. Note that Polarity logic will act before channel enable logic. Therefore, it is imperative that the user program the channel Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 992: Dithering
• the FRACMOD is updated with the value of its write buffer, or • the FTM counter is stopped. NOTE For the PWM period dithering, the register MOD_MIRROR should be used instead of the register MOD. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 993 MOD is 0xFFFE for PWM period dithering with unsigned counting and 0x7FFE for PWM period dithering with signed counting. The figure belows an examples of PWM period dithering when the FTM counter is an up counter. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 994 (in decimal) is [(MOD - CNTIN + 1) + (FRACMOD/32)] x T, where the integer value is (MOD - CNTIN + 1) and the fractional value is (FRACMOD/ 32). See the example below. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 995 Due to one unit of FTM counter that can be added to the PWM period, the largest valid value for MOD is 0x7FFE for PWM period dithering in up-down counting (CPWM mode). Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 996 VAL of the register C(n)V is updated with the value of its write buffer. The PWM edge dithering is not available: • to the channel in input modes, and • to the channel in output compare mode. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 997 T is the period of one unit of FTM counter channel (n) output accumulator 0x1B 0x1E 0x01 overflow Figure 39-107. Channel (n) is in EPWM Mode with PWM Edge Dithering Assuming: Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 998 CPWM duty cycle happens on channel (n) match (FTM counter = C(n)V) when the FTM counter is decrementing, and the final edge of CPWM duty cycle on channel (n) match when the FTM counter is incrementing. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 999 (FTM counter = C(n)V + 0x0001). The figure below shows an example of the channel (n) match edge dithering when the channels (n) and (n+1) are in Combine mode. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 NXP Semiconductors...
Page 1000 (n+1) match edge happens when (FTM counter = C(n+1)V + 0x0001). The figure below shows an example of the channel (n+1) match edge dithering when the channels (n) and (n+1) are in Combine mode. Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018 1000 NXP Semiconductors...

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NXP Semiconductors Kinetis KE1xZ256 Reference Manual

Chapter 1 About this Manual

Chapter 2 Introduction

Chapter 3 Core Overview

Chapter 4 Interrupts

Chapter 5 System Integration Module (SIM)

Chapter 6 Memory-Mapped Divide and Square Root (MMDVSQ)

Chapter 7 Miscellaneous Control Module (MCM)

Chapter 8 Bit Manipulation Engine (BME)

Chapter 9 Crossbar Switch Lite (AXBS-Lite)

Chapter 10 Peripheral Bridge (AIPS-Lite)

Chapter 11 Trigger MUX Control (TRGMUX)

Chapter 12 Direct Memory Access Multiplexer (DMAMUX)

Chapter 13 Enhanced Direct Memory Access (Edma)

Chapter 14 Memory and Memory Map

Chapter 15 Flash Acceleration Unit (FAU)

Chapter 16 Flash Memory Module (FTFE)

Chapter 18 System Clock Generator (SCG)

Chapter 19 RTC Oscillator (OSC32)

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