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Memory map and register definitions
For more information regarding the calibration procedure, please refer to the
function
section.
Address: 4003_B000h base + 30h offset = 4003_B030h
Bit
31
30
29
28
27
26
R
W
0
0
0
0
0
0
Reset
Field
31–16
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
MG
Minus-Side Gain
23.4.11 ADC Plus-Side General Calibration Value Register
(ADCx_CLPD)
The Plus-Side General Calibration Value Registers (CLPx) contain calibration
information that is generated by the calibration function. These registers contain seven
calibration values of varying widths: CLP0[5:0], CLP1[6:0], CLP2[7:0], CLP3[8:0],
CLP4[9:0], CLPS[5:0], and CLPD[5:0]. CLPx are automatically set when the self-
calibration sequence is done, that is, CAL is cleared. If these registers are written by the
user after calibration, the linearity error specifications may not be met.
For more information regarding the calibration procedure, please refer to the
function
section.
Address: 4003_B000h base + 34h offset = 4003_B034h
Bit
31
30
29
28
27
26
R
W
0
0
0
0
0
0
Reset
Field
31–6
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
CLPD
Calibration Value
Calibration Value
356
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
0
ADCx_MG field descriptions
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
0
ADCx_CLPD field descriptions
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
17
16
15
14
13
12
11
10
0
0
1
0
0
0
0
0
Description
17
16
15
14
13
12
11
10
0
0
0
0
0
0
0
0
Description
Calibration
9
8
7
6
5
4
3
2
MG
1
0
0
0
0
0
0
0
Calibration
9
8
7
6
5
4
3
2
CLPD
0
0
0
0
0
0
1
0
Freescale Semiconductor, Inc.
1
0
0
0
1
0
1
0
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