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Field
31–16
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
OFS
Offset Error Correction Value
23.4.9 ADC Plus-Side Gain Register (ADCx_PG)
The Plus-Side Gain Register (PG) contains the gain error correction for the plus-side
input in differential mode or the overall conversion in single-ended mode. PG, a 16-bit
real number in binary format, is the gain adjustment factor, with the radix point fixed
between PG[15] and PG[14]. This register must be written by the user with the value
described in the calibration procedure. Otherwise, the gain error specifications may not
be met.
For more information regarding the calibration procedure, please refer to the
function
section.
Address: 4003_B000h base + 2Ch offset = 4003_B02Ch
Bit
31
30
29
28
27
26
R
W
0
0
0
0
0
0
Reset
Field
31–16
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
PG
Plus-Side Gain
23.4.10 ADC Minus-Side Gain Register (ADCx_MG)
The Minus-Side Gain Register (MG) contains the gain error correction for the minus-side
input in differential mode. This register is ignored in single-ended mode. MG, a 16-bit
real number in binary format, is the gain adjustment factor, with the radix point fixed
between MG[15] and MG[14]. This register must be written by the user with the value
described in the calibration procedure. Otherwise, the gain error specifications may not
be met.
Freescale Semiconductor, Inc.
ADCx_OFS field descriptions
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
0
ADCx_PG field descriptions
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Chapter 23 Analog-to-Digital Converter (ADC)
Description
17
16
15
14
13
12
11
10
0
0
1
0
0
0
0
0
Description
Calibration
9
8
7
6
5
4
3
2
PG
1
0
0
0
0
0
0
0
1
0
0
0
355
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