Overview; Features - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Table of Contents

Introduction

42.1.1 Overview

The following figure is a generic block diagram of the processor core and platform for

this class of ultra low-end microcontrollers.

Note: BME can be accessed only by the core.

Figure 42-1. Cortex-M0+ core platform block diagram

As shown in the block diagram, the BME module interfaces to a crossbar switch AHB

slave port as its primary input and sources an AHB bus output to the Peripheral Bridge

(PBRIDGE) controller. The BME hardware microarchitecture is a 2-stage pipeline design

matching the protocol of the AMBA-AHB system bus interfaces. The PBRIDGE module

converts the AHB system bus protocol into the IPS/APB protocol used by the attached

slave peripherals.

The key features of the BME include:

• Lightweight implementation of decorated storage for selected address spaces

Cortex-M0+ Core

KL27 Sub-Family Reference Manual , Rev. 5, 01/2016

CM0+ Core Platform

Freescale Semiconductor, Inc.