NXP Semiconductors freescale KV4 Series Reference Manual

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KV4x Reference Manual

Supports MKV46, MKV45, MKV44, MKV43, MKV41, MKV40 part

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Document Number: KV4XP100M150RM

Rev 2, 02/2015

Preliminary

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Page 1 KV4x Reference Manual Supports MKV46, MKV45, MKV44, MKV43, MKV41, MKV40 part numbers Document Number: KV4XP100M150RM Rev 2, 02/2015 Preliminary...
Page 2 KV4x Reference Manual, Rev. 2, 02/2015 Preliminary Freescale Semiconductor, Inc.
Page 3 Contents Section number Title Page Chapter 1 About This Document Overview..................................61 1.1.1 Purpose................................61 1.1.2 Audience................................ 61 Conventions.................................. 61 1.2.1 Numbering systems............................61 1.2.2 Typographic notation............................. 62 1.2.3 Special terms..............................62 Chapter 2 Introduction Overview..................................63 Module Functional Categories............................63 2.2.1 ARM® Cortex®-M4 Core Modules......................64 2.2.2 System Modules.............................
Page 4 Section number Title Page 3.1.3 Debug facilities.............................. 74 3.1.4 Core privilege levels............................75 Nested Vectored Interrupt Controller (NVIC) Configuration..................75 3.2.1 Interrupt priority levels..........................75 3.2.2 Non-maskable interrupt..........................75 3.2.3 Interrupt vector assignments ......................... 76 Asynchronous Wake-up Interrupt Controller (AWIC) Configuration................79 3.3.1 Wake-up sources............................
Page 5 Section number Title Page Chapter 6 Clock Distribution Introduction...................................95 High-level device clocking diagram..........................95 6.2.1 Clock definitions............................96 Internal clocking requirements............................. 97 6.3.1 Clock divider values after reset........................98 6.3.2 VLPR mode clocking.............................99 Clock Gating................................. 99 Module clocks................................100 6.5.1 nano edge module clocking..........................101 6.5.2 WDOG clocking............................
Page 6 Section number Title Page Power modes shutdown sequencing..........................113 Clock Gating................................. 113 Flash Program Restrictions............................114 Chapter 8 Security Introduction...................................115 Flash Security................................115 Security Interactions with other Modules........................116 8.3.1 Security Interactions with Debug........................116 Chapter 9 Debug Introduction...................................117 9.1.1 References..............................119 The Debug Port................................
Page 7 Section number Title Page 10.2 Reset....................................129 10.2.1 Power-on reset (POR)............................ 130 10.2.2 System resets..............................130 10.2.2.1 External pin reset (PIN)......................130 10.2.2.2 Low-voltage detect (LVD) reset....................131 10.2.2.3 Computer operating properly (COP) watchdog reset..............132 10.2.2.4 Low leakage wakeup (LLWU) reset..................132 10.2.2.5 Multipurpose clock generator loss-of-clock (LOC) reset............
Page 8 Section number Title Page Chapter 12 Port control and interrupts (PORT) 12.1 Introduction...................................151 12.2 Overview..................................151 12.2.1 Features................................151 12.2.2 Modes of operation............................152 12.2.2.1 Run mode........................... 152 12.2.2.2 Wait mode..........................152 12.2.2.3 Stop mode..........................152 12.2.2.4 Debug mode..........................152 12.3 External signal description............................153 12.4 Detailed signal description............................153...
Page 9 Section number Title Page 13.2 Memory map and register definition..........................172 13.2.1 System Options Register 1 (SIM_SOPT1)....................173 13.2.2 System Options Register 2 (SIM_SOPT2)....................174 13.2.3 System Options Register 4 (SIM_SOPT4)....................176 13.2.4 System Options Register 5 (SIM_SOPT5)....................179 13.2.5 System Options Register 7 (SIM_SOPT7)....................180 13.2.6 System Options Register 8 (SIM_SOPT8)....................
Page 10 Section number Title Page Chapter 14 Kinetis Flashloader 14.1 Introduction...................................213 14.2 Functional Description..............................214 14.2.1 Memory Maps..............................214 14.2.2 Start-up Process..............................215 14.2.3 Clock Configuration............................217 14.2.4 Flashloader Protocol............................217 14.2.4.1 Command with no data phase....................217 14.2.4.2 Command with incoming data phase..................218 14.2.4.3 Command with outgoing data phase..................
Page 11 Section number Title Page 14.3 Peripherals Supported..............................242 14.3.1 I2C Peripheral..............................242 14.3.2 SPI Peripheral..............................244 14.3.3 UART Peripheral............................246 14.3.4 CAN (or FlexCAN) Peripheral........................249 14.4 Get/SetProperty Command Properties..........................251 14.4.1 Property Definitions............................252 14.4.1.1 CurrentVersion Property......................252 14.4.1.2 AvailablePeripherals Property....................252 14.4.1.3 AvailableCommands Property....................
Page 12 Section number Title Page 16.3.4 Power Mode Status register (SMC_PMSTAT)..................... 272 16.4 Functional description..............................273 16.4.1 Power mode transitions..........................273 16.4.2 Power mode entry/exit sequencing........................ 276 16.4.2.1 Stop mode entry sequence......................276 16.4.2.2 Stop mode exit sequence......................276 16.4.2.3 Aborted stop mode entry......................276 16.4.2.4 Transition to wait modes......................277 16.4.2.5...
Page 13 Section number Title Page 17.2.4 Interrupt Status Register (MCM_ISR)......................289 17.2.5 Compute Operation Control Register (MCM_CPO)..................291 17.3 Functional description..............................292 17.3.1 Interrupts................................ 292 17.3.1.1 Non-maskable interrupt......................292 17.3.1.2 Normal interrupt.........................292 17.4 Functional description..............................293 17.4.1 Interrupts................................ 293 17.4.1.1 Determining source of the interrupt................... 293 Chapter 18 Power Management Controller (PMC) 18.1...
Page 14 Section number Title Page 19.2.2.2 Non-low leakage modes......................305 19.2.2.3 Debug mode..........................305 19.2.3 Block diagram..............................305 19.3 LLWU signal descriptions............................305 19.4 Memory map/register definition........................... 306 19.4.1 LLWU Pin Enable 1 register (LLWU_PE1)....................307 19.4.2 LLWU Pin Enable 2 register (LLWU_PE2)....................308 19.4.3 LLWU Pin Enable 3 register (LLWU_PE3)....................309 19.4.4...
Page 15 Section number Title Page 20.2 Introduction...................................332 20.2.1 Features................................332 20.3 Memory Map / Register Definition..........................333 20.4 Functional Description..............................333 20.4.1 General operation............................333 20.4.2 Arbitration..............................334 20.4.2.1 Arbitration during undefined length bursts................334 20.4.2.2 Fixed-priority operation......................334 20.4.2.3 Round-robin priority operation....................335 20.5 Initialization/application information...........................
Page 16 Section number Title Page 22.1.2 DMA transfers via PIT trigger........................355 22.2 Introduction...................................355 22.2.1 Overview................................ 355 22.2.2 Features................................356 22.2.3 Modes of operation............................356 22.3 External signal description............................357 22.4 Memory map/register definition........................... 357 22.4.1 Channel Configuration register (DMAMUX_CHCFGn)................358 22.5 Functional description..............................359 22.5.1 DMA channels with periodic triggering capability..................359...
Page 17 Section number Title Page 23.3.3 Enable Request Register (DMA_ERQ)......................388 23.3.4 Enable Error Interrupt Register (DMA_EEI)....................390 23.3.5 Clear Enable Error Interrupt Register (DMA_CEEI)..................392 23.3.6 Set Enable Error Interrupt Register (DMA_SEEI)..................393 23.3.7 Clear Enable Request Register (DMA_CERQ)..................... 394 23.3.8 Set Enable Request Register (DMA_SERQ)....................
Page 18 Section number Title Page 23.3.29 TCD Last Destination Address Adjustment/Scatter Gather Address (DMA_TCDn_DLASTSGA).... 420 23.3.30 TCD Control and Status (DMA_TCDn_CSR)....................421 23.3.31 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCDn_BITER_ELINKYES)......................423 23.3.32 TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (DMA_TCDn_BITER_ELINKNO)......................
Page 19 Section number Title Page 23.5.7 Dynamic programming..........................445 23.5.7.1 Dynamically changing the channel priority................445 23.5.7.2 Dynamic channel linking......................446 23.5.7.3 Dynamic scatter/gather......................446 Chapter 24 External Watchdog Monitor (EWM) 24.1 Chip-specific EWM information..........................451 24.1.1 EWM clocks..............................451 24.1.2 EWM low-power modes..........................451 24.1.3 EWM_OUT pin state in low power modes....................451 24.2...
Page 20 Section number Title Page Chapter 25 Watchdog Timer (WDOG) 25.1 Chip-specific WDOG information..........................461 25.1.1 WDOG clocks..............................461 25.1.2 WDOG low-power modes..........................461 25.2 Introduction...................................462 25.3 Features..................................462 25.4 Functional overview..............................463 25.4.1 Unlocking and updating the watchdog......................465 25.4.2 Watchdog configuration time (WCT)......................466 25.4.3 Refreshing the watchdog..........................467 25.4.4...
Page 21 Section number Title Page 25.8.9 Watchdog Timer Output Register High (WDOG_TMROUTH)..............477 25.8.10 Watchdog Timer Output Register Low (WDOG_TMROUTL)..............478 25.8.11 Watchdog Reset Count register (WDOG_RSTCNT)..................478 25.8.12 Watchdog Prescaler register (WDOG_PRESC).................... 478 25.9 Watchdog operation with 8-bit access.......................... 479 25.9.1 General guideline............................
Page 22 Section number Title Page 26.4.5 Crossbar A Select Register 4 (XBARA_SEL4).....................493 26.4.6 Crossbar A Select Register 5 (XBARA_SEL5).....................493 26.4.7 Crossbar A Select Register 6 (XBARA_SEL6).....................494 26.4.8 Crossbar A Select Register 7 (XBARA_SEL7).....................494 26.4.9 Crossbar A Select Register 8 (XBARA_SEL8).....................495 26.4.10 Crossbar A Select Register 9 (XBARA_SEL9).....................495 26.4.11 Crossbar A Select Register 10 (XBARA_SEL10)..................496 26.4.12 Crossbar A Select Register 11 (XBARA_SEL11)..................496 26.4.13 Crossbar A Select Register 12 (XBARA_SEL12)..................497...
Page 23 Section number Title Page 26.5 Functional Description..............................510 26.5.1 General................................510 26.5.2 Functional Mode............................510 26.6 Resets.................................... 511 26.7 Clocks................................... 511 26.8 Interrupts and DMA Requests............................511 Chapter 27 Inter-Peripheral Crossbar Switch B (XBARB) 27.1 chip-specific XBARB information..........................513 27.1.1 XBARB signal input assignment........................513 27.1.2 XBARB signal output assignment.........................
Page 24 Section number Title Page 28.3 External Signal Description............................524 28.4 Memory Map and Register Descriptions........................524 28.4.1 Boolean Function Term 0 and 1 Configuration Register for EVENTn (AOI_BFCRT01n)......526 28.4.2 Boolean Function Term 2 and 3 Configuration Register for EVENTn (AOI_BFCRT23n)......527 28.5 Functional Description..............................529 28.5.1...
Page 25 Section number Title Page 29.8.2.4 High-Frequency, Low-Power Mode..................543 29.8.3 Counter................................543 29.8.4 Reference clock pin requirements........................543 29.9 Reset....................................543 29.10 Low power modes operation............................544 29.11 Interrupts..................................544 Chapter 30 Multipurpose Clock Generator (MCG) 30.1 Introduction...................................545 30.1.1 Features................................545 30.1.2 Modes of Operation............................548 30.2 External Signal Description............................
Page 26 Section number Title Page 30.4.3 MCG Internal Reference Clocks........................566 30.4.3.1 MCG Internal Reference Clock....................566 30.4.4 External Reference Clock..........................566 30.4.5 MCG Fixed Frequency Clock ........................567 30.4.6 MCG PLL clock ............................567 30.4.7 MCG Auto TRIM (ATM)..........................568 30.5 Initialization / Application information........................569 30.5.1 MCG module initialization sequence......................569 30.5.1.1...
Page 27 Section number Title Page 31.4.8 Cache Data Storage (uppermost word) (FMC_DATAW0SnUM)..............595 31.4.9 Cache Data Storage (mid-upper word) (FMC_DATAW0SnMU)..............595 31.4.10 Cache Data Storage (mid-lower word) (FMC_DATAW0SnML)..............596 31.4.11 Cache Data Storage (lowermost word) (FMC_DATAW0SnLM)..............596 31.4.12 Cache Data Storage (uppermost word) (FMC_DATAW1SnUM)..............597 31.4.13 Cache Data Storage (mid-upper word) (FMC_DATAW1SnMU)..............597 31.4.14 Cache Data Storage (mid-lower word) (FMC_DATAW1SnML)..............
Page 28 Section number Title Page 32.2 External Signal Description............................610 32.3 Memory Map and Registers............................610 32.3.1 Flash Configuration Field Description......................610 32.3.2 Program Flash IFR Map..........................611 32.3.2.1 Program Once Field........................612 32.3.3 Register Descriptions............................. 612 32.3.3.1 Flash Status Register (FTFA_FSTAT)..................614 32.3.3.2 Flash Configuration Register (FTFA_FCNFG).................
Page 29 Section number Title Page 32.4.9 Margin Read Commands..........................633 32.4.10 Flash Command Description..........................634 32.4.10.1 Read 1s Section Command......................635 32.4.10.2 Program Check Command......................636 32.4.10.3 Read Resource Command......................637 32.4.10.4 Program Longword Command....................638 32.4.10.5 Erase Flash Sector Command....................639 32.4.10.6 Read 1s All Blocks Command....................
Page 30 Section number Title Page 33.3.2 CRC calculations............................656 33.3.2.1 16-bit CRC..........................656 33.3.2.2 32-bit CRC..........................656 33.3.3 Transpose feature............................657 33.3.3.1 Types of transpose........................657 33.3.4 CRC result complement..........................659 Chapter 34 12-bit Cyclic Analog-to-Digital Converter (ADC) 34.1 Chip-specific Cyclic ADC information........................661 34.1.1 Cyclic ADC Instantiation..........................661 34.1.2...
Page 31 Section number Title Page 34.4.6 ADC Channel List Register 2 (ADC_CLIST2)..................... 680 34.4.7 ADC Channel List Register 3 (ADC_CLIST3)..................... 682 34.4.8 ADC Channel List Register 4 (ADC_CLIST4)..................... 684 34.4.9 ADC Sample Disable Register (ADC_SDIS)....................686 34.4.10 ADC Status Register (ADC_STAT)......................687 34.4.11 ADC Ready Register (ADC_RDY).......................
Page 32 Section number Title Page 34.5.6 Power Management............................715 34.5.6.1 Low Power Modes........................715 34.5.6.2 Startup in Different Power Modes..................... 716 34.5.6.3 Stop Mode of Operation......................717 34.6 Reset....................................718 34.7 Clocks................................... 718 34.8 Interrupts..................................720 34.9 Timing Specifications..............................721 Chapter 35 Comparator (CMP) 35.1 Chip-specific CMP information............................723 35.1.1...
Page 33 Section number Title Page 35.4 Functional description..............................736 35.4.1 CMP functional modes...........................736 35.4.1.1 Disabled mode (# 1)........................738 35.4.1.2 Continuous mode (#s 2A & 2B)....................738 35.4.1.3 Sampled, Non-Filtered mode (#s 3A & 3B)................739 35.4.1.4 Sampled, Filtered mode (#s 4A & 4B)..................741 35.4.1.5 Windowed mode (#s 5A &...
Page 34 Section number Title Page Chapter 36 12-bit Digital-to-Analog Converter (DAC) 36.1 Chip-specific 12-bit DAC information......................... 753 36.1.1 12-bit DAC Instantiation Information......................753 36.1.2 12-bit DAC Output............................753 36.1.3 12-bit DAC Reference........................... 753 36.2 Introduction...................................754 36.3 Features..................................754 36.4 Block diagram................................754 36.5 Memory map/register definition........................... 755 36.5.1 DAC Data Low Register (DAC_DATnL).....................
Page 35 Section number Title Page 37.2 Introduction...................................766 37.2.1 Features................................767 37.2.2 Modes of Operation............................767 37.2.3 Block Diagram............................... 768 37.2.3.1 PWM Submodule........................769 37.3 Signal Descriptions............................... 770 37.3.1 PWM[n]_A and PWM[n]_B - External PWM Output Pair................770 37.3.2 PWM[n]_X - Auxiliary PWM Output signal....................770 37.3.3 FAULT[n] - Fault Inputs..........................771 37.3.4...
Page 36 Section number Title Page 37.4.15 Value Register 5 (PWMA_SMnVAL5)......................791 37.4.16 Fractional Control Register (PWMA_SMnFRCTRL)................... 791 37.4.17 Output Control Register (PWMA_SMnOCTRL)..................793 37.4.18 Status Register (PWMA_SMnSTS).......................794 37.4.19 Interrupt Enable Register (PWMA_SMnINTEN)..................796 37.4.20 DMA Enable Register (PWMA_SMnDMAEN)................... 798 37.4.21 Output Trigger Control Register (PWMA_SMnTCTRL)................799 37.4.22 Fault Disable Mapping Register 0 (PWMA_SMnDISMAP0)..............
Page 37 Section number Title Page 37.4.44 Output Enable Register (PWMA_OUTEN)....................814 37.4.45 Mask Register (PWMA_MASK)........................815 37.4.46 Software Controlled Output Register (PWMA_SWCOUT)................816 37.4.47 PWM Source Select Register (PWMA_DTSRCSEL)...................817 37.4.48 Master Control Register (PWMA_MCTRL)....................819 37.4.49 Master Control 2 Register (PWMA_MCTRL2).................... 820 37.4.50 Fault Control Register (PWMA_FCTRL)..................... 821 37.4.51 Fault Status Register (PWMA_FSTS)......................
Page 38 Section number Title Page 37.5.2.8 Deadtime Insertion Logic......................842 37.5.2.9 Fractional Delay Logic.......................847 37.5.2.10 Output Logic..........................848 37.5.2.11 E-Capture........................... 849 37.5.2.12 Fault Protection.......................... 851 37.5.3 PWM Generator Loading..........................855 37.5.3.1 Load Enable..........................855 37.5.3.2 Load Frequency..........................856 37.5.3.3 Reload Flag..........................857 37.5.3.4 Reload Errors..........................857 37.5.3.5 Initialization..........................
Page 39 Section number Title Page 38.2.3 Back-to-back acknowledgment connections....................868 38.2.4 DAC External Trigger Input Connections..................... 868 38.2.5 Block diagram..............................868 38.2.6 Modes of operation............................870 38.3 PDB signal descriptions..............................870 38.4 Memory map and register definition..........................870 38.4.1 Status and Control register (PDBx_SC)......................872 38.4.2 Modulus register (PDBx_MOD)........................
Page 40 Section number Title Page 38.6 Application information..............................887 38.6.1 Impact of using the prescaler and multiplication factor on timing resolution..........887 Chapter 39 FlexTimer Module (FTM) 39.1 Chip-specific FTM information............................889 39.1.1 Instantiation Information..........................889 39.1.2 External Clock Options..........................889 39.1.3 Fixed frequency clock............................ 890 39.1.4 FTM Interrupts...............................
Page 41 Section number Title Page 39.4.8 Counter Initial Value (FTMx_CNTIN)......................910 39.4.9 Capture And Compare Status (FTMx_STATUS)..................911 39.4.10 Features Mode Selection (FTMx_MODE)....................913 39.4.11 Synchronization (FTMx_SYNC)........................915 39.4.12 Initial State For Channels Output (FTMx_OUTINIT)...................917 39.4.13 Output Mask (FTMx_OUTMASK)....................... 918 39.4.14 Function For Linked Channels (FTMx_COMBINE)..................920 39.4.15 Deadtime Insertion Control (FTMx_DEADTIME)..................
Page 42 Section number Title Page 39.5.3.5 When the TOF bit is set......................954 39.5.4 Input Capture mode............................955 39.5.4.1 Filter for Input Capture mode....................956 39.5.4.2 FTM Counter Reset in Input Capture Mode................957 39.5.5 Output Compare mode........................... 958 39.5.6 Edge-Aligned PWM (EPWM) mode......................959 39.5.7 Center-Aligned PWM (CPWM) mode......................
Page 43 Section number Title Page 39.5.15 Output mask..............................995 39.5.16 Fault control..............................996 39.5.16.1 Automatic fault clearing......................998 39.5.16.2 Manual fault clearing......................... 998 39.5.16.3 Fault inputs polarity control....................... 999 39.5.17 Polarity control...............................999 39.5.18 Initialization..............................1000 39.5.19 Features priority............................. 1000 39.5.20 Channel trigger output........................... 1001 39.5.21 Initialization trigger............................1002 39.5.22 Capture Test mode............................
Page 44 Section number Title Page 39.8 Initialization Procedure..............................1025 Chapter 40 Periodic Interrupt Timer (PIT) 40.1 Chip-specific PIT information............................1027 40.1.1 PIT/DMA Periodic Trigger Assignments ..................... 1027 40.1.2 PIT Trigger Output Assignments........................1027 40.2 Introduction...................................1028 40.2.1 Block diagram..............................1028 40.2.2 Features................................1028 40.3 Signal description................................1029 40.4...
Page 45 Section number Title Page 41.2 Introduction...................................1040 41.2.1 Features................................1040 41.2.2 Decoder Block Diagram..........................1040 41.2.3 System Block Diagram..........................1041 41.2.4 Glitch Filter..............................1041 41.2.5 Edge Detect State Machine..........................1042 41.2.6 Position Counter.............................1042 41.2.7 Position Difference Counter...........................1043 41.2.8 Position Difference Counter Hold........................1043 41.2.9 Revolution Counter............................
Page 46 Section number Title Page 41.4.10 Upper Position Hold Register (ENC_UPOSH)..................... 1053 41.4.11 Lower Position Hold Register (ENC_LPOSH)..................... 1053 41.4.12 Upper Initialization Register (ENC_UINIT)....................1054 41.4.13 Lower Initialization Register (ENC_LINIT)....................1054 41.4.14 Input Monitor Register (ENC_IMR)......................1055 41.4.15 Test Register (ENC_TST)..........................1056 41.4.16 Control 2 Register (ENC_CTRL2)........................ 1057 41.4.17 Upper Modulus Register (ENC_UMOD)......................
Page 47 Section number Title Page 42.4 Memory map and register definition..........................1065 42.4.1 Low Power Timer Control Status Register (LPTMR_CSR)................. 1066 42.4.2 Low Power Timer Prescale Register (LPTMR_PSR)..................1067 42.4.3 Low Power Timer Compare Register (LPTMR_CMR)................1069 42.4.4 Low Power Timer Counter Register (LPTMR_CNR)................... 1069 42.5 Functional description..............................1070 42.5.1...
Page 48 Section number Title Page 43.3.2 CAN Tx .................................1082 43.4 Memory map/register definition........................... 1082 43.4.1 FlexCAN memory mapping...........................1082 43.4.2 Module Configuration Register (CANx_MCR).....................1087 43.4.3 Control 1 register (CANx_CTRL1)....................... 1093 43.4.4 Free Running Timer (CANx_TIMER)......................1096 43.4.5 Rx Mailboxes Global Mask Register (CANx_RXMGMASK)..............1097 43.4.6 Rx 14 Mask register (CANx_RX14MASK)....................
Page 49 Section number Title Page 43.5.4 Matching process............................1137 43.5.5 Move process..............................1141 43.5.5.1 Move-in............................1141 43.5.5.2 Move-out............................ 1143 43.5.6 Data coherence............................... 1143 43.5.6.1 Transmission abort mechanism....................1143 43.5.6.2 Mailbox inactivation........................1144 43.5.6.3 Mailbox lock mechanism......................1145 43.5.7 Rx FIFO................................. 1146 43.5.7.1 Rx FIFO under DMA Operation....................
Page 50 Section number Title Page Chapter 44 Serial Peripheral Interface (SPI) 44.1 Chip-specific SPI information............................1169 44.1.1 SPI Instantiation Information.........................1169 44.1.2 SPI signals..............................1169 44.1.3 SPI clocking..............................1169 44.1.4 Number of CTARs............................1169 44.1.5 TX FIFO size..............................1170 44.1.6 RX FIFO Size..............................1170 44.1.7 Number of PCS signals..........................
Page 51 Section number Title Page 44.3.4 PCS5/PCSS—Peripheral Chip Select 5/Peripheral Chip Select Strobe............1177 44.3.5 SCK—Serial Clock............................1177 44.3.6 SIN—Serial Input............................1177 44.3.7 SOUT—Serial Output............................1178 44.4 Memory Map/Register Definition..........................1178 44.4.1 Module Configuration Register (SPI_MCR)....................1180 44.4.2 Transfer Count Register (SPI_TCR)......................1183 44.4.3 Clock and Transfer Attributes Register (In Master Mode) (SPI_CTARn)............ 1183 44.4.4 Clock and Transfer Attributes Register (In Slave Mode) (SPI_CTARn_SLAVE)........
Page 52 Section number Title Page 44.5.3.4 Delay after Transfer (tDT)......................1208 44.5.3.5 Peripheral Chip Select Strobe Enable (PCSS )................1208 44.5.4 Transfer formats............................. 1210 44.5.4.1 Classic SPI Transfer Format (CPHA = 0)..................1210 44.5.4.2 Classic SPI Transfer Format (CPHA = 1)..................1211 44.5.4.3 Modified SPI Transfer Format (MTFE = 1, CPHA = 0)............
Page 53 Section number Title Page 44.6.6.3 Address Calculation for the First-in Entry and Last-in Entry in the RX FIFO......1229 Chapter 45 Inter-Integrated Circuit (I2C) 45.1 Chip-specific I2C information............................1231 45.1.1 I2C signals..............................1231 45.2 Introduction...................................1231 45.2.1 Features................................1231 45.2.2 Modes of operation............................1232 45.2.3 Block diagram..............................
Page 54 Section number Title Page 45.5.1.5 Repeated START signal......................1248 45.5.1.6 Arbitration procedure......................... 1249 45.5.1.7 Clock synchronization........................1249 45.5.1.8 Handshaking..........................1250 45.5.1.9 Clock stretching......................... 1250 45.5.1.10 I2C divider and hold values....................... 1250 45.5.2 10-bit address..............................1251 45.5.2.1 Master-transmitter addresses a slave-receiver................1252 45.5.2.2 Master-receiver addresses a slave-transmitter................1252 45.5.3 Address matching............................1253 45.5.4...
Page 55 Section number Title Page 46.1.2 UART signals..............................1265 46.1.3 UART wakeup............................... 1266 46.1.4 UART interrupts............................1266 46.2 Introduction...................................1267 46.2.1 Features................................1267 46.2.2 Modes of operation............................1268 46.2.2.1 Run mode........................... 1268 46.2.2.2 Wait mode..........................1268 46.2.2.3 Stop mode..........................1269 46.3 UART signal descriptions.............................1269 46.3.1 Detailed signal descriptions...........................
Page 56 Section number Title Page 46.4.18 UART FIFO Transmit Watermark (UARTx_TWFIFO)................1292 46.4.19 UART FIFO Transmit Count (UARTx_TCFIFO)..................1293 46.4.20 UART FIFO Receive Watermark (UARTx_RWFIFO).................1293 46.4.21 UART FIFO Receive Count (UARTx_RCFIFO)..................1294 46.5 Functional description..............................1294 46.5.1 Transmitter..............................1294 46.5.1.1 Transmitter character length...................... 1295 46.5.1.2 Transmission bit order.......................
Page 57 Section number Title Page 46.5.6 Loop operation............................... 1319 46.6 Reset....................................1319 46.7 System level interrupt sources............................1319 46.7.1 RXEDGIF description............................1320 46.7.1.1 RxD edge detect sensitivity......................1320 46.7.1.2 Clearing RXEDGIF interrupt request..................1320 46.7.1.3 Exit from low-power modes...................... 1321 46.8 DMA operation................................1321 46.9 Application information..............................1321 46.9.1...
Page 58 Section number Title Page 47.3 Memory map and register definition..........................1329 47.3.1 Port Data Output Register (GPIOx_PDOR)....................1331 47.3.2 Port Set Output Register (GPIOx_PSOR)......................1332 47.3.3 Port Clear Output Register (GPIOx_PCOR)....................1332 47.3.4 Port Toggle Output Register (GPIOx_PTOR)....................1333 47.3.5 Port Data Input Register (GPIOx_PDIR).......................1333 47.3.6 Port Data Direction Register (GPIOx_PDDR)....................1334 47.4...
Page 59 Section number Title Page 48.4 Functional description..............................1342 48.4.1 JTAGC reset configuration..........................1342 48.4.2 IEEE 1149.1-2001 (JTAG) Test Access Port....................1342 48.4.3 TAP controller state machine.........................1343 48.4.3.1 Enabling the TAP controller...................... 1344 48.4.3.2 Selecting an IEEE 1149.1-2001 register..................1345 48.4.4 JTAGC block instructions..........................1345 48.4.4.1 IDCODE instruction........................
Page 60 KV4x Reference Manual, Rev. 2, 02/2015 Preliminary Freescale Semiconductor, Inc.
Page 61: Chapter 1 About This Document
Chapter 1 About This Document Overview 1.1.1 Purpose This document describes the features, architecture, and programming model of the Freescale's KV4x family of microcontrollers. 1.1.2 Audience This document is primarily for system architects and software application developers who are using or considering using the microcontroller in a system. Conventions 1.2.1 Numbering systems The following suffixes identify different numbering systems:...
Page 62: Typographic Notation
Conventions 1.2.2 Typographic notation The following typographic notation is used throughout this document: Example Description placeholder, x Items in italics are placeholders for information that you provide. Italicized text is also used for the titles of publications and for emphasis. Plain lowercase letters are also used as placeholders for single letters and numbers.
Page 63: Chapter 2 Introduction
Chapter 2 Introduction 2.1 Overview This chapter provides an overview of the KV4x product family of ARM® Cortex®-M4 MCUs. It also presents high-level descriptions of the modules available on the devices covered by this document. 2.2 Module Functional Categories The modules on this device are grouped into functional categories. The following sections describe the modules assigned to each category in more detail.
Page 64: Arm® Cortex®-M4 Core Modules
Module Functional Categories Table 2-1. Module functional categories (continued) Module category Description Security • Cyclic Redundancy Check module for error detection Analog • Two 12-bit analog-to-digital converters (ADC) with 240 ns conversion time • Four high speed comparators (CMP) • Digital-to-analog converter (DAC) Timers •...
Page 65: System Modules
Chapter 2 Introduction Table 2-2. Core modules (continued) Module Description ™ Debug interfaces Most of this device's debug is based on the ARM CoreSight architecture. Four debug interface is supported: • JTAG Controller (JTAG) • IEEE 1149.7 JTAG (cJTAG) • Serial Wire Debug (SWD) •...
Page 66: Security And Integrity Modules
Module Functional Categories Table 2-3. System modules Module Description each product term containing true or complement values of the four selected inputs (A, B, C, D). 2.2.3 Memories and Memory Interfaces The following memories and memory interfaces are available on this device. Table 2-4.
Page 67: Analog Modules
Chapter 2 Introduction Table 2-6. Security and integrity modules Module Description Cyclic Redundancy Check (CRC) Hardware CRC generator circuit using 16/32-bit shift register. Error detection for all single, double, odd, and most multi-bit errors, programmable initial seed value, and optional feature to transpose input data and CRC result via transpose register. Watchdog (WDOG) The WDOG monitors internal system operation and forces a reset in case of failure.
Page 68 Module Functional Categories Table 2-8. Timer modules (continued) Module Description • 16-bit counter supporting free-running or initial/final value, and counting is up or up-down • Input capture, output compare, and edge-aligned and center-aligned eFlexPWM modes • Operation of FTM channels as pairs with equal outputs, pairs with complementary outputs, or independent channels with independent outputs •...
Page 69: Communication Interfaces
Chapter 2 Introduction Table 2-8. Timer modules (continued) Module Description • Configurable digital filter for inputs to remove glitches and ensure only true transitions are recorded • 32-bit position counter register • 16-bit position difference register • Maximum count frequency equals the IPBus clock rate •...
Page 70 Orderable part numbers and features 2.3 Orderable part numbers and features NOTE The 48-pin LQFP package for this product is not yet available. However, it is included in a Package Your Way program for Kinetis MCUs. Visit freescale.com/KPYW for more details. Part Core Flash...
Page 71 Chapter 2 Introduction • 16+2 = FTM0 8 channels, FTM3 8 channels and FTM1 2channels are available • 8+2 = FTM0 8 channels are available, FTM1 2channels are available 3. Package Your Way KV4x Reference Manual, Rev. 2, 02/2015 Preliminary Freescale Semiconductor, Inc.
Page 72 Orderable part numbers and features KV4x Reference Manual, Rev. 2, 02/2015 Preliminary Freescale Semiconductor, Inc.
Page 73: Chapter 3 Core Overview
Chapter 3 Core overview 3.1 ARM Cortex-M4 Core Configuration This section summarizes how the module has been configured in the chip. Full documentation for this module is provided by ARM and can be found at arm.com. Debug Interrupts SRAM Upper ARM Cortex-M4 Crossbar Modules...
Page 74: Buses, Interconnects, And Interfaces
ARM Cortex-M4 Core Configuration Table 3-1. Reference links to related information (continued) Topic Related module Reference Private Peripheral Bus Miscellaneous Control (PPB) module Module (MCM) Private Peripheral Bus Single-precision floating (PPB) module point unit (FPU) 3.1.1 Buses, interconnects, and interfaces The ARM Cortex-M4 core has four buses as described in the following table.
Page 75: Core Privilege Levels
Chapter 3 Core overview 3.1.4 Core privilege levels The ARM documentation uses different terms than this document to distinguish between privilege levels. If you see this term... it also means this term... Privileged Supervisor Unprivileged or user User 3.2 Nested Vectored Interrupt Controller (NVIC) Configuration This section summarizes how the module has been configured in the chip.
Page 76: Interrupt Vector Assignments
Nested Vectored Interrupt Controller (NVIC) Configuration 3.2.3 Interrupt vector assignments Table 3-4. Interrupt vector assignments Address Vector Source description Source module ARM Core System Handler Vectors 0x0000_0000 — Initial Stack Pointer ARM core 0x0000_0004 — Initial Program Counter ARM core 0x0000_0008 —...
Page 77 Chapter 3 Core overview Table 3-4. Interrupt vector assignments (continued) Address Vector Source description Source module 0x0000_0080 DMA error interrupt channels 0-1531 0x0000_0084 MCM interrupt Off-platform Vectors 0x0000_0088 Command complete Flash memory 0x0000_008C Read collision Flash memory 0x0000_0090 Low-voltage detect, low-voltage warning Mode Controller 0x0000_0094 Low Leakage Wakeup...
Page 78 Nested Vectored Interrupt Controller (NVIC) Configuration Table 3-4. Interrupt vector assignments (continued) Address Vector Source description Source module 0x0000_0114 — 0x0000_0118 XBARA XBARA 0x0000_011C PDB1 PDB1 0x0000_0120 DAC0 DAC0 0x0000_0124 0x0000_0128 LPTMR Low Power Timer 0x0000_012C Pin detect (Port A) Port A control module 0x0000_0130 Pin detect (Port B)
Page 79: Asynchronous Wake-Up Interrupt Controller (Awic) Configuration
Chapter 3 Core overview Table 3-4. Interrupt vector assignments (continued) Address Vector Source description Source module 0x0000_01B0 CMP3 CMP3 0x0000_01B4 — 0x0000_01B8 FLexCAN1 OR'ed Message buffer (0-15) CAN1 0x0000_01BC FLexCAN1 Bus Off CAN1 0x0000_01C0 FLexCAN1 Error CAN1 0x0000_01C4 FLexCAN1 Transmit Warning CAN1 0x0000_01C8 FLexCAN1 Receive Warning...
Page 80: Wake-Up Sources
FPU Configuration 3.3.1 Wake-up sources The device uses the following internal and external inputs to the AWIC module. Table 3-6. AWIC Stop and VLPS Wake-up Sources Wake-up source Description Available system resets RESET pin and WDOG when LPO is its clock source, and JTAG Low-voltage detect Mode Controller Low-voltage warning...
Page 81: Jtag Controller Configuration
Chapter 3 Core overview 3.5 JTAG Controller Configuration This section summarizes how the module has been configured in the chip. Signal JTAG controller cJTAG multiplexing Figure 3-5. JTAGC Controller configuration Table 3-8. Reference links to related information Topic Related module Reference Full description JTAGC...
Page 82 JTAG Controller Configuration KV4x Reference Manual, Rev. 2, 02/2015 Preliminary Freescale Semiconductor, Inc.
Page 83: Chapter 4 Memories And Memory Interfaces
Chapter 4 Memories and Memory Interfaces 4.1 Flash memory types This chip contains a non-volatile program flash memory that can execute program code. 4.2 Flash Memory Sizes The amounts of flash memory for the devices covered in this document are: NOTE The 48-pin LQFP package for this product is not yet available.
Page 84: Flash Security
Flash Security Table 4-1. KV4x flash memory size (continued) Device Flash (KB) Block 0 (flash) address range MKV43F128VLH15 MKV43F128VLF15 MKV41F128VLF15 MKV40F128VLL15 MKV40F128VLH15 MKV40F128VLF15 MKV44F64VLH15 0000_0000 - 0000_FFFF MKV44F64VLF15 MKV43F64VLH15 MKV43F64VLF15 MKV41F64VLF15 MKV40F64VLH15 MKV40F64VLF15 1. Package Your Way 4.3 Flash Security How flash security is implemented on this device is described in Chip Security.
Page 85: Ftfa_Fopt Register
Chapter 4 Memories and Memory Interfaces 4.6 FTFA_FOPT Register The flash memory's FTFA_FOPT register allows the user to customize the operation of the MCU at boot time. See FOPT boot options for details of its definition. 4.7 SRAM sizes The amount of SRAM for the devices covered in this document is shown in the following table.
Page 86 SRAM Arrays Table 4-2. SRAM size (continued) Freescale part number SRAM (KB) MKV40F128VLL15 MKV40F128VLH15 MKV40F128VLF15 MKV40F64VLH15 MKV40F64VLF15 1. Package Your Way 4.8 SRAM Arrays The on-chip SRAM is split into two equally-sized logical arrays, SRAM_L and SRAM_U. The on-chip RAM is implemented such that the SRAM_L and SRAM_U ranges form a contiguous block in the memory map.
Page 87: Sram Retention In Low Power Modes
Chapter 4 Memories and Memory Interfaces SRAM size (KB) SRAM_L range SRAM_U range 1FFF_C000 – 1FFF_FFFF (16K) 2000_0000 – 2000_3FFF (16K) 1FFF_E000 – 1FFF_FFFF (8K) 2000_0000 – 2000_3FFF (16K) 1FFF_E000 – 1FFF_FFFF (8K) 2000_0000 – 2000_1FFF (8K) 4.9 SRAM retention in low power modes The SRAM is retained down to VLLS3 mode.
Page 88 System Register file KV4x Reference Manual, Rev. 2, 02/2015 Preliminary Freescale Semiconductor, Inc.
Page 89: Chapter 5 Memory Map
Chapter 5 Memory Map 5.1 Introduction This chip contains both Flash and RAM memories and memory-mapped peripherals which are located in one contiguous memory space. The ARM M4 core supports both register access of the various peripherals and also bit-band accesses. Following are the memory sizes present.
Page 90: Peripheral Memory Map
Peripheral Memory Map The bitbanding functionality supported by the processor core uses aliased regions that map to the basic RAM and peripheral address spaces. This functionality maps each 32-bit word of the aliased address space to a unique bit in the underlying RAM or peripheral address space to support single-bit insert and extract operations from the processor.
Page 91: Read-After-Write Sequence And Required Serialization Of Memory Operations
Chapter 5 Memory Map 5.3.1 Read-after-write sequence and required serialization of memory operations In some situations, a write to a peripheral must be completed fully before a subsequent action can occur. Examples of such situations include: • Exiting an interrupt service routine (ISR) •...
Page 92 Peripheral Memory Map Table 5-2. Peripheral bridge 0 slot assignments (continued) System 32-bit base address Slot Module number 0x4001_0000 — 0x4001_1000 — 0x4001_2000 — 0x4001_3000 — 0x4001_4000 — 0x4001_5000 — 0x4001_6000 — 0x4001_7000 — 0x4001_8000 — 0x4001_9000 — 0x4001_A000 — 0x4001_B000 —...
Page 93 Chapter 5 Memory Map Table 5-2. Peripheral bridge 0 slot assignments (continued) System 32-bit base address Slot Module number 0x4003_6000 PDB0 0x4003_7000 PIT (periodic interrupt timer) 0x4003_8000 FTM0 (8 channel FlexTimer) 0x4003_9000 FTM1 (2 channel FlexTimer) 0x4003_A000 0x4003_B000 0x4003_C000 0x4003_D000 0x4003_E000 0x4003_F000 DAC0...
Page 94 Peripheral Memory Map Table 5-2. Peripheral bridge 0 slot assignments (continued) System 32-bit base address Slot Module number 0x4005_D000 0x4005_E000 0x4005_F000 0x4006_0000 0x4006_1000 External Watchdog Monitor (EWM) 0x4006_2000 0x4006_3000 0x4006_4000 0x4006_5000 OSC0 0x4006_6000 0x4006_7000 0x4006_8000 0x4006_9000 0x4006_A000 UART0 0x4006_B000 UART1 0x4006_C000 0x4006_D000 0x4006_E000...
Page 95: Chapter 6 Clock Distribution
Chapter 6 Clock Distribution 6.1 Introduction The KV4x family is based on the Kinetis ARM M4 based platform and utilises the MCG (Multiple Clock Generator) module that provides the clocks for the CPU, memories and peripherals. The MCG has input clocks from the OSC module, providing an external feed from a ceramic resonator/crystal/external clock, and internal RC oscillators.
Page 96: Clock Definitions
High-level device clocking diagram Muliplexers MCG_Cx MCG_Cx SIM_SOPT1, SIM_SOPT2 Dividers — MCG_Cx SIM_CLKDIVx Clock gates OSC_CR MCG_C1 SIM_SCGCx 4 MHz IRC FCRDIV Clock options for MCGIRCLK some peripherals 32 kHz IRC MCGFFCLK (see note) system (CPU) clock OUTDIV1 MCGOUTCLK fast peripheral clock OUTDIV2 FRDIV MCGFLLCLK...
Page 97: Internal Clocking Requirements
Chapter 6 Clock Distribution Clock name Description Fast Peripheral clock MCGOUTCLK divided by OUTDIV2 clocks the UARTs, SPI, eFlexPWM, FTMs, PDBs, ENC, FlexCAN, XBARA, and ADC modules. Bus /Flash clock MCGOUTCLK divided by OUTDIV4 clocks Flash, I2C, WDOG, EWM, PIT, LPTIMER , OSC, MCG, PMC , XBARB/ AOI, CMP.
Page 98: Clock Divider Values After Reset
Internal clocking requirements NOTE To enable nanoedge module for nanosecond resolution, PLL must be enabled to provide high frequencies clock source, MCGPLLCLK and MCGPLL2XCLK. When nanoedge enable, system clock source(core and system clock, fast bus clock, slow bus and flash clock must be from/divided from MCGPLLCLK.
Page 99: Vlpr Mode Clocking
Chapter 6 Clock Distribution FTFA_FOPT System clock Fast Peripheral Bus / Flash clock Description [LPBOOT] clock 0x7 (divide by 8) 0x7 (divide by 8) 0xF (divide by 16) Low power boot 0x0 (divide by 1) 0x0 (divide by 1) 0x1 (divide by 2) Fast clock boot This gives the user flexibility for a lower frequency, low-power boot option.
Page 100: Module Clocks
Module clocks Any bus access to a peripheral that has its clock disabled generates an error termination. 6.5 Module clocks The following table summarizes the clocks associated with each module. Table 6-1. Module clocks Module Bus interface clock Internal clocks I/O interface clocks Core modules ARM Cortex-M4 core...
Page 101: Wdog Clocking
Chapter 6 Clock Distribution Table 6-1. Module clocks (continued) Module Bus interface clock Internal clocks I/O interface clocks Fast Peripheral clock MCGIRCLK — Bus / Flash clock — — Fast Peripheral clock — — Timers Fast Peripheral clock — — FlexTimers Fast Peripheral clock MCGFFCLK...
Page 102: Debug Trace Clock
Module clocks WDOG clock Bus / Flash clock WDOG_STCTRLH[CLKSRC] Figure 6-3. WDOG clock generation 6.5.3 Debug trace clock The debug trace clock source can be clocked as shown in the following figure. 6.5.4 PMC 1-kHz LPO clock The Power Management Controller (PMC) generates a 1-kHz clock that is enabled in all modes of operation, including all low power modes.
Page 103: Lptmr Clocking
Chapter 6 Clock Distribution Bus clock PORTx digital input filter clock PORTx_DFCR[CS] Figure 6-4. PORTx digital input filter clock generation 6.5.6 LPTMR clocking The prescaler and glitch filters in each of the LPTMRx modules can be clocked as shown in the following figure. NOTE The chosen clock must remain enabled if the LPTMRx is to continue operating in all required low-power modes.
Page 104: Uart Clocking
External clocks OSCERCLK FlexCAN clock Fast Peripheral clock CANx_CTRL1[CLKSRC] Figure 6-6. FlexCAN clock generation 6.5.8 UART clocking UART0 and UART1 modules operate from the fast peripheral clock, which provides higher performance level for these modules. 6.6 External clocks The input clocks to the SoC are described in detail in the MCG chapter. •...
Page 105: Chapter 7 Power Management
Chapter 7 Power Management 7.1 Introduction This chapter describes the various chip power modes and functionality of the individual modules in these modes. 7.2 Clocking Modes This section describes the various clocking modes supported on this device. 7.2.1 Partial Stop Partial Stop is a clocking option that can be taken instead of entering Stop mode and is configured in the SMC Stop Control Register (SMC_STOPCTRL).
Page 106: Dma Wakeup
Clocking Modes When configured for PSTOP1, both the system clock and the bus clock are gated. All bus masters and bus slaves enter Stop mode, but the clock generators in the MCG and the on- chip regulator in the PMC remain in Run (or VLP Run) mode. Exit from PSTOP1 can be initiated by a reset or an asynchronous interrupt from a bus master or bus slave.
Page 107: Compute Operation
Chapter 7 Power Management NOTE If the requested DMA transfer cannot cause the DMA request to negate, then the device remains in a higher power state until the low power mode is fully exited. If the DMA request asserts during the Stop mode entry sequence (or reentry if the request asserts during a DMA wakeup), then an enabled DMA wakeup can cause an aborted entry into the low power mode, as well as cause the SMC to assert its Stop Abort flag.
Page 108: Peripheral Doze
Clocking Modes GPIO registers via the IOPORT is supported, the GPIO port data input registers do not return valid data since clocks are disabled to the Port Control and Interrupt modules. By writing to the GPIO port data output registers, it is possible to control those GPIO ports that are configured as output pins.
Page 109: Power Modes
Chapter 7 Power Management the bus masters to acknowledge the entry as part of the stop entry sequence. Finally, it can be used to disable selected bus masters or slaves that should remain inactive during a DMA wakeup. If the Flash is not being accessed during WAIT and PSTOP modes, then the Flash Doze mode can be used to reduce power consumption, at the expense of a slightly longer wakeup when executing code and vectors from Flash.
Page 110: Module Operation In Low Power Modes
Module Operation in Low Power Modes Table 7-1. Chip power modes (continued) Chip mode Description Core mode Normal recovery method VLPR (Very Low On-chip voltage regulator is in a low power mode that supplies only Power Run) enough power to run the chip at a reduced frequency. Reduced frequency Flash access mode (1 MHz);...
Page 111 Chapter 7 Power Management • FF = Full functionality. In VLPR and VLPW the system frequency is limited, but if a module does not have a limitation in its functionality, it is still listed as FF. • static = Module register states and associated memories are retained. •...
Page 112 Module Operation in Low Power Modes Table 7-2. Module operation in low power modes (continued) Modules Stop VLPR VLPW VLPS VLLSx All of SRAM_L low power low power low power low power low power in VLLS3; otherwise Register files powered powered powered powered...
Page 113: Power Modes Shutdown Sequencing
Chapter 7 Power Management 7.5 Power modes shutdown sequencing When entering stop or other low-power modes, the clocks are shut off in an orderly sequence to safely place the chip in the targeted low-power state. All low-power entry sequences are initiated by the core executing an WFI instruction. The ARM core's outputs, SLEEPDEEP and SLEEPING, trigger entry to the various low-power modes: •...
Page 114: Flash Program Restrictions
Flash Program Restrictions 7.7 Flash Program Restrictions The flash memory on this device should not be programmed or erased while operating in High Speed Run or VLPR power modes. KV4x Reference Manual, Rev. 2, 02/2015 Preliminary Freescale Semiconductor, Inc.
Page 115: Chapter 8 Security
Chapter 8 Security 8.1 Introduction This device implements security based on the mode selected from the flash module. The following sections provide an overview of flash security and details the effects of security on non-flash modules. 8.2 Flash Security The flash module provides security information to the MCU based on the state held by the FSEC[SEC] bits.
Page 116: Security Interactions With Other Modules
Security Interactions with other Modules 8.3 Security Interactions with other Modules The flash security settings are used by the SoC to determine what resources are available. The following sections describe the interactions between modules and the flash security settings or the impact that the flash security has on non-flash modules. 8.3.1 Security Interactions with Debug When flash security is active the JTAG port cannot access the memory resources of the MCU.
Page 117: Chapter 9 Debug
Chapter 9 Debug 9.1 Introduction This device's debug is based on the ARM coresight architecture and is configured in each device to provide the maximum flexibility as allowed by the restrictions of the pinout and other available resources. Four debug interfaces are supported: •...
Page 118 Introduction Cortex-M4 INTNMI Interrupts Sleep INTISR[239:0] NVIC Core SLEEPING Debug Trigger SLEEPDEEP Instr. Data Trace port (serial wire or multi-pin) TPIU AWIC Private Peripheral Bus (internal) Table I-code bus Code bus D-code bus Matrix System bus SWJ-DP AHB-AP JTAG MDM-AP Figure 9-1.
Page 119: The Debug Port
Chapter 9 Debug Table 9-1. Debug Components Description (continued) Module Description FPB (Flash Patch and Breakpoints) The FPB implements hardware breakpoints and patches code and data from code space to system space. The FPB unit contains two literal comparators for matching against literal loads from Code space, and remapping to a corresponding area in System space.
Page 120: Debug Port Pin Descriptions
Debug Port Pin Descriptions 9.3 Debug Port Pin Descriptions The debug port pins default after POR to their JTAG functionality with the exception of JTAG_TRST_b and can be later reassigned to their alternate functionalities. In cJTAG and SWD modes JTAG_TDI and JTAG_TRST_b can be configured to alternate GPIO functions.
Page 121 Chapter 9 Debug Table 9-3. MDM-AP Register Summary (continued) 0x0100_0000 Status MDM-AP Status Register 0x0100_0004 Control MDM-AP Control Register 0x0100_00FC Read-only identification register that always reads as 0x001C_0000 DPACC APACC Data[31:0] A[3:2] RnW Data[31:0] A[3:2] RnW SWJ-DP See the ARM Debug Interface v5p1 Supplement. Generic Debug Port (DP)
Page 122: Mdm-Ap Control Register
JTAG status and control registers 9.4.1 MDM-AP Control Register Table 9-4. MDM-AP Control register assignments Name Secure Description Flash Mass Erase in Progress Set to cause mass erase. Cleared by hardware after mass erase operation completes. When mass erase is disabled (via MEEN and SEC settings), the erase request does not occur and the Flash Mass Erase in Progress bit continues to assert until the next system reset.
Page 123: Mdm-Ap Status Register
Chapter 9 Debug 9.4.2 MDM-AP Status Register Table 9-5. MDM-AP Status register assignments Name Description Flash Mass Erase Acknowledge The Flash Mass Erase Acknowledge bit is cleared after any system reset. The bit is also cleared at launch of a mass erase command due to write of Flash Mass Erase in Progress bit in MDM AP Control Register.
Page 124: Debug Resets
Debug Resets Table 9-5. MDM-AP Status register assignments (continued) Name Description This bit is set during the VLLSx recovery sequence. The VLLSx Mode Exit bit is held until the debugger has had a chance to recognize that a VLLS mode was exited and is cleared by a write of 1 to the LLS, VLLSx Status Acknowledge bit in MDM AP Control register.
Page 125 Chapter 9 Debug transactions. SWJ/SW-DP-initiated transaction aborts drive an AHB-AP-supported sideband signal called HABORT. This signal is driven into the Bus Matrix, which resets the Bus Matrix state, so that AHB-AP can access the Private Peripheral Bus for last ditch debugging such as read/stop/reset the core.
Page 126: Debug In Low Power Modes
9.9 DWT The DWT is a unit that performs the following debug functionality: • It contains four comparators that you can configure as a hardware watchpoint, a PC sampler event trigger, or a data address sampler event trigger. The first comparator, DWT_COMP0, can also compare against the clock cycle counter, CYCCNT.
Page 127: Debug Module State In Low Power Modes
Chapter 9 Debug With debug enabled, transitions from Run directly to VLPS are not allowed and result in the system entering Stop mode instead. Status bits within the MDM-AP Status register can be evaluated to determine this pseudo-VLPS state. Note with the debug enabled, transitions from Run-->...
Page 128 Debug & Security KV4x Reference Manual, Rev. 2, 02/2015 Preliminary Freescale Semiconductor, Inc.
Page 129: Chapter 10 Reset And Boot
Chapter 10 Reset and Boot 10.1 Introduction The following reset sources are supported in this MCU: Table 10-1. Reset sources Reset sources Description POR reset • Power-on reset (POR) System resets • External pin reset (PIN) • Low-voltage detect (LVD) •...
Page 130: Power-On Reset (Por)
Reset 10.2.1 Power-on reset (POR) When power is initially applied to the MCU or when the supply voltage drops below the power-on reset re-arm voltage level (V ), the POR circuit causes a POR reset condition. As the supply voltage rises, the LVD circuit holds the MCU in reset until the supply has risen above the LVD low threshold (V ).
Page 131: External Pin Reset (Pin)
Chapter 10 Reset and Boot 10.2.2.1 External pin reset (PIN) On this device, RESET is a dedicated pin. This pin is open drain and has an internal pullup device. Asserting RESET wakes the device from any mode. During a pin reset, the SRSL[PIN] bit is set.
Page 132 Reset The LVD can be configured to generate a reset upon detection of a low voltage condition by setting LVDSC1[LVDRE]. After an LVD reset has occurred, the LVD system holds the MCU in reset until the supply voltage rises above the low voltage detection threshold. The SRSL[LVD] bit is set following an LVD reset or POR.
Page 133: Software Reset (Sw)
Chapter 10 Reset and Boot The MC_SRSL[LOC] bit is set to indicate the error. 10.2.2.6 Software reset (SW) The SYSRESETREQ bit in the NVIC application interrupt and reset control register can be set to force a software reset on the device. (See ARM's NVIC documentation for the full description of the register fields, especially the VECTKEY field requirements.) Setting SYSRESETREQ generates a software reset request.
Page 134: Jtag Reset
Reset 10.2.3.1 JTAG reset The JTAG module generate a system reset when certain IR codes are selected. This functional reset is asserted when EXTEST, HIGHZ and CLAMP instructions are active. The reset source from the JTAG module is released when any other IR code is selected. A JTAG reset causes the SRSH[JTAG] bit to set.
Page 135: Boot Sources
Chapter 10 Reset and Boot • AHB-AP • Private peripheral bus 10.3 Boot This section describes the boot sequence, including sources and options. 10.3.1 Boot sources This device only supports booting from internal flash. Any secondary boot must go through an initialization sequence in flash. 10.3.2 FOPT boot options The flash option register (FOPT) in the flash memory module allows the user to customize the operation of the MCU at boot time.
Page 136: Boot Sequence
Boot Table 10-2. Flash Option Register Bit Definitions (continued) Field Value Definition Reserved Reserved for future expansion. LPBOOT Control the reset value of OUTDIVx values in SIM_CLKDIV1 register. Larger divide value selections produce lower average power consumption during POR, VLLSx recoveries and reset sequencing and after reset exit.
Page 137 Chapter 10 Reset and Boot 7. When the system exits reset, the processor sets up the stack, program counter (PC), and link register (LR). The processor reads the start SP (SP_main) from vector-table offset 0. The core reads the start PC from vector-table offset 4. LR is set to 0xFFFF_FFFF.
Page 138 Boot KV4x Reference Manual, Rev. 2, 02/2015 Preliminary Freescale Semiconductor, Inc.
Page 139: Chapter 11 Signal Multiplexing
Chapter 11 Signal Multiplexing 11.1 Introduction To optimize functionality in small packages, pins have several functions available via signal multiplexing. This chapter illustrates which of this device's signals are multiplexed on which external pin. Port Control block controls which signal is present on the external pin. Reference that chapter to find which register controls the operation of a specific pin.
Page 140 Clock gating Table 11-1. Ports summary (continued) Feature Port A Port B Port C Port D Port E Slew rate enable control Slew rate enable at Disabled Disabled Disabled Disabled Disabled reset Passive filter PTA4=Yes; enable control Others=No Passive filter Disabled Disabled Disabled...
Page 141: Signal Multiplexing Constraints
Chapter 11 Signal Multiplexing 11.4 Signal multiplexing constraints 1. A given peripheral function must be assigned to a maximum of one package pin. Do not program the same function to more than one pin. 2. To ensure the best signal timing for a given peripheral's interface, choose the pins in closest proximity to each other.
Page 142 KV4x Signal Multiplexing and Pin Assignments Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 LQFP LQFP LQFP — — PTE2/ ADCB_CH6g ADCB_CH6g PTE2/ UART1_CTS_ LLWU_P1 LLWU_P1 — — PTE3 ADCB_CH7g ADCB_CH7g PTE3 UART1_RTS_ — — PTE4/ DISABLED PTE4/ LLWU_P2 LLWU_P2...
Page 143 Chapter 11 Signal Multiplexing Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 LQFP LQFP LQFP PTA0 JTAG_TCLK/ PTA0 UART0_CTS_ FTM0_CH5 XBAR0_IN4 EWM_IN JTAG_TCLK/ SWD_CLK SWD_CLK UART0_COL_ PTA1 JTAG_TDI PTA1 UART0_RX FTM0_CH6 CMP0_OUT FTM1_CH1 JTAG_TDI PTA2 JTAG_TDO/ PTA2 UART0_TX FTM0_CH7 CMP1_OUT...
Page 144 KV4x Signal Multiplexing and Pin Assignments Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 LQFP LQFP LQFP — — PTB16 DISABLED PTB16 UART0_RX FTM_CLKIN2 CAN0_TX EWM_IN XBAR0_IN5 PTB17 DISABLED PTB17 UART0_TX FTM_CLKIN1 CAN0_RX EWM_OUT_b — PTB18 DISABLED PTB18 CAN0_TX FTM3_CH2...
Page 145 Chapter 11 Signal Multiplexing Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 LQFP LQFP LQFP PTC6/ CMP2_IN4/ CMP2_IN4/ PTC6/ SPI0_SOUT PDB0_EXTRG XBAR0_IN3 UART0_RX XBAR0_OUT6 I2C0_SCL LLWU_P10 CMP0_IN0 CMP0_IN0 LLWU_P10 PTC6/ CMP2_IN4/ CMP2_IN4/ PTC6/ SPI0_SOUT PDB0_EXTRG XBAR0_IN3 UART0_RX XBAR0_OUT6 I2C0_SCL LLWU_P10 CMP0_IN0...
Page 146: Pinout Diagrams
Pinout diagrams Pin Name Default ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7 LQFP LQFP LQFP PTC18 DISABLED PTC18 UART3_RTS_ ENET0_1588_ FLEXPWMB_ TMR2 PTD0/ DISABLED PTD0/ SPI0_PCS0 FTM3_CH0 FTM0_CH0 FLEXPWMA_ LLWU_P12 LLWU_P12 PTD0/ DISABLED PTD0/ SPI0_PCS0 UART2_RTS_ FTM3_CH0 FTM0_CH0 FLEXPWMA_ LLWU_P12 LLWU_P12 PTD1...
Page 147 Chapter 11 Signal Multiplexing PTE0/CLKOUT32K VDD VDD PTE1/LLWU_P0 VSS VSS PTE2/LLWU_P1 PTC3/LLWU_P7 PTC3/LLWU_P7 PTE3 PTC2 PTC2 PTE4/LLWU_P2 PTC1/LLWU_P6 PTC1/LLWU_P6 PTE5 PTC0 PTC0 PTE6/LLWU_P16 PTB23 PTB23 PTB22 PTB22 PTB21 PTB21 PTE16 PTB20 PTB19 PTE17/LLWU_P19 PTB18 PTE18/LLWU_P20 PTB17 PTE19 PTB16 ADCA_CH6a ADCA_CH7a PTE20 PTB11 PTE21...
Page 148 Pinout diagrams PTE0/CLKOUT32K PTE1/LLWU_P0 PTC3/LLWU_P7 PTC2 PTE16 PTC1/LLWU_P6 PTE17/LLWU_P19 PTC0 PTE18/LLWU_P20 PTB19 PTE19 PTB18 ADCA_CH2 PTB17 ADCA_CH3 PTB16 ADCA_CH6c PTB3 ADCA_CH7c PTB2 VDDA PTB1 VREFH PTB0/LLWU_P5 VREFL RESET_b VSSA PTA19 Figure 11-2. 64-pin LQFP KV4x Reference Manual, Rev. 2, 02/2015 Preliminary Freescale Semiconductor, Inc.
Page 149 Chapter 11 Signal Multiplexing PTC3/LLWU_P7 ADCB_CH6c /CMP1_IN0 ADCB_CH7b ADCA_CH0 ADCB_CH6b ADCA_CH1 ADCB_CH0 PTB17 ADCB_CH1 PTB16 ADCB_CH7e / CMP3_IN5 ADCA_CH6b ADCA_CH7b ADCA_CH6e / CMP2_IN2 VDDA ADCB_CH3 VREFH ADCB_CH2 VREFL RESET_b VSSA PTA19 Figure 11-3. 48-pin LQFP KV4x Reference Manual, Rev. 2, 02/2015 Preliminary Freescale Semiconductor, Inc.
Page 150 Pinout diagrams KV4x Reference Manual, Rev. 2, 02/2015 Preliminary Freescale Semiconductor, Inc.
Page 151: Chapter 12 Port Control And Interrupts (Port)
Chapter 12 Port control and interrupts (PORT) 12.1 Introduction 12.2 Overview The Port Control and Interrupt (PORT) module provides support for port control, digital filtering, and external interrupt functions. Most functions can be configured independently for each pin in the 32-bit port and affect the pin regardless of its pin muxing state.
Page 152: Modes Of Operation
Overview • Selectable clock source for digital input filter with a five bit resolution on filter size • Functional in all digital pin multiplexing modes • Port control • Individual pull control fields with pullup, pulldown, and pull-disable support • Individual drive strength field supporting high and low drive strength •...
Page 153: Debug Mode
Chapter 12 Port control and interrupts (PORT) 12.2.2.4 Debug mode In Debug mode, PORT operates normally. 12.3 External signal description The table found here describes the PORT external signal. Table 12-1. Signal properties Name Function Reset Pull PORTx[31:0] External interrupt NOTE Not all pins within each port are implemented on each device.
Page 154 Memory map and register definition PORT memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4004_9000 Pin Control Register n (PORTA_PCR0) See section 12.5.1/160 4004_9004 Pin Control Register n (PORTA_PCR1) See section 12.5.1/160 4004_9008 Pin Control Register n (PORTA_PCR2) See section 12.5.1/160...
Page 155 Chapter 12 Port control and interrupts (PORT) PORT memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4004_90C0 Digital Filter Enable Register (PORTA_DFER) 0000_0000h 12.5.5/164 4004_90C4 Digital Filter Clock Register (PORTA_DFCR) 0000_0000h 12.5.6/165 4004_90C8 Digital Filter Width Register (PORTA_DFWR) 0000_0000h 12.5.7/165...
Page 156 Memory map and register definition PORT memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4004_A084 Global Pin Control High Register (PORTB_GPCHR) (always 0000_0000h 12.5.3/163 reads 0) 4004_A0A0 Interrupt Status Flag Register (PORTB_ISFR) 0000_0000h 12.5.4/164 4004_A0C0 Digital Filter Enable Register (PORTB_DFER)
Page 157 Chapter 12 Port control and interrupts (PORT) PORT memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4004_B07C Pin Control Register n (PORTC_PCR31) See section 12.5.1/160 4004_B080 Global Pin Control Low Register (PORTC_GPCLR) (always 0000_0000h 12.5.2/163...
Page 158 Memory map and register definition PORT memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4004_C070 Pin Control Register n (PORTD_PCR28) See section 12.5.1/160 4004_C074 Pin Control Register n (PORTD_PCR29) See section 12.5.1/160 4004_C078 Pin Control Register n (PORTD_PCR30) See section 12.5.1/160...
Page 159 Chapter 12 Port control and interrupts (PORT) PORT memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4004_D064 Pin Control Register n (PORTE_PCR25) See section 12.5.1/160 4004_D068 Pin Control Register n (PORTE_PCR26) See section 12.5.1/160 4004_D06C Pin Control Register n (PORTE_PCR27) See section...
Page 160 Memory map and register definition 12.5.1 Pin Control Register n (PORTx_PCRn) NOTE See the Signal Multiplexing and Pin Assignment chapter for the reset value of this device. See the GPIO Configuration section for details on the available functions for each pin. Do not modify pin configuration registers associated with pins not available in your selected package.
Page 161 Chapter 12 Port control and interrupts (PORT) PORTx_PCRn field descriptions (continued) Field Description Configured interrupt is not detected. Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag.
Page 162 Memory map and register definition PORTx_PCRn field descriptions (continued) Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. Drive Strength Enable Drive strength configuration is valid in all digital pin muxing modes. Low drive strength is configured on the corresponding pin, if pin is configured as a digital output.
Page 163 Chapter 12 Port control and interrupts (PORT) 12.5.2 Global Pin Control Low Register (PORTx_GPCLR) Only 32-bit writes are supported to this register. Address: Base address + 80h offset GPWE GPWD Reset PORTx_GPCLR field descriptions Field Description 31–16 Global Pin Write Enable GPWE Selects which Pin Control Registers (15 through 0) bits [15:0] update with the value in GPWD.
Page 164 Memory map and register definition 12.5.4 Interrupt Status Flag Register (PORTx_ISFR) The pin interrupt configuration is valid in all digital pin muxing modes. The Interrupt Status Flag for each pin is also visible in the corresponding Pin Control Register, and each flag can be cleared in either location.
Page 165 Chapter 12 Port control and interrupts (PORT) PORTx_DFER field descriptions (continued) Field Description The digital filter configuration is valid in all digital pin muxing modes. The output of each digital filter is reset to zero at system reset and whenever the digital filter is disabled. Each bit in the field enables the digital filter of the same number as the field.
Page 166: Pin Control
Functional description Address: Base address + C8h offset FILT Reset PORTx_DFWR field descriptions Field Description 31–5 This field is reserved. Reserved This read-only field is reserved and always has the value 0. FILT Filter Length The digital filter configuration is valid in all digital pin muxing modes. Configures the maximum size of the glitches, in clock cycles, that the digital filter absorbs for the enabled digital filters.
Page 167: Global Pin Control
Chapter 12 Port control and interrupts (PORT) When the Pin Muxing mode is configured for analog or is disabled, all the digital functions on that pin are disabled. This includes the pullup and pulldown enables, output buffer enable, input buffer enable, and passive filter enable. A lock field also exists that allows the configuration for each pin to be locked until the next system reset.
Page 168: Digital Filter
Functional description • Interrupt disabled, default out of reset • Active high level sensitive interrupt • Active low level sensitive interrupt • Rising edge sensitive interrupt • Falling edge sensitive interrupt • Rising and falling edge sensitive interrupt • Rising edge sensitive DMA request •...
Page 169 Chapter 12 Port control and interrupts (PORT) The filter width in clock size is the same for all enabled digital filters within one port and must be changed only when all digital filters for that port are disabled. The output of each digital filter is logic zero after system reset and whenever a digital filter is disabled.
Page 170 Functional description KV4x Reference Manual, Rev. 2, 02/2015 Preliminary Freescale Semiconductor, Inc.
Page 171: Chapter 13 System Integration Module (Sim)
Chapter 13 System Integration Module (SIM) 13.1 Introduction The System Integration Module (SIM) provides system control and chip configuration registers. 13.1.1 Features Features of the SIM include: • System clocking configuration • System clock divide values • Architectural clock gating control •...
Page 172: Memory Map And Register Definition
Memory map and register definition 13.2 Memory map and register definition The SIM module contains many fields for selecting the clock source and dividers for various module clocks. See the Clock Distribution chapter for more information, including block diagrams and clock definitions. NOTE The SIM registers can be written only in supervisor mode.
Page 173 Chapter 13 System Integration Module (SIM) SIM memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4004_806C Miscellaneous Control Register (SIM_MISCTRL) 0000_0000h 13.2.21/202 4004_8070 Miscellaneous Control Register 2 (SIM_MISCTRL2) 0000_0000h 13.2.22/203 4004_8100 WDOG Control Register (SIM_WDOGC) 0000_0000h 13.2.23/206 4004_8104...
Page 174 Memory map and register definition SIM_SOPT1 field descriptions (continued) Field Description 17–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 15–12 RAM size RAMSIZE This field specifies the amount of system RAM available on the device. 0001 Reserved 0011...
Page 175 Chapter 13 System Integration Module (SIM) SIM_SOPT2 field descriptions Field Description Nanoedge clock(PWM 2x clock) select NANOEDGECLK2XSEL Selects the PLL 2x clock(MCGPLLCLK2X) or 1x clock (MCGPLLCLK) as the nanoedge clock source. 0 MCGPLLCLK 1 MCGPLLCLK2X 30–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0.
Page 176 Memory map and register definition 13.2.3 System Options Register 4 (SIM_SOPT4) Address: 4004_7000h base + 100Ch offset = 4004_800Ch Reset Reset SIM_SOPT4 field descriptions Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. FlexTimer 3 Hardware Trigger 2 Source Select FTM3TRG2SRC Selects the source of FTM3 hardware trigger 2.
Page 177 Chapter 13 System Integration Module (SIM) SIM_SOPT4 field descriptions (continued) Field Description FTM1_FLT0 pin drives FTM1 hardware trigger 2 XBARA output 35 drives FTM1 hardware trigger 2 This field is reserved. Reserved This read-only field is reserved and always has the value 0. FlexTimer 1 Hardware Trigger 0 Source Select FTM1TRG0SRC Selects the source of FTM1 hardware trigger 0.
Page 178 Memory map and register definition SIM_SOPT4 field descriptions (continued) Field Description NOTE: The pin source for fault 0 must be configured for the FTM module fault function through the appropriate pin control register in the port control module. FTM1_FLT0 pin CMP0 out Selects the source of FTM0 fault 3.
Page 179 Chapter 13 System Integration Module (SIM) 13.2.4 System Options Register 5 (SIM_SOPT5) Address: 4004_7000h base + 1010h offset = 4004_8010h Reset Reset SIM_SOPT5 field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 7–6 UART 1 receive data source select UART1RXSRC...
Page 180 Memory map and register definition SIM_SOPT5 field descriptions (continued) Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. UART 0 transmit data source select UART0TXSRC Selects the source for the UART 0 transmit data. UART0_TX pin UART0_TX pin modulated with FTM1 channel 0 output 13.2.5 System Options Register 7 (SIM_SOPT7)
Page 181 Chapter 13 System Integration Module (SIM) SIM_SOPT7 field descriptions (continued) Field Description 0111 PIT trigger 3 1000 FTM0 trigger 1001 FTM1 trigger 1010 Reserved 1011 FTM3 trigger 1100 XBARA output 41 1101 Reserved 1110 Low-power timer trigger 1111 Reserved 7–6 ADCA alternate trigger enable ADCAALTTRGEN Enable alternative conversion triggers for ADCA.
Page 182 Memory map and register definition 13.2.6 System Options Register 8 (SIM_SOPT8) Address: 4004_7000h base + 101Ch offset = 4004_801Ch Reset Reset SIM_SOPT8 field descriptions Field Description FTM3 channel 7 output source FTM3OCH7SRC FTM3_CH7 pin is output of FTM3 channel 7 output FTM3_CH7 pin is output of FTM3 channel 7 output modulated by carrier frequency clock, as per FTM3CFSEL.
Page 183 Chapter 13 System Integration Module (SIM) SIM_SOPT8 field descriptions (continued) Field Description FTM3_CH2 pin is output of FTM3 channel 2 output FTM3_CH2 pin is output of FTM3 channel 2 output modulated by carrier frequency clock, as per FTM3CFSEL. FTM3 channel 1 output source FTM3OCH1SRC FTM3_CH1 pin is output of FTM3 channel 1 output FTM3_CH1 pin is output of FTM3 channel 1 output modulated by carrier frequency clock, as per...
Page 184 Memory map and register definition SIM_SOPT8 field descriptions (continued) Field Description FTM0_CH0 pin is output of FTM0 channel 0 output FTM0_CH0 pin is output of FTM0 channel 0 output, modulated by carrier frequency clock, as per FTM0CFSEL 15–10 This field is reserved. Reserved This read-only field is reserved and always has the value 0.
Page 185 Chapter 13 System Integration Module (SIM) 13.2.7 System Options Register 9 (SIM_SOPT9) Address: 4004_7000h base + 1020h offset = 4004_8020h Reset Reset SIM_SOPT9 field descriptions Field Description 31–30 FlexTimer 3 External Clock Pin Select FTM3CLKSEL Selects the external pin used to drive the clock to the FTM3 module. NOTE: The selected pin must also be configured for the FTM3 module external clock function through the appropriate pin control register in the port control module.
Page 186 Memory map and register definition SIM_SOPT9 field descriptions (continued) Field Description NOTE: The selected pin must also be configured for the FTM0 module external clock function through the appropriate pin control register in the port control module. FTM0 external clock driven by FTM_CLK0 pin FTM0 external clock driven by FTM_CLK1 pin FTM0 external clock driven by FTM_CLK2 pin Reserved...
Page 187 Chapter 13 System Integration Module (SIM) SIM_SDID field descriptions (continued) Field Description 0100 Kinetis family of this device. This is the Vseries. 27–24 Kinetis Sub-Family ID SUBFAMID Specifies the Kinetis sub-family of the device. 0000 KVx0 Subfamily (FlexTimer & MC_ADC) 0001 KVx1 Subfamily (FlexTimer &...
Page 188 Memory map and register definition SIM_SDID field descriptions (continued) Field Description 1110 Reserved 1111 Reserved 13.2.9 System Clock Gating Control Register 4 (SIM_SCGC4) Address: 4004_7000h base + 1034h offset = 4004_8034h Reset I2C0 Reset SIM_SCGC4 field descriptions Field Description 31–28 This field is reserved.
Page 189 Chapter 13 System Integration Module (SIM) SIM_SCGC4 field descriptions (continued) Field Description eFlexPWM submodule 0 Clock Gate Control eFlexPWM0 This bit controls the clock gate to the PWM submodule 0. Clock disabled Clock enabled 23–20 This field is reserved. Reserved This read-only field is reserved and always has the value 0.
Page 190 Memory map and register definition 13.2.10 System Clock Gating Control Register 5 (SIM_SCGC5) Address: 4004_7000h base + 1038h offset = 4004_8038h Reset Reset SIM_SCGC5 field descriptions Field Description 31–29 This field is reserved. Reserved This read-only field is reserved and always has the value 0. ADC Clock Gate Control This bit controls the clock gate to the ADC module.
Page 191 Chapter 13 System Integration Module (SIM) SIM_SCGC5 field descriptions (continued) Field Description This bit controls the clock gate to the ENC module. Clock disabled Clock enabled 20–19 This field is reserved. Reserved This read-only field is reserved and always has the value 0. This field is reserved.
Page 192 Memory map and register definition SIM_SCGC5 field descriptions (continued) Field Description This bit controls software access to the Low Power Timer module. Access disabled Access enabled 13.2.11 System Clock Gating Control Register 6 (SIM_SCGC6) Address: 4004_7000h base + 103Ch offset = 4004_803Ch PDB0 CRC PDB1 Reset...
Page 193 Chapter 13 System Integration Module (SIM) SIM_SCGC6 field descriptions (continued) Field Description PDB0 Clock Gate Control PDB0 This bit controls the clock gate to the PDB0 module. Clock disabled Clock enabled 21–19 This field is reserved. Reserved This read-only field is reserved and always has the value 0. CRC Clock Gate Control This bit controls the clock gate to the CRC module.
Page 194 Memory map and register definition SIM_SCGC6 field descriptions (continued) Field Description Clock disabled Clock enabled Flash Memory Clock Gate Control This bit controls the clock gate to the flash memory. Flash reads are still supported while the flash memory is clock gated, but entry into low power modes is blocked. Clock disabled Clock enabled 13.2.12 System Clock Gating Control Register 7 (SIM_SCGC7)
Page 195 Chapter 13 System Integration Module (SIM) NOTE The CLKDIV1 register cannot be written to when the device is in VLPR mode. Address: 4004_7000h base + 1044h offset = 4004_8044h OUTDIV1 OUTDIV2 OUTDIV4 0 x* x* x* 0 x* x* x* 0* 0* 0* 0* 0 x* x* x* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* Reset * Notes: •...
Page 196 Memory map and register definition SIM_CLKDIV1 field descriptions (continued) Field Description 1000 Divide-by-9. 1001 Divide-by-10. 1010 Divide-by-11. 1011 Divide-by-12. 1100 Divide-by-13. 1101 Divide-by-14. 1110 Divide-by-15. 1111 Divide-by-16. 23–20 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 19–16 Clock 4 output divider value OUTDIV4...
Page 197 Chapter 13 System Integration Module (SIM) 13.2.14 Flash Configuration Register 1 (SIM_FCFG1) Address: 4004_7000h base + 104Ch offset = 4004_804Ch PFSIZE Reset Reset * Notes: • Reset value loaded during System Reset from Flash IFR. • x = Undefined at reset. SIM_FCFG1 field descriptions Field Description...
Page 198 Memory map and register definition SIM_FCFG1 field descriptions (continued) Field Description 19–16 This field is reserved. Reserved This read-only field is reserved and always has the value 1. 15–12 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 11–8 This field is reserved.
Page 199 Chapter 13 System Integration Module (SIM) SIM_FCFG2 field descriptions Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. 30–24 Max address block 0 MAXADDR0 This field concatenated with 13 trailing zeros indicates the first invalid address of flash block 0 (program flash 0).
Page 200 Memory map and register definition SIM_UIDMH field descriptions Field Description Unique Identification Unique identification for the device. 13.2.18 Unique Identification Register Mid Low (SIM_UIDML) Address: 4004_7000h base + 105Ch offset = 4004_805Ch — x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* Reset * Notes: •...
Page 201 Chapter 13 System Integration Module (SIM) 13.2.20 System Clock Divider Register 4 (SIM_CLKDIV4) Address: 4004_7000h base + 1068h offset = 4004_8068h Reset TRACEDIV Reset SIM_CLKDIV4 field descriptions Field Description 31–29 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Debug Trace Divider Control TRACEDIVEN This bit controls the Debug Trace Divider.
Page 202 Memory map and register definition 13.2.21 Miscellaneous Control Register (SIM_MISCTRL) Address: 4004_7000h base + 106Ch offset = 4004_806Ch Reset Reset SIM_MISCTRL field descriptions Field Description 31–20 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 19–18 DAC0 Hardware Trigger Input Source DACTRIGSRC...
Page 203 Chapter 13 System Integration Module (SIM) SIM_MISCTRL field descriptions (continued) Field Description PDB0 pluse-out channel 2. PDB1 pluse-out channel 2. 11–10 CMP Sample/Window Input 1 Source CMPWIN1SRC XBARA output 17. CMP1 Sample/Window input is driven by both PDB0 and PDB1 pluse-out channel 1. PDB0 pluse-out channel 1.
Page 204 Memory map and register definition SIM_MISCTRL2 field descriptions (continued) Field Description Synchronize XBARA's output for CMP3's Sample/Window Input with flash/slow clock SYNCCMP3SAMPLEWIN This field controls the synchronizer between XBARA's output and CMP3's sample/window input. NOTE: Set this bit if the CMP3's sample/window input isn't from flash/slow peripherials through xbar.
Page 205 Chapter 13 System Integration Module (SIM) SIM_MISCTRL2 field descriptions (continued) Field Description 15–14 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Synchronize XBARB's Input PIT Trigger 1 with fast clock SYNCXBARBPITTRIG1 This field controls the synchronizer between PIT trigger 1 and XBARB's input. NOTE: Set this bit if the XBARB's input PIT trigger 1 is fed into fast peripherials through xbar.
Page 206 Memory map and register definition 13.2.23 WDOG Control Register (SIM_WDOGC) Address: 4004_7000h base + 1100h offset = 4004_8100h Reset Reset SIM_WDOGC field descriptions Field Description 31–2 This field is reserved. Reserved This read-only field is reserved and always has the value 0. WDOG Clock Select WDOGCLKS This write-once bit selects the clock source of the WDOG2008 watchdog.
Page 207 Chapter 13 System Integration Module (SIM) 13.2.24 Power Control Register (SIM_PWRC) NOTE Setting PMC_REGSC[BGBE] before nanoedge regulator is enabled, because the regulator uses 1v reference of PMC. Address: 4004_7000h base + 1104h offset = 4004_8104h Reset SRPDN Reset SIM_PWRC field descriptions Field Description 31–26...
Page 208 Memory map and register definition SIM_PWRC field descriptions (continued) Field Description 23–17 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Nanoedge PMC Status SRPWROK Power supply for nanoedge isn't ready. Power supply for nanoedge is OK. 15–10 This field is reserved.
Page 209 Chapter 13 System Integration Module (SIM) SIM_PWRC field descriptions (continued) Field Description eliminates its power consumption. Analog modules powered by this supply should themselves be powered down before entering this mode. Nanoedge regulator placed in normal mode. Nanoedge regulator placed in powerdown mode. Nanoedge regulator placed in normal mode and SRPDN is write protected until chip reset.
Page 210 Memory map and register definition SIM_ADCOPT field descriptions Field Description 31–26 This field is reserved. Reserved This read-only field is reserved and always has the value 0. ADC Clock Status ADCIRCLK Indicates which clock is fed in ADC. NOTE: Can't access ADC's registers when this bit is "1". This bit is used in STOP/VLPS mode to make sure if the ADC clock is switched to the expected clock.
Page 211: Functional Description
Chapter 13 System Integration Module (SIM) SIM_ADCOPT field descriptions (continued) Field Description ADCA MUX1's channel a. ADCA MUX1's channel b. ADCA MUX1's channel c. Reserved ADCA MUX1's channel e. ADCA MUX1's channel f. ADCA MUX1's channel g. PMC 1V This field is reserved. Reserved This read-only field is reserved and always has the value 0.
Page 212 Functional description KV4x Reference Manual, Rev. 2, 02/2015 Preliminary Freescale Semiconductor, Inc.
Page 213: Chapter 14 Kinetis Flashloader
Chapter 14 Kinetis Flashloader 14.1 Introduction The Kinetis devices that do not have an on-chip ROM are shipped with the pre- programmed Kinetis Flashloader in the on-chip flash memory, for one-time, in-system factory programming. The Kinetis Flashloader’s main task is to load a customer firmware image into the flash memory.
Page 214: Memory Maps
Functional Description • Protection of RAM used by the flashloader while it is running • Provides command to read properties of the device, such as flash and RAM size Table 14-1. Commands supported by the Kinetis Flashloader Command Description When flash security is enabled, then this command is Execute Run user application code that never returns control to...
Page 215: Startup Process
Chapter 14 Kinetis Flashloader Available 0x2000_2E00 Flashloader use 0x1FFF_F000 Figure 14-1. Kinetis Flashloader RAM Memory Map NOTE The Kinetis Flashloader requires a minimum memory space of 16KB of RAM. For Kinetis devices with less than 16 KB of on- chip RAM, the Kinetis Flashloader is not available. 14.2.2 Start-up Process As the Kinetis Flashloader begins executing, flashloader operations begin: 1.
Page 216 Functional Description Shutdown all Jump to user Peripherals application Timeout Check enabled and has Timeout occurred? Enter bootloader Init hardware CAN n entered interrupt state? Load user-config data SPIn entered Configure clocks interrupt state? Init Flash, Property and Memory interfaces I2Cn entered Shutdown unused interrupt state?
Page 217: Clock Configuration
Chapter 14 Kinetis Flashloader 14.2.3 Clock Configuration The Kinetis Flashloader uses the clock configuration of the chip out of reset. 14.2.4 Flashloader Protocol This section explains the general protocol for the packet transfers between the host and the Kinetis Flashloader. The description includes the transfer of packets for different transactions, such as commands with no data phase and commands with incoming or outgoing data phase.
Page 218: Command With Incoming Data Phase
Functional Description Target Host Command Process command Response Figure 14-3. Command with No Data Phase 14.2.4.2 Command with incoming data phase The protocol for a command with an incoming data phase contains: • Command packet (from host) • Generic response command packet (to host) •...
Page 219: Process Data
Chapter 14 Kinetis Flashloader Target Host Command Process command Initial Response Data packet Process data Final data packet Process data Final Response Figure 14-4. Command with incoming data phase NOTE • The host may not send any further packets while it (the host) is waiting for the response to a command.
Page 220: Command With Outgoing Data Phase
Functional Description kStatus_AbortDataPhase. The host may abort the data phase early by sending a zero-length data packet. • The final Generic Response packet sent after the data phase includes the status for the entire operation. 14.2.4.3 Command with outgoing data phase The protocol for a command with an outgoing data phase contains: •...
Page 221 Chapter 14 Kinetis Flashloader Target Host Command Process command Initial Response Data packet Process data Final data packet Process data Final Response Figure 14-5. Command with outgoing data phase NOTE • For the outgoing data phase sequence above, the data phase is really considered part of the response command.
Page 222: Flashloader Packet Types
Functional Description • Data phases may be aborted by the host sending the final Generic Response early with a status of kStatus_AbortDataPhase. The sending side may abort the data phase early by sending a zero-length data packet. • The final Generic Response packet sent after the data phase includes the status for the entire operation.
Page 223: Ping Response Packet
Chapter 14 Kinetis Flashloader Target Host Ping Packet 0x5a 0xa6 Target executes UART autobaud if necessary PingResponse Packet : 0x5a 0xa7 0x00 0x02 0x01 0x50 0x00 0x00 0xaa 0xea Figure 14-6. Ping Packet Protocol Sequence 14.2.5.2 Ping Response Packet The target (Kinetis Flashloader) sends a Ping Response packet back to the host after receiving a Ping packet.
Page 224: Framing Packet
Functional Description 14.2.5.3 Framing Packet The framing packet is used for flow control and error detection, and it (the framing packet) wraps command and data packets as well. Table 14-4. Framing Packet Format Byte # Value Parameter 0x5A start byte packetType length_low Length is a 16-bit field that specifies the entire...
Page 225: Command Packet
Chapter 14 Kinetis Flashloader uint16_t crc16_update(const uint8_t * src, uint32_t lengthInBytes) uint32_t crc = 0; uint32_t j; for (j=0; j < lengthInBytes; ++j) uint32_t i; uint32_t byte = src[j]; crc ^= byte << 8; for (i = 0; i < 8; ++i) uint32_t temp = crc <<...
Page 226 Functional Description Table 14-8. Command Header Format Byte # Command Header Field Command or Response tag The command header is 4 bytes long, with these fields. Flags Reserved. Should be 0x00. ParameterCount The header is followed by 32-bit parameters up to the value of the ParameterCount field specified in the header.
Page 227: Data Packet
Chapter 14 Kinetis Flashloader Table 14-10. Responses that are supported (continued) Response Name 0xA3 ReadMemoryResponse (used for sending responses to ReadMemory command only) Flags: Each command packet contains a Flag byte. Only bit 0 of the flag byte is used. If bit 0 of the flag byte is set to 1, then data packets will follow in the command sequence.
Page 228 Functional Description (with generic response tag = 0xA0) and a list of parameters (defined in the next section). The parameter count field in the header is always set to 2, for status code and command tag parameters. Table 14-11. GenericResponse Parameters Byte # Parameter Descripton...
Page 229: Flashloader Command Api
Chapter 14 Kinetis Flashloader Table 14-13. ReadMemoryResponse Parameters Byte # Parameter Descripton 0 - 3 Status code The status of the associated Read Memory command. 4 - 7 Data byte count The number of bytes sent in the data phase. 14.2.6 Flashloader Command API All Kinetis Flashloader command APIs follow the command packet format that is wrapped by the framing packet, as explained in previous sections.
Page 230 Functional Description Target Host GetProperty: Property tag = 0x01 0x5a a4 08 00 73 d4 07 00 00 01 01 00 00 00 ACK: 0x5a a1 Process command Generic Response: 0x5a a4 0c 00 07 7a a7 00 00 02 00 00 00 00 00 00 01 4 b ACK: 0x5a a1 Figure 14-7.
Page 231: Setproperty Command
Chapter 14 Kinetis Flashloader Table 14-16. GetProperty Response Packet Format (Example) (continued) GetPropertyResponse Parameter Value crc16 0x07 0x7a Command packet responseTag 0xA7 flags 0x00 reserved 0x00 parameterCount 0x02 status 0x00000000 propertyValue 0x0000014b - CurrentVersion 14.2.6.2 SetProperty command The SetProperty command is used to change or alter the values of the properties or options in the Kinetis Flashloader.
Page 232 Functional Description Target Host SetProperty: Property tag = 10, Property Value = 1 0x5a a4 0 c 00 67 8d 0c 00 00 02 0 a 00 00 00 01 00 00 00 ACK : 0x5a a1 Process command GenericResponse: 0x5a a4 00 9 e 10 a0 00 0c 02 00 00 00 00 0c 00 00 00 ACK: 0x5a a1...
Page 233: Flasheraseall Command
Chapter 14 Kinetis Flashloader 14.2.6.3 FlashEraseAll command The FlashEraseAll command performs an erase of the entire flash memory. If any flash regions are protected, then the FlashEraseAll command will fail and return an error status code. Executing the FlashEraseAll command will release flash security if it (flash security) was enabled, by setting the FTFA_FSEC register.
Page 234: Flasheraseregion Command
Functional Description Response: The target (Kinetis Flashloader ) will return a GenericResponse packet with status code either set to kStatus_Success for successful execution of the command, or set to an appropriate error status code. 14.2.6.4 FlashEraseRegion command The FlashEraseRegion command performs an erase of one or more sectors of the flash memory.
Page 235: Fillmemory Command
Chapter 14 Kinetis Flashloader Response: The target (Kinetis Flashloader ) will return a GenericResponse packet with one of following error status codes. Table 14-22. FlashEraseRegion Response Status Codes Status Code kStatus_Success (0x0) kStatus_MemoryRangeInvalid (0x10200) kStatus_FlashAlignmentError (0x101) kStatus_FlashAddressError (0x102) kStatus_FlashAccessError (0x103) kStatus_FlashProtectionViolation (0x104) kStatus_FlashCommandFailure (0x105) 14.2.6.5 FillMemory command...
Page 236 Functional Description • Writing to flash requires the start address to be . • If the VerifyWrites property is set to true, then writes to flash will also perform a flash verify program operation. When writing to RAM, the start address need not be aligned, and the data will not be padded.
Page 237: Writememory Command
Chapter 14 Kinetis Flashloader 14.2.6.6 WriteMemory command The WriteMemory command writes data provided in the data phase to a specified range of bytes in memory (flash or RAM). However, if flash protection is enabled, then writes to protected sectors will fail. Special care must be taken when writing to flash.
Page 238: Process Data
Functional Description Target Host WriteMemory : startAddress = 0x20000400, byteCount = 0x64 0x5a a4 0c 00 06 5a 04 00 00 02 00 04 00 20 64 00 00 00 ACK: 0x5a a1 Process command Generic Response: 0x5a a4 0c 00 27 1f a0 00 ff 02 00 00 00 00 04 00 00 00 ACK: 0x5a a1 Data packet : 0x5a a5 20 00 CRC16 32 bytes data...
Page 239: Read Memory Command
Chapter 14 Kinetis Flashloader Data Phase: The WriteMemory command has a data phase; the host will send data packets until the number of bytes of data specified in the byteCount parameter of the WriteMemory command are received by the target. Response: The target (Kinetis Flashloader ) will return a GenericResponse packet with a status code set to kStatus_Success upon successful execution of the command, or to an appropriate error status code.
Page 240 Functional Description Target Host readMemory : startAddress = 0x20000400, byteCount = 100 0x5a a4 0c 00 1d 23 03 00 00 02 00 04 00 20 64 00 00 00 ACK: 0x5a a1 Process command Generic response for command: 0x5a a4 0c 00 27 f6 a3 01 00 02 00 00 00 00 64 00 00 00 ACK: 0x5a a1 Data packet : 0x5a a5 20 00 CRC 16 32 bytes data...
Page 241: Execute Command
Chapter 14 Kinetis Flashloader Data Phase: The ReadMemory command has a data phase. Since the target (Kinetis Flashloader) works in slave mode, the host need pull data packets until the number of bytes of data specified in the byteCount parameter of ReadMemory command are received by host.
Page 242: Peripherals Supported
Peripherals Supported Target Host Reset 0x5a a4 04 00 6f 46 0b 00 00 00 ACK : 0x5a a1 Process command GenericResponse: 0x5a a4 0c 00 f8 0b a 0 00 04 02 00 00 00 00 0b 00 00 00 ACK: 0x5a a1 Figure 14-14.
Page 243 Chapter 14 Kinetis Flashloader 14.3.1 I2C Peripheral The Kinetis Flashloader supports loading data into flash via the I2C peripheral, where the I2C peripheral serves as the I2C slave. A 7-bit slave address is used during the transfer. The Kinetis Flashloader uses 0x10 as the I2C slave address, and supports 400 kbps as the I2C baud rate.
Page 244: Spi Peripheral
Peripherals Supported Fetch ACK Report an error Read 1 byte 0xA2 Process NAK received? from target Reached 0x5A Read 1 byte 0xA1 maximum received? from target received? retries? Report a timeout error Figure 14-16. Host reads ACK packet from target via I2C Fetch Response Read 1 byte...
Page 245 Chapter 14 Kinetis Flashloader The Kinetis Flashloader supports 400 kbps as the SPI baud rate. The SPI peripheral uses the following bus attributes: • Clock Phase = 1 (Second Edge) • Clock Polarity = 1 (Active Low) Because the SPI peripheral serves as a SPI slave device, each transfer should be started by the host, and each outgoing packet should be fetched by the host.
Page 246: Uart Peripheral
Peripherals Supported Report an error Fetch ACK Send 0x00 to 0xA2 shift out 1 byte Process NAK received? from target Reached maximum retries? Send 0x00 to 0x5A 0xA1 shift out 1 byte received? received? from target Report a Next action timeout error Figure 14-19.
Page 247 Chapter 14 Kinetis Flashloader Autobaud feature: If UARTn is used to connect to the flashloader, then the UARTn_RX pin must be kept high and not left floating during the detection phase in order to comply with the autobaud detection algorithm. After the flashloader detects the ping packet (0x5A 0xA6) on UARTn_RX, the flashloader firmware executes the autobaud sequence.
Page 248 Peripherals Supported Wait Report an error for ACK Wait for 1 byte 0xA2 Process NAK received? from target Reached Wait for 1 byte 0x5A 0xA1 maximum received? from target received? retries? Report a timeout error Figure 14-21. Host reads an ACK from target via UART Wait for ping response Wait for...
Page 249 Chapter 14 Kinetis Flashloader Wait for response Wait for 1 byte from target Wait for payload data from target Reached 0x5A maximum received? retries? Set payload length Payload length to maximum less than supported supported length length? Wait for 1 byte from target Wait for payload Wait for CRC...
Page 250 Peripherals Supported • If there is no error, it means that the transfer speed is correct, and it changes the settings back to normal receiving mode, to see if there is a package for this node. • The host side should also have reasonable time tolerance during the automatic speed detection period.
Page 251: Get/Setproperty Command Properties
Chapter 14 Kinetis Flashloader Wait for response Wait for 1 byte from target Wait for payload data from target Reached 0x5A maximum received? retries? Set payload length Payload length is to maximum less than supported supported length length? Wait for 1 byte from target Wait for payload Wait for CRC...
Page 252: Property Definitions
Get/SetProperty Command Properties Table 14-31. Properties used by Get/SetProperty Commands, sorted by Value (continued) Property Writable Tag Value Size Descripion ReservedRegions List of memory regions reserved by the flashloader. Returned as value pairs (<start-address-of-region>, <end-address-of-region>). • If HasDataPhase flag is not set, then the Response packet parameter count indicates the number of pairs.
Page 253: Kinetis Flashloader Status Error Codes
Chapter 14 Kinetis Flashloader Table 14-33. Peripheral bits: [31:7] Peripheral Reserved Reserved Reserved Reserved CAN Slave SPI Slave I2C Slave UART If the peripheral is available, then the corresponding bit will be set in the property value. All reserved bits must be set to 0. 14.4.1.3 AvailableCommands Property This property value is a bitfield with set bits indicating the commands enabled in the flashloader.
Page 254 Kinetis Flashloader Status Error Codes Table 14-35. Kinetis Flashloader Status Error Codes, sorted by Value (continued) Error Code Value Description kStatus_ReadOnly Requested value cannot be changed because it is read-only. kStatus_OutOfRange Requested value is out of range. kStatus_InvalidArgument The requested command's argument is undefined. kStatus_Timeout A timeout occurred.
Page 255: Chapter 15 Reset Control Module (Rcm)
Chapter 15 Reset Control Module (RCM) 15.1 Introduction Information found here describes the registers of the Reset Control Module (RCM). The RCM implements many of the reset functions for the chip. See the chip's reset chapter for more information. AN4503: Power Management for Kinetis and ColdFire+ MCUs for further details on using the RCM.
Page 256 Reset memory map and register descriptions RCM memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4007_F008 Sticky System Reset Status Register 0 (RCM_SSRS0) 15.2.5/261 4007_F009 Sticky System Reset Status Register 1 (RCM_SSRS1) 15.2.6/262 15.2.1 System Reset Status Register 0 (RCM_SRS0) This register includes read-only status flags to indicate the source of the most recent...
Page 257 Chapter 15 Reset Control Module (RCM) RCM_SRS0 field descriptions (continued) Field Description Indicates a reset has been caused by the watchdog timer timing out. This reset source can be blocked by disabling the watchdog. Reset not caused by watchdog timeout Reset caused by watchdog timeout This field is reserved.
Page 258 Reset memory map and register descriptions • VLLS mode wakeup — 0x00 • Other reset — a bit is set if its corresponding reset source caused the reset Address: 4007_F000h base + 1h offset = 4007_F001h Read SACKERR MDM_AP LOCKUP Write Reset RCM_SRS1 field descriptions...
Page 259 Chapter 15 Reset Control Module (RCM) 15.2.3 Reset Pin Filter Control register (RCM_RPFC) NOTE The reset values of bits 2-0 are for Chip POR only. They are unaffected by other reset types. NOTE The bus clock filter is reset when disabled or when entering stop mode.
Page 260 Reset memory map and register descriptions 15.2.4 Reset Pin Filter Width register (RCM_RPFW) NOTE The reset values of the bits in the RSTFLTSEL field are for Chip POR only. They are unaffected by other reset types. Address: 4007_F000h base + 5h offset = 4007_F005h Read RSTFLTSEL Write...
Page 261 Chapter 15 Reset Control Module (RCM) RCM_RPFW field descriptions (continued) Field Description 11001 Bus clock filter count is 26 11010 Bus clock filter count is 27 11011 Bus clock filter count is 28 11100 Bus clock filter count is 29 11101 Bus clock filter count is 30 11110...
Page 262 Reset memory map and register descriptions RCM_SSRS0 field descriptions (continued) Field Description Reset not caused by watchdog timeout Reset caused by watchdog timeout This field is reserved. Reserved This read-only field is reserved and always has the value 0. Sticky Loss-of-Lock Reset SLOL Indicates a reset has been caused by a loss of lock in the MCG PLL.
Page 263 Chapter 15 Reset Control Module (RCM) RCM_SSRS1 field descriptions Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. This field is reserved. Reserved This read-only field is reserved and always has the value 0. Sticky Stop Mode Acknowledge Error Reset SSACKERR Indicates that after an attempt to enter Stop mode, a reset has been caused by a failure of one or more...
Page 264 Reset memory map and register descriptions KV4x Reference Manual, Rev. 2, 02/2015 Preliminary Freescale Semiconductor, Inc.
Page 265: Chapter 16 System Mode Controller (Smc)
Chapter 16 System Mode Controller (SMC) 16.1 Introduction The System Mode Controller (SMC) is responsible for sequencing the system into and out of all low-power Stop and Run modes. Specifically, it monitors events to trigger transitions between power modes while controlling the power, clocks, and memories of the system to achieve the power consumption and functionality of that mode.
Page 266 Modes of operation ARM CPU mode MCU mode Sleep Wait Deep Sleep Stop Accordingly, the ARM CPU documentation refers to sleep and deep sleep, while the Freescale MCU documentation normally uses wait and stop. In addition, Freescale MCUs also augment Stop, Wait, and Run modes in a number of ways.
Page 267: Memory Map And Register Descriptions
Chapter 16 System Mode Controller (SMC) Table 16-1. Power modes (continued) Mode Description VLLS3 The core clock is gated off. System clocks to other masters and bus clocks are gated off after all stop acknowledge signals from supporting peripherals are valid. The MCU is placed in a low leakage mode by powering down the internal logic.
Page 268 Memory map and register descriptions SMC memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4007_E000 Power Mode Protection register (SMC_PMPROT) 16.3.1/268 4007_E001 Power Mode Control register (SMC_PMCTRL) 16.3.2/269 4007_E002 Stop Control Register (SMC_STOPCTRL) 16.3.3/271 4007_E003 Power Mode Status register (SMC_PMSTAT)
Page 269 Chapter 16 System Mode Controller (SMC) SMC_PMPROT field descriptions (continued) Field Description Allow Very-Low-Power Modes AVLP Provided the appropriate control bits are set up in PMCTRL, this write-once field allows the MCU to enter any very-low-power mode (VLPR, VLPW, and VLPS). VLPR, VLPW, and VLPS are not allowed.
Page 270 Memory map and register descriptions SMC_PMCTRL field descriptions Field Description This field is reserved. Reserved This bit is reserved for future expansion and should always be written zero. 6–5 Run Mode Control RUNM When written, causes entry into the selected run mode. Writes to this field are blocked if the protection level has not been enabled using the PMPROT register.
Page 271 Chapter 16 System Mode Controller (SMC) 16.3.3 Stop Control Register (SMC_STOPCTRL) The STOPCTRL register provides various control bits allowing the user to fine tune power consumption during the stop mode selected by the STOPM field. NOTE This register is reset on Chip POR not VLLS and by reset types that trigger Chip POR not VLLS.
Page 272 Memory map and register descriptions SMC_STOPCTRL field descriptions (continued) Field Description LPO clock is enabled in VLLSx LPO clock is disabled in VLLSx VLLSM VLLS Mode Control This field controls which VLLS sub-mode to enter if STOPM = VLLSx. VLLS0 VLLS1 VLLS2 VLLS3...
Page 273: Functional Description
Chapter 16 System Mode Controller (SMC) SMC_PMSTAT field descriptions (continued) Field Description 0000_1000 Current power mode is VLPW. 0001_0000 Current power mode is VLPS. 0010_0000 Reserved 0100_0000 Current power mode is VLLS. 1000_0000 Current power mode is HSRUN 16.4 Functional description 16.4.1 Power mode transitions The following figure shows the power mode state transitions available on the chip.
Page 274 Functional description Any RESET VLPW HSRUN VLPR WAIT STOP VLPS VLLS Figure 16-5. Power mode state diagram The following table defines triggers for the various state transitions shown in the previous figure. Table 16-7. Power mode transition triggers Transition # From Trigger conditions WAIT...
Page 275 Chapter 16 System Mode Controller (SMC) Table 16-7. Power mode transition triggers (continued) Transition # From Trigger conditions Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core. See note. STOP Interrupt or Reset VLPR The core, system, bus and flash clock frequencies and MCG clocking mode are restricted in this mode.
Page 276: Power Mode Entry/Exit Sequencing
Functional description 3. If PMCTRL[STOPM]=000 and STOPCTRL[PSTOPO]=00, then VLPS mode is entered instead of STOP. If PMCTRL[STOPM]=000 and STOPCTRL[PSTOPO]=01 or 10, then only a Partial Stop mode is entered instead of VLPS 16.4.2 Power mode entry/exit sequencing When entering or exiting low-power modes, the system must conform to an orderly sequence to manage transitions safely.
Page 277: Run Modes
Chapter 16 System Mode Controller (SMC) 16.4.2.3 Aborted stop mode entry If an interrupt or a reset occurs during a stop entry sequence, the SMC can abort the transition early and return to RUN mode without completely entering the stop mode. An aborted entry is possible only if the reset or interrupt occurs before the PMC begins the transition to stop mode regulation.
Page 278: Very-Low Power Run (Vlpr) Mode
Functional description To reduce power in this mode, disable the clocks to unused modules using their corresponding clock gating control bits in the SIM's registers. 16.4.3.2 Very-Low Power Run (VLPR) mode In VLPR mode, the on-chip voltage regulator is put into a stop mode regulation state. In this state, the regulator is designed to supply enough current to the MCU over a reduced frequency.
Page 279: High Speed Run (Hsrun) Mode
Chapter 16 System Mode Controller (SMC) 16.4.3.3 High Speed Run (HSRUN) mode In HSRUN mode, the on-chip voltage regulator remains in a run regulation state, but with a slightly elevated voltage output. In this state, the MCU is able to operate at a faster frequency compared to normal RUN mode.
Page 280: Very-Low-Power Wait (Vlpw) Mode
Functional description 16.4.4.2 Very-Low-Power Wait (VLPW) mode VLPW is entered by the entering the Sleep-Now or Sleep-On-Exit mode while SLEEPDEEP is cleared and the MCU is in VLPR mode. In VLPW, the on-chip voltage regulator remains in its stop regulation state. In this state, the regulator is designed to supply enough current to the MCU over a reduced frequency.
Page 281: Stop Mode
Chapter 16 System Mode Controller (SMC) • Normal Stop (STOP) • Very-Low Power Stop (VLPS) • Very-Low-Leakage Stop (VLLSx) 16.4.5.1 STOP mode STOP mode is entered via the sleep-now or sleep-on-exit with the SLEEPDEEP bit set in the System Control Register in the ARM core. The MCG module can be configured to leave the reference clocks running.
Page 282 Functional description • VLLS3 • VLLS2 • VLLS1 • VLLS0 VLLSx is often used in this document to refer to all of these modes. All VLLSx modes can be entered from normal RUN or VLPR modes. The MCU enters the configured VLLS mode if: •...
Page 283 Chapter 16 System Mode Controller (SMC) When asserted while in RUN, WAIT, VLPR, or VLPW, the mode controller drives a corresponding acknowledge for each signal, that is, both CDBGPWRUPACK and CSYSPWRUPACK. When both requests are asserted, the mode controller handles attempts to enter STOP and VLPS by entering an emulated stop state.
Page 284 Functional description KV4x Reference Manual, Rev. 2, 02/2015 Preliminary Freescale Semiconductor, Inc.
Page 285: Chapter 17 Miscellaneous Control Module (Mcm)
Chapter 17 Miscellaneous Control Module (MCM) 17.1 Introduction The Miscellaneous Control Module (MCM) provides a myriad of miscellaneous control functions. 17.1.1 Features The MCM includes the following features: • Program-visible information on the platform configuration and revision • Floating Point Exception monitor and interrupt control •...
Page 286 Memory map/register descriptions 17.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC) PLASC is a 16-bit read-only register identifying the presence/absence of bus slave connections to the device’s crossbar switch. Address: E008_0000h base + 8h offset = E008_0008h Read Write Reset MCM_PLASC field descriptions Field Description 15–8...
Page 287 Chapter 17 Miscellaneous Control Module (MCM) MCM_PLAMC field descriptions (continued) Field Description A bus master connection to AXBS input port n is absent A bus master connection to AXBS input port n is present 17.2.3 Control Register (MCM_CR) CR defines the arbitration and protection schemes for the two system RAM arrays. Address: E008_0000h base + Ch offset = E008_000Ch SRAMLAP SRAMUAP...
Page 288 Memory map/register descriptions MCM_CR field descriptions (continued) Field Description Round robin Special round robin (favors SRAM backoor accesses over the processor) Fixed priority. Processor has highest, backdoor has lowest Fixed priority. Backdoor has highest, processor has lowest This field is reserved. Reserved This read-only field is reserved and always has the value 0.
Page 289 Chapter 17 Miscellaneous Control Module (MCM) 17.2.4 Interrupt Status Register (MCM_ISR) Address: E008_0000h base + 10h offset = E008_0010h Reserved Reset Reset MCM_ISR field descriptions Field Description FPU input denormal interrupt enable FIDCE Disable interrupt Enable interrupt 30–29 This field is reserved. Reserved This read-only field is reserved and always has the value 0.
Page 290 Memory map/register descriptions MCM_ISR field descriptions (continued) Field Description FPU overflow interrupt enable FOFCE Disable interrupt Enable interrupt FPU divide-by-zero interrupt enable FDZCE Disable interrupt Enable interrupt FPU invalid operation interrupt enable FIOCE Disable interrupt Enable interrupt 23–16 This field is reserved. Reserved FPU input denormal interrupt status FIDC...
Page 291 Chapter 17 Miscellaneous Control Module (MCM) MCM_ISR field descriptions (continued) Field Description FPU invalid operation interrupt status FIOC This read-only bit is a copy of the core’s FPSCR[IOC] bit and signals an illegal operation has been detected in the processor’s FPU. Once set, this bit remains set until software clears the FPSCR[IOC] bit. No interrupt Interrupt occurred Reserved...
Page 292: Functional Description
Functional description MCM_CPO field descriptions Field Description 31–3 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Compute Operation wakeup on interrupt CPOWOI No effect. When set, the CPOREQ is cleared on any interrupt or exception vector fetch. Compute Operation acknowledge CPOACK Compute operation entry has not completed or compute operation exit has completed.
Page 293 Chapter 17 Miscellaneous Control Module (MCM) 17.3.1.2 Normal interrupt The MCM's normal interrupt is generated if any of the following is true: • ISCR[ETBI] is set, when • The ETB counter is enabled, ETBCC[CNTEN] = 1 • The ETB count expires •...
Page 294 Functional description KV4x Reference Manual, Rev. 2, 02/2015 Preliminary Freescale Semiconductor, Inc.
Page 295: Chapter 18 Power Management Controller (Pmc)
Chapter 18 Power Management Controller (PMC) 18.1 Introduction The power management controller (PMC) contains the internal voltage regulator, power on reset (POR), low voltage detect system (LVD), and high voltage detect system (HVD). AN4503: Power Management for Kinetis and ColdFire+ MCUs for further details on using the PMC.
Page 296: Lvd Reset Operation
Low-voltage detect (LVD) system when the supply voltage falls below the selected trip point (VLVD). LVDSC1[LVDF] is cleared by writing 1 to LVDSC1[LVDACK], but only if the internal supply has returned above the trip point; otherwise, LVDSC1[LVDF] remains set. • The Low Voltage Warning Flag (LVWF) in the Low Voltage Status and Control 2 Register (LVDSC2[LVWF]) operates in a level sensitive manner.
Page 297: Memory Map And Register Descriptions
Chapter 18 Power Management Controller (PMC) • Two mid-levels: V and V LVW3 LVW2 • Lowest: V LVW1 18.4 I/O retention When in VLLS modes, the I/O states are held on a wake-up event (with the exception of wake-up by reset event) until the wake-up has been acknowledged via a write to REGSC[ACKISO].
Page 298 Memory map and register descriptions 18.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1) This register contains status and control bits to support the low voltage detect function. This register should be written during the reset initialization program to set the desired controls even if the desired settings are the same as the reset settings.
Page 299 Chapter 18 Power Management Controller (PMC) PMC_LVDSC1 field descriptions (continued) Field Description Low-Voltage Detect Reset Enable LVDRE This write-once bit enables LVDF events to generate a hardware reset. Additional writes are ignored. LVDF does not generate hardware resets Force an MCU reset when LVDF = 1 3–2 This field is reserved.
Page 300 Memory map and register descriptions PMC_LVDSC2 field descriptions Field Description Low-Voltage Warning Flag LVWF This read-only status field indicates a low-voltage warning event. LVWF is set when V transitions Supply below the trip point, or after reset and V is already below V .
Page 301 Chapter 18 Power Management Controller (PMC) Address: 4007_D000h base + 2h offset = 4007_D002h Read ACKISO REGONS Reserved BGEN BGBDS BGBE Write Reset PMC_REGSC field descriptions Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. This field is reserved.
Page 302 Memory map and register descriptions PMC_REGSC field descriptions (continued) Field Description Bandgap buffer not enabled Bandgap buffer enabled KV4x Reference Manual, Rev. 2, 02/2015 Preliminary Freescale Semiconductor, Inc.
Page 303: Chapter 19 Low-Leakage Wakeup Unit (Llwu)
Chapter 19 Low-Leakage Wakeup Unit (LLWU) 19.1 Chip-specific LLWU information This chip uses the following internal peripheral and external pin inputs as wakeup sources to the LLWU module: • LLWU_P0-P16, P19-P21 are external pin inputs. Any digital function multiplexed on the pin can be selected as the wakeup source. See the chip's signal multiplexing table for the digital signal options.
Page 304: Modes Of Operation
Introduction 1. Requires the peripheral and the peripheral interrupt to be enabled. The LLWU's WUME bit enables the internal module flag as a wakeup input. After wakeup, the flags are cleared based on the peripheral clearing mechanism. 19.2 Introduction The LLWU module allows the user to select up to 32 external pins and up to 8 internal modules as interrupt wake-up sources from low-leakage power modes.
Page 305: Block Diagram
Chapter 19 Low-Leakage Wakeup Unit (LLWU) 19.2.2.1 VLLS modes All wakeup and reset events result in VLLS exit via a reset flow. 19.2.2.2 Non-low leakage modes The LLWU is not active in all non-low leakage modes where detection and control logic are in a static state.
Page 306: Memory Map/Register Definition
Memory map/register definition 19.4 Memory map/register definition The LLWU includes the following registers: • Wake-up source enable registers • Enable external pin input sources • Enable internal peripheral interrupt sources • Wake-up flag registers • Indication of wakeup source that caused exit from a low-leakage power mode includes external pin or internal module interrupt •...
Page 307 Chapter 19 Low-Leakage Wakeup Unit (LLWU) LLWU memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4007_C00C LLWU Pin Flag 4 register (LLWU_PF4) 19.4.13/322 4007_C00D LLWU Module Flag 5 register (LLWU_MF5) 19.4.14/324 4007_C00E LLWU Pin Filter 1 register (LLWU_FILT1) 19.4.15/326 4007_C00F LLWU Pin Filter 2 register (LLWU_FILT2) 19.4.16/327...
Page 308 Memory map/register definition LLWU_PE1 field descriptions (continued) Field Description Enables and configures the edge detection for the wakeup pin. External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection External input pin enabled with any change detection WUPE0 Wakeup Pin Enable For LLWU_P0...
Page 309 Chapter 19 Low-Leakage Wakeup Unit (LLWU) LLWU_PE2 field descriptions (continued) Field Description External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection External input pin enabled with any change detection 3–2 Wakeup Pin Enable For LLWU_P5 WUPE5...
Page 310 Memory map/register definition LLWU_PE3 field descriptions (continued) Field Description External input pin enabled with falling edge detection External input pin enabled with any change detection 5–4 Wakeup Pin Enable For LLWU_P10 WUPE10 Enables and configures the edge detection for the wakeup pin. External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection...
Page 311 Chapter 19 Low-Leakage Wakeup Unit (LLWU) LLWU_PE4 field descriptions Field Description 7–6 Wakeup Pin Enable For LLWU_P15 WUPE15 Enables and configures the edge detection for the wakeup pin. External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection External input pin enabled with any change detection 5–4...
Page 312 Memory map/register definition Address: 4007_C000h base + 4h offset = 4007_C004h Read WUPE19 WUPE18 WUPE17 WUPE16 Write Reset LLWU_PE5 field descriptions Field Description 7–6 Wakeup Pin Enable For LLWU_P19 WUPE19 Enables and configures the edge detection for the wakeup pin. External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection...
Page 313 Chapter 19 Low-Leakage Wakeup Unit (LLWU) types that do not trigger Chip Reset not VLLS. See the Introduction details for more information. Address: 4007_C000h base + 5h offset = 4007_C005h Read WUPE23 WUPE22 WUPE21 WUPE20 Write Reset LLWU_PE6 field descriptions Field Description 7–6...
Page 314 Memory map/register definition NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information.
Page 315 Chapter 19 Low-Leakage Wakeup Unit (LLWU) 19.4.8 LLWU Pin Enable 8 register (LLWU_PE8) LLWU_PE8 contains the field to enable and select the edge detect type for the external wakeup input pins LLWU_P31-LLWU_P28. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS.
Page 316 Memory map/register definition LLWU_PE8 field descriptions (continued) Field Description External input pin enabled with falling edge detection External input pin enabled with any change detection 19.4.9 LLWU Module Enable register (LLWU_ME) LLWU_ME contains the bits to enable the internal module flag as a wakeup input source for inputs MWUF7-MWUF0.
Page 317 Chapter 19 Low-Leakage Wakeup Unit (LLWU) LLWU_ME field descriptions (continued) Field Description Internal module flag not used as wakeup source Internal module flag used as wakeup source Wakeup Module Enable For Module 3 WUME3 Enables an internal module as a wakeup source input. Internal module flag not used as wakeup source Internal module flag used as wakeup source Wakeup Module Enable For Module 2...
Page 318 Memory map/register definition Address: 4007_C000h base + 9h offset = 4007_C009h Read WUF7 WUF6 WUF5 WUF4 WUF3 WUF2 WUF1 WUF0 Write Reset LLWU_PF1 field descriptions Field Description Wakeup Flag For LLWU_P7 WUF7 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF7.
Page 319 Chapter 19 Low-Leakage Wakeup Unit (LLWU) LLWU_PF1 field descriptions (continued) Field Description Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF1. LLWU_P1 input was not a wakeup source LLWU_P1 input was a wakeup source Wakeup Flag For LLWU_P0 WUF0...
Page 320 Memory map/register definition LLWU_PF2 field descriptions (continued) Field Description Wakeup Flag For LLWU_P14 WUF14 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF14. LLWU_P14 input was not a wakeup source LLWU_P14 input was a wakeup source Wakeup Flag For LLWU_P13 WUF13...
Page 321 Chapter 19 Low-Leakage Wakeup Unit (LLWU) 19.4.12 LLWU Pin Flag 3 register (LLWU_PF3) LLWU_PF3 contains the wakeup flags indicating which wakeup source caused the MCU to exit VLLS mode. For VLLS, this is the source causing the MCU reset flow. The external wakeup flags are read-only and clearing a flag is accomplished by a write of a 1 to the corresponding WUFx bit.
Page 322 Memory map/register definition LLWU_PF3 field descriptions (continued) Field Description Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF20. LLWU_P20 input was not a wakeup source LLWU_P20 input was a wakeup source Wakeup Flag For LLWU_P19 WUF19...
Page 323 Chapter 19 Low-Leakage Wakeup Unit (LLWU) Address: 4007_C000h base + Ch offset = 4007_C00Ch Read WUF31 WUF30 WUF29 WUF28 WUF27 WUF26 WUF25 WUF24 Write Reset LLWU_PF4 field descriptions Field Description Wakeup Flag For LLWU_P31 WUF31 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF31.
Page 324 Memory map/register definition LLWU_PF4 field descriptions (continued) Field Description Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF25. LLWU_P25 input was not a wakeup source LLWU_P25 input was a wakeup source Wakeup Flag For LLWU_P24 WUF24...
Page 325 Chapter 19 Low-Leakage Wakeup Unit (LLWU) LLWU_MF5 field descriptions (continued) Field Description Module 7 input was not a wakeup source Module 7 input was a wakeup source Wakeup flag For module 6 MWUF6 Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism.
Page 326 Memory map/register definition 19.4.15 LLWU Pin Filter 1 register (LLWU_FILT1) LLWU_FILT1 is a control and status register that is used to enable/disable the digital filter 1 features for an external pin. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS.
Page 327 Chapter 19 Low-Leakage Wakeup Unit (LLWU) 19.4.16 LLWU Pin Filter 2 register (LLWU_FILT2) LLWU_FILT2 is a control and status register that is used to enable/disable the digital filter 2 features for an external pin. NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS.
Page 328: Functional Description
Functional description 19.5 Functional description Thie low-leakage wakeup unit (LLWU) module allows internal peripherals and external input pins as a source of wakeup from low-leakage modes. It is operational only in VLLSx modes. The LLWU module contains pin enables for each external pin and internal module. For each external pin, the user can disable or select the edge type for the wakeup with the following options: •...
Page 329 Chapter 19 Low-Leakage Wakeup Unit (LLWU) 19.5.2 Initialization For an enabled peripheral wakeup input, the peripheral flag must be cleared by software before entering VLLSx mode to avoid an immediate exit from the mode. Flags associated with external input pins, filtered and unfiltered, must also be cleared by software prior to entry to VLLSx mode.
Page 330 Functional description KV4x Reference Manual, Rev. 2, 02/2015 Preliminary Freescale Semiconductor, Inc.
Page 331: Chapter 20 Crossbar Switch Lite (Axbs-Lite)
Chapter 20 Crossbar Switch Lite (AXBS-Lite) 20.1 Crossbar-Light Switch Configuration This section summarizes how the module has been configured in the chip. Master Modules Slave Modules Crossbar Switch ARM core code bus Flash controller ARM core system bus SRAM controller_L SRAM controller_U Peripheral...
Page 332: Crossbar Switch Slave Assignments
Introduction 20.1.1 Crossbar Switch Master Assignments The masters connected to the crossbar switch are assigned as follows: Master module Master port number ARM core code bus ARM core system bus 20.1.2 Crossbar Switch Slave Assignments The slaves connected to the crossbar switch are assigned as follows: Slave module Slave port number Flash memory controller...
Page 333: Memory Map / Register Definition
Chapter 20 Crossbar Switch Lite (AXBS-Lite) • Operation at a 1-to-1 clock frequency with the bus masters • Programmable configuration for fixed-priority or round-robin slave port arbitration (see the chip-specific information). 20.3 Memory Map / Register Definition This crossbar switch is designed for minimal gate count. It, therefore, has no memory- mapped configuration registers.
Page 334: Arbitration During Undefined Length Bursts
Functional Description After the master has control of the slave port it is targeting, the master remains in control of the slave port until it relinquishes the slave port by running an IDLE cycle or by targeting a different slave port for its next access. The master can also lose control of the slave port if another higher-priority master makes a request to the slave port.
Page 335: Fixed-Priority Operation
Chapter 20 Crossbar Switch Lite (AXBS-Lite) 20.4.2.2 Fixed-priority operation When operating in fixed-priority mode, each master is assigned a unique priority level with the highest numbered master having the highest priority (for example, in a system with 5 masters, master 1 has lower priority than master 3). If two masters request access to the same slave port, the master with the highest priority gains control over the slave port.
Page 336: Initialization/Application Information
Initialization/application information After granted access to a slave port, a master may perform as many transfers as desired to that port until another master makes a request to the same slave port. The next master in line is granted access to the slave port at the next transfer boundary, or possibly on the next clock cycle if the current master has no pending access request.
Page 337: Chapter 21 Peripheral Bridge (Aips-Lite)
Chapter 21 Peripheral Bridge (AIPS-Lite) 21.1 Number of peripheral bridges This device contains one peripheral bridge AIPS-Lite with registers. 21.2 Memory map The peripheral bridge is used to access the registers of most of the modules on this device. See Peripheral Memory Map for the memory slot assignment of each module.
Page 338 Introduction 21.5 Introduction The peripheral bridge converts the crossbar switch interface to an interface that can access most of the slave peripherals on this chip. The peripheral bridge occupies 64 MB of the address space, which is divided into peripheral slots of 4 KB. (It might be possible that all the peripheral slots are not used. See the memory map chapter for details on slot assignments.) The bridge includes separate clock enable inputs for each of the slots to accommodate slower peripherals.
Page 339 Chapter 21 Peripheral Bridge (AIPS-Lite) 21.6 Memory map/register definition The 32-bit peripheral bridge registers can be accessed only in supervisor mode by trusted bus masters. Additionally, these registers must be read from or written to only by a 32-bit aligned access. The peripheral bridge registers are mapped into the Peripheral Access Control Register A PACRA[PACR0] address space.
Page 340 Memory map/register definition A register field that maps to an unimplemented master or peripheral behaves as read- only-zero. Each master is assigned a logical ID from 0 to 15. See the master logical ID assignment table in the chip-specific AIPS information. Address: 4000_0000h base + 0h offset = 4000_0000h Reserved Reset...
Page 341 Chapter 21 Peripheral Bridge (AIPS-Lite) AIPS_MPRA field descriptions (continued) Field Description Determines whether the master is trusted for read accesses. This master is not trusted for read accesses. This master is trusted for read accesses. Master 1 Trusted for Writes MTW1 Determines whether the master is trusted for write accesses.
Page 342 Memory map/register definition 21.6.2 Peripheral Access Control Register (AIPS_PACRn) Each PACR register consists of eight 4-bit PACR fields. Each PACR field defines the access levels for a particular peripheral. The mapping between a peripheral and its PACR field is shown in the table below. The peripheral assignment to each PACR is defined by the memory map slot that the peripheral is assigned to.
Page 343 Chapter 21 Peripheral Bridge (AIPS-Lite) Address: 4000_0000h base + 20h offset + (4d × i), where i=0d to 3d Reset Reset * Notes: • The reset value is chip-dependent and can be found in the AIPS chip-specific information. AIPS_PACRn field descriptions Field Description This field is reserved.
Page 344 Memory map/register definition AIPS_PACRn field descriptions (continued) Field Description Write Protect Determines whether the peripheral allows write accesses. When this field is set and a write access is attempted, access terminates with an error response and no peripheral access initiates. This peripheral allows write accesses.
Page 345 Chapter 21 Peripheral Bridge (AIPS-Lite) AIPS_PACRn field descriptions (continued) Field Description Write Protect Determines whether the peripheral allows write accesses. When this field is set and a write access is attempted, access terminates with an error response and no peripheral access initiates. This peripheral allows write accesses.
Page 346 Memory map/register definition AIPS_PACRn field descriptions (continued) Field Description Write Protect Determines whether the peripheral allows write accesses. When this field is set and a write access is attempted, access terminates with an error response and no peripheral access initiates. This peripheral allows write accesses.
Page 347 Chapter 21 Peripheral Bridge (AIPS-Lite) AIPS_PACRn field descriptions (continued) Field Description Write Protect Determines whether the peripheral allows write accesses. When this field is set and a write access is attempted, access terminates with an error response and no peripheral access initiates. This peripheral allows write accesses.
Page 348 Memory map/register definition AIPS_PACRn field descriptions (continued) Field Description This peripheral does not require supervisor privilege level for accesses. This peripheral requires supervisor privilege level for accesses. Write Protect Determines whether the peripheral allows write accesses. When this field is set and a write access is attempted, access terminates with an error response and no peripheral access initiates.
Page 349 Chapter 21 Peripheral Bridge (AIPS-Lite) AIPS_PACRn field descriptions (continued) Field Description This peripheral does not require supervisor privilege level for accesses. This peripheral requires supervisor privilege level for accesses. Write Protect Determines whether the peripheral allows write accesses. When this field is set and a write access is attempted, access terminates with an error response and no peripheral access initiates.
Page 350 Memory map/register definition AIPS_PACRn field descriptions (continued) Field Description This peripheral does not require supervisor privilege level for accesses. This peripheral requires supervisor privilege level for accesses. Write Protect Determines whether the peripheral allows write accesses. When this field is set and a write access is attempted, access terminates with an error response and no peripheral access initiates.
Page 351: Functional Description
Chapter 21 Peripheral Bridge (AIPS-Lite) AIPS_PACRn field descriptions (continued) Field Description This peripheral does not require supervisor privilege level for accesses. This peripheral requires supervisor privilege level for accesses. Write Protect Determines whether the peripheral allows write accesses. When this field is set and a write access is attempted, access terminates with an error response and no peripheral access initiates.
Page 352: Access Support
Functional description The peripheral bridge manages all transactions destined for the attached slave devices and generates select signals for modules on the peripheral bus by decoding accesses within the attached address space. 21.7.1 Access support All combinations of access size and peripheral data port width are supported. An access that is larger than the target peripheral's data width will be decomposed to multiple, smaller accesses.
Page 353: Chapter 22 Direct Memory Access Multiplexer (Dmamux)
Chapter 22 Direct memory access multiplexer (DMAMUX) 22.1 Chip-specific DMAMUX information 22.1.1 DMA MUX request sources This device includes a DMA request mux that allows up to 63 DMA request signals to be mapped to any of the 16 DMA channels. Because of the mux there is not a hard correlation between any of the DMA request sources and a specific DMA channel.
Page 354 Chip-specific DMAMUX information Table 22-1. DMA request sources (continued) Source Number Peripheral Assignment Description flexPWMA_CP2 Submodule 2 DMA request for input capture on any of the Capture FIFO ( OR of 6 capture circuits X0,X1,A0,A1,B0,B1) flexPWMA_CP3 Submodule 3 DMA request for input capture on any of the Capture FIFO ( OR of 6 capture circuits X0,X1,A0,A1,B0,B1)
Page 355: Dma Transfers Via Pit Trigger
Chapter 22 Direct memory access multiplexer (DMAMUX) Table 22-1. DMA request sources (continued) Source Number Peripheral Assignment Description PDB1 — PDB0 — control module Port A — control module Port B — control module Port C — control module Port D —...
Page 356: Modes Of Operation
Introduction DMA channel #0 DMAMUX Source #1 DMA channel #1 Source #2 Source #3 Source #x Always #1 Always #y Trigger #1 DMA channel #n Trigger #z Figure 22-1. DMAMUX block diagram 22.2.2 Features The DMAMUX module provides these features: •...
Page 357: External Signal Description
Chapter 22 Direct memory access multiplexer (DMAMUX) In this mode, the DMA channel is disabled. Because disabling and enabling of DMA channels is done primarily via the DMA configuration registers, this mode is used mainly as the reset state for a DMA channel in the DMA channel MUX. It may also be used to temporarily suspend a DMA channel while reconfiguration of the system takes place, for example, changing the period of a DMA trigger.
Page 358 Memory map/register definition DMAMUX memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4002_1009 Channel Configuration register (DMAMUX_CHCFG10) 22.4.1/358 4002_100A Channel Configuration register (DMAMUX_CHCFG9) 22.4.1/358 4002_100B Channel Configuration register (DMAMUX_CHCFG8) 22.4.1/358 4002_100C Channel Configuration register (DMAMUX_CHCFG15) 22.4.1/358 4002_100D Channel Configuration register (DMAMUX_CHCFG14) 22.4.1/358...
Page 359: Dma Channels With Periodic Triggering Capability
Chapter 22 Direct memory access multiplexer (DMAMUX) DMAMUX_CHCFGn field descriptions (continued) Field Description Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode) Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.
Page 360 Functional description Source #1 Source #2 Source #3 DMA channel #0 Trigger #1 Source #x DMA channel #m-1 Trigger #m Always #1 Always #y Figure 22-19. DMAMUX triggered channels The DMA channel triggering capability allows the system to schedule regular DMA transfers, usually on the transmit side of certain peripherals, without the intervention of the processor.
Page 361: Dma Channels With No Triggering Capability
Chapter 22 Direct memory access multiplexer (DMAMUX) Peripheral request Trigger DMA request Figure 22-21. DMAMUX channel triggering: ignored trigger This triggering capability may be used with any peripheral that supports DMA transfers, and is most useful for two types of situations: •...
Page 362: Always-Enabled Dma Sources
Functional description 22.5.3 Always-enabled DMA sources In addition to the peripherals that can be used as DMA sources, there are six additional DMA sources that are always enabled. Unlike the peripheral DMA sources, where the peripheral controls the flow of data during DMA transfers, the sources that are always enabled provide no such "throttling"...
Page 363: Initialization/Application Information
Chapter 22 Direct memory access multiplexer (DMAMUX) In this option, the DMA is configured to transfer the data using both minor and major loops, and the DMA channel MUX does the channel reactivation. For this option, the DMA channel should be enabled and pointing to an "always enabled" source. Note that the reactivation of the channel can be continuous (DMA triggering is disabled) or can use the DMA triggering capability.
Page 364 Initialization/application information 2. Configure channel 1 in the DMA, including enabling the channel. 3. Configure a timer for the desired trigger interval. 4. Write 0xC5 to CHCFG1 (base address + 0x01). The following code example illustrates steps 1 and 4 above: void DMAMUX_Init(uint8_t DMA_CH, uint8_t DMAMUX_SOURCE) DMAMUX_0.CHCFG[DMA_CH].B.SOURCE = DMAMUX_SOURCE;...
Page 365 Chapter 22 Direct memory access multiplexer (DMAMUX) volatile unsigned char *CHCFG14= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000E); volatile unsigned char *CHCFG15= (volatile unsigned char *) (DMAMUX_BASE_ADDR+0x000F); In File main.c: #include "registers.h" *CHCFG1 = 0x00; *CHCFG1 = 0x85; To disable a source: A particular DMA source may be disabled by not writing the corresponding source value into any of the CHCFG registers.
Page 366 Initialization/application information In File main.c: #include "registers.h" *CHCFG8 = 0x00; *CHCFG8 = 0x87; KV4x Reference Manual, Rev. 2, 02/2015 Preliminary Freescale Semiconductor, Inc.
Page 367: Chapter 23 Direct Memory Access Controller (Edma)
Chapter 23 Direct Memory Access Controller (eDMA) 23.1 Introduction The enhanced direct memory access (eDMA) controller is a second-generation module capable of performing complex data transfers with minimal intervention from a host processor. The hardware microarchitecture includes: • A DMA engine that performs: •...
Page 368: Block Parts
Introduction eDMA system Write Address Write Data Transfer Control Descriptor (TCD) eDMA e ngine Program Model/ Read Data Channel Arbitration Read Data Address Path Control Data Path Write Data Address eDMA Peripheral eDMA Done Request Figure 23-1. eDMA system block diagram 23.1.2 Block parts The eDMA module is partitioned into two major modules: the eDMA engine and the transfer-control descriptor local memory.
Page 369 Chapter 23 Direct Memory Access Controller (eDMA) Table 23-1. eDMA engine submodules (continued) Submodule Function the new values for the TCDn_{SADDR, DADDR, CITER} back to local memory. If the major iteration count is exhausted, additional processing is performed, including the final address pointer updates, reloading the TCDn_CITER field, and a possible fetch of the next TCDn from memory as part of a scatter/gather operation.
Page 370: Modes Of Operation
Modes of operation • 16-channel implementation that performs complex data transfers with minimal intervention from a host processor • Internal data buffer, used as temporary storage to support 16- and 32-byte transfers • Connections to the crossbar switch for bus mastering the data movement •...
Page 371: Memory Map/Register Definition
Chapter 23 Direct Memory Access Controller (eDMA) Table 23-3. Modes of operation Mode Description Normal In Normal mode, the eDMA transfers data between a source and a destination. The source and destination can be a memory block or an I/O block capable of operation with the eDMA. A service request initiates a transfer of a specific number of bytes (NBYTES) as specified in the transfer control descriptor (TCD).
Page 372: Tcd Structure
Memory map/register definition 23.3.3 TCD structure 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 0000h SADDR 0004h SMOD SSIZE DMOD DSIZE SOFF NBYTES DMA_CR[EMLM] disabled 0008h MLOFF or NBYTES NBYTES...
Page 373 Chapter 23 Direct Memory Access Controller (eDMA) DMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4000_801A Clear Enable Request Register (DMA_CERQ) (always 23.3.7/394 reads 0) 4000_801B Set Enable Request Register (DMA_SERQ) (always 23.3.8/395 reads 0)
Page 374 Memory map/register definition DMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) TCD Minor Byte Count (Minor Loop Disabled) 4000_9008 Undefined 23.3.21/413 (DMA_TCD0_NBYTES_MLNO) TCD Signed Minor Loop Offset (Minor Loop Enabled and 4000_9008 Undefined 23.3.22/414...
Page 375 Chapter 23 Direct Memory Access Controller (eDMA) DMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) TCD Beginning Minor Loop Link, Major Loop Count 4000_903E (Channel Linking Enabled) Undefined 23.3.31/423 (DMA_TCD1_BITER_ELINKYES) TCD Beginning Minor Loop Link, Major Loop Count 4000_903E Undefined 23.3.32/424...
Page 376 Memory map/register definition DMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) TCD Signed Destination Address Offset 4000_9074 Undefined 23.3.26/417 (DMA_TCD3_DOFF) TCD Current Minor Loop Link, Major Loop Count (Channel 4000_9076 Undefined 23.3.27/418 Linking Enabled) (DMA_TCD3_CITER_ELINKYES) 4000_9076...
Page 377 Chapter 23 Direct Memory Access Controller (eDMA) DMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) TCD Signed Minor Loop Offset (Minor Loop Enabled and 4000_90A8 Undefined 23.3.22/414 Offset Disabled) (DMA_TCD5_NBYTES_MLOFFNO) TCD Signed Minor Loop Offset (Minor Loop and Offset 4000_90A8 Undefined 23.3.23/415...
Page 378 Memory map/register definition DMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) TCD Beginning Minor Loop Link, Major Loop Count 4000_90DE Undefined 23.3.32/424 (Channel Linking Disabled) (DMA_TCD6_BITER_ELINKNO) 4000_90E0 TCD Source Address (DMA_TCD7_SADDR) Undefined 23.3.18/411 4000_90E4...
Page 379 Chapter 23 Direct Memory Access Controller (eDMA) DMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4000_9116 DMA_TCD8_CITER_ELINKNO Undefined 23.3.28/419 TCD Last Destination Address Adjustment/Scatter Gather 4000_9118 Undefined 23.3.29/420 Address (DMA_TCD8_DLASTSGA) 4000_911C TCD Control and Status (DMA_TCD8_CSR) Undefined 23.3.30/421 TCD Beginning Minor Loop Link, Major Loop Count...
Page 380 Memory map/register definition DMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) TCD Last Source Address Adjustment 4000_914C Undefined 23.3.24/416 (DMA_TCD10_SLAST) 4000_9150 TCD Destination Address (DMA_TCD10_DADDR) Undefined 23.3.25/417 TCD Signed Destination Address Offset 4000_9154 Undefined 23.3.26/417...
Page 381 Chapter 23 Direct Memory Access Controller (eDMA) DMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4000_9180 TCD Source Address (DMA_TCD12_SADDR) Undefined 23.3.18/411 4000_9184 TCD Signed Source Address Offset (DMA_TCD12_SOFF) Undefined 23.3.19/411 4000_9186 TCD Transfer Attributes (DMA_TCD12_ATTR) Undefined...
Page 382 Memory map/register definition DMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) TCD Last Destination Address Adjustment/Scatter Gather 4000_91B8 Undefined 23.3.29/420 Address (DMA_TCD13_DLASTSGA) 4000_91BC TCD Control and Status (DMA_TCD13_CSR) Undefined 23.3.30/421 TCD Beginning Minor Loop Link, Major Loop Count 4000_91BE (Channel Linking Enabled) Undefined...
Page 383 Chapter 23 Direct Memory Access Controller (eDMA) DMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) TCD Signed Minor Loop Offset (Minor Loop and Offset 4000_91E8 Undefined 23.3.23/415 Enabled) (DMA_TCD15_NBYTES_MLOFFYES) TCD Last Source Address Adjustment 4000_91EC Undefined 23.3.24/416...
Page 384 Memory map/register definition complete, the minor loop offset is ignored and the major loop address offsets (TCDn_SLAST and TCDn_DLAST_SGA) are used to compute the next TCDn_SADDR and TCDn_DADDR values. When minor loop mapping is enabled (EMLM is 1), TCDn word2 is redefined. A portion of TCDn word2 is used to specify multiple fields: a source enable bit (SMLOE) to specify the minor loop offset should be applied to the source address (TCDn_SADDR) upon minor loop completion, a destination enable bit (DMLOE) to specify the minor loop...
Page 385 Chapter 23 Direct Memory Access Controller (eDMA) DMA_CR field descriptions (continued) Field Description Normal operation Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence.
Page 386 Memory map/register definition 23.3.2 Error Status Register (DMA_ES) The ES provides information concerning the last recorded channel error. Channel errors can be caused by: • A configuration error, that is: • An illegal setting in the transfer-control descriptor, or • An illegal priority register setting in fixed-arbitration •...
Page 387 Chapter 23 Direct Memory Access Controller (eDMA) DMA_ES field descriptions (continued) Field Description 11–8 Error Channel Number or Canceled Channel Number ERRCHN The channel number of the last recorded error, excluding CPE errors, or last recorded error canceled transfer. Source Address Error No source address configuration error.
Page 388 Memory map/register definition 23.3.3 Enable Request Register (DMA_ERQ) The ERQ register provides a bit map for the 16 channels to enable the request signal for each channel. The state of any given channel enable is directly affected by writes to this register;...
Page 389 Chapter 23 Direct Memory Access Controller (eDMA) DMA_ERQ field descriptions (continued) Field Description Enable DMA Request 12 ERQ12 The DMA request signal for the corresponding channel is disabled The DMA request signal for the corresponding channel is enabled Enable DMA Request 11 ERQ11 The DMA request signal for the corresponding channel is disabled The DMA request signal for the corresponding channel is enabled...
Page 390 Memory map/register definition DMA_ERQ field descriptions (continued) Field Description Enable DMA Request 0 ERQ0 The DMA request signal for the corresponding channel is disabled The DMA request signal for the corresponding channel is enabled 23.3.4 Enable Error Interrupt Register (DMA_EEI) The EEI register provides a bit map for the 16 channels to enable the error interrupt signal for each channel.
Page 391 Chapter 23 Direct Memory Access Controller (eDMA) DMA_EEI field descriptions (continued) Field Description The error signal for corresponding channel does not generate an error interrupt The assertion of the error signal for corresponding channel generates an error interrupt request Enable Error Interrupt 13 EEI13 The error signal for corresponding channel does not generate an error interrupt The assertion of the error signal for corresponding channel generates an error interrupt request...
Page 392 Memory map/register definition DMA_EEI field descriptions (continued) Field Description The error signal for corresponding channel does not generate an error interrupt The assertion of the error signal for corresponding channel generates an error interrupt request Enable Error Interrupt 1 EEI1 The error signal for corresponding channel does not generate an error interrupt The assertion of the error signal for corresponding channel generates an error interrupt request Enable Error Interrupt 0...
Page 393 Chapter 23 Direct Memory Access Controller (eDMA) 23.3.6 Set Enable Error Interrupt Register (DMA_SEEI) The SEEI provides a simple memory-mapped mechanism to set a given bit in the EEI to enable the error interrupt for a given channel. The data value on a register write causes the corresponding bit in the EEI to be set.
Page 394 Memory map/register definition 23.3.7 Clear Enable Request Register (DMA_CERQ) The CERQ provides a simple memory-mapped mechanism to clear a given bit in the ERQ to disable the DMA request for a given channel. The data value on a register write causes the corresponding bit in the ERQ to be cleared.
Page 395 Chapter 23 Direct Memory Access Controller (eDMA) 23.3.8 Set Enable Request Register (DMA_SERQ) The SERQ provides a simple memory-mapped mechanism to set a given bit in the ERQ to enable the DMA request for a given channel. The data value on a register write causes the corresponding bit in the ERQ to be set.
Page 396 Memory map/register definition 23.3.9 Clear DONE Status Bit Register (DMA_CDNE) The CDNE provides a simple memory-mapped mechanism to clear the DONE bit in the TCD of the given channel. The data value on a register write causes the DONE bit in the corresponding transfer control descriptor to be cleared.
Page 397 Chapter 23 Direct Memory Access Controller (eDMA) 23.3.10 Set START Bit Register (DMA_SSRT) The SSRT provides a simple memory-mapped mechanism to set the START bit in the TCD of the given channel. The data value on a register write causes the START bit in the corresponding transfer control descriptor to be set.
Page 398 Memory map/register definition 23.3.11 Clear Error Register (DMA_CERR) The CERR provides a simple memory-mapped mechanism to clear a given bit in the ERR to disable the error condition flag for a given channel. The given value on a register write causes the corresponding bit in the ERR to be cleared.
Page 399 Chapter 23 Direct Memory Access Controller (eDMA) 23.3.12 Clear Interrupt Request Register (DMA_CINT) The CINT provides a simple, memory-mapped mechanism to clear a given bit in the INT to disable the interrupt request for a given channel. The given value on a register write causes the corresponding bit in the INT to be cleared.
Page 400 Memory map/register definition 23.3.13 Interrupt Request Register (DMA_INT) The INT register provides a bit map for the 16 channels signaling the presence of an interrupt request for each channel. Depending on the appropriate bit setting in the transfer-control descriptors, the eDMA engine generates an interrupt on data transfer completion.
Page 401 Chapter 23 Direct Memory Access Controller (eDMA) DMA_INT field descriptions (continued) Field Description Interrupt Request 15 INT15 The interrupt request for corresponding channel is cleared The interrupt request for corresponding channel is active Interrupt Request 14 INT14 The interrupt request for corresponding channel is cleared The interrupt request for corresponding channel is active Interrupt Request 13 INT13...
Page 402 Memory map/register definition DMA_INT field descriptions (continued) Field Description Interrupt Request 3 INT3 The interrupt request for corresponding channel is cleared The interrupt request for corresponding channel is active Interrupt Request 2 INT2 The interrupt request for corresponding channel is cleared The interrupt request for corresponding channel is active Interrupt Request 1 INT1...
Page 403 Chapter 23 Direct Memory Access Controller (eDMA) Address: 4000_8000h base + 2Ch offset = 4000_802Ch Reset Reset DMA_ERR field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Error In Channel 15 ERR15 An error in this channel has not occurred An error in this channel has occurred...
Page 404 Memory map/register definition DMA_ERR field descriptions (continued) Field Description Error In Channel 9 ERR9 An error in this channel has not occurred An error in this channel has occurred Error In Channel 8 ERR8 An error in this channel has not occurred An error in this channel has occurred Error In Channel 7 ERR7...
Page 405 Chapter 23 Direct Memory Access Controller (eDMA) 23.3.15 Hardware Request Status Register (DMA_HRS) The HRS register provides a bit map for the DMA channels, signaling the presence of a hardware request for each channel. The hardware request status bits reflect the current state of the register and qualified (via the ERQ fields) DMA request signals as seen by the DMA’s arbitration logic.
Page 406 Memory map/register definition DMA_HRS field descriptions (continued) Field Description The HRS bit for its respective channel remains asserted for the period when a Hardware Request is Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically cleared by hardware.
Page 407 Chapter 23 Direct Memory Access Controller (eDMA) DMA_HRS field descriptions (continued) Field Description A hardware service request for channel 9 is not present A hardware service request for channel 9 is present Hardware Request Status Channel 8 HRS8 The HRS bit for its respective channel remains asserted for the period when a Hardware Request is Present on the Channel.
Page 408 Memory map/register definition DMA_HRS field descriptions (continued) Field Description The HRS bit for its respective channel remains asserted for the period when a Hardware Request is Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically cleared by hardware.
Page 409 Chapter 23 Direct Memory Access Controller (eDMA) DMA_EARS field descriptions (continued) Field Description Enable asynchronous DMA request in stop mode for channel 15 EDREQ_15 Disable asynchronous DMA request for channel 15. Enable asynchronous DMA request for channel 15. Enable asynchronous DMA request in stop mode for channel 14 EDREQ_14 Disable asynchronous DMA request for channel 14.
Page 410 Memory map/register definition DMA_EARS field descriptions (continued) Field Description Enable asynchronous DMA request in stop mode for channel 3. EDREQ_3 Disable asynchronous DMA request for channel 3. Enable asynchronous DMA request for channel 3. Enable asynchronous DMA request in stop mode for channel 2. EDREQ_2 Disable asynchronous DMA request for channel 2.
Page 411 Chapter 23 Direct Memory Access Controller (eDMA) DMA_DCHPRIn field descriptions (continued) Field Description Disable Preempt Ability. Channel n can suspend a lower priority channel. Channel n cannot suspend any channel, regardless of channel priority. 5–4 This field is reserved. Reserved This read-only field is reserved and always has the value 0.
Page 412 Memory map/register definition DMA_TCDn_SOFF field descriptions Field Description SOFF Source address signed offset Sign-extended offset applied to the current source address to form the next-state value as each source read is completed. 23.3.20 TCD Transfer Attributes (DMA_TCDn_ATTR) Address: 4000_8000h base + 1006h offset + (32d × i), where i=0d to 15d Read SMOD SSIZE...
Page 413 Chapter 23 Direct Memory Access Controller (eDMA) DMA_TCDn_ATTR field descriptions (continued) Field Description See the SSIZE definition 23.3.21 TCD Minor Byte Count (Minor Loop Disabled) (DMA_TCDn_NBYTES_MLNO) This register, or one of the next two registers (TCD_NBYTES_MLOFFNO, TCD_NBYTES_MLOFFYES), defines the number of bytes to transfer per request. Which register to use depends on whether minor loop mapping is disabled, enabled but not used for this channel, or enabled and used.
Page 414 Memory map/register definition 23.3.22 TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) (DMA_TCDn_NBYTES_MLOFFNO) One of three registers (this register, TCD_NBYTES_MLNO, or TCD_NBYTES_MLOFFYES), defines the number of bytes to transfer per request. Which register to use depends on whether minor loop mapping is disabled, enabled but not used for this channel, or enabled and used.
Page 415 Chapter 23 Direct Memory Access Controller (eDMA) DMA_TCDn_NBYTES_MLOFFNO field descriptions (continued) Field Description The minor loop offset is not applied to the DADDR The minor loop offset is applied to the DADDR NBYTES Minor Byte Transfer Count Number of bytes to be transferred in each service request of the channel. As a channel activates, the appropriate TCD contents load into the eDMA engine, and the appropriate reads and writes perform until the minor byte transfer count has transferred.
Page 416 Memory map/register definition • x = Undefined at reset. DMA_TCDn_NBYTES_MLOFFYES field descriptions Field Description Source Minor Loop Offset Enable SMLOE Selects whether the minor loop offset is applied to the source address upon minor loop completion. The minor loop offset is not applied to the SADDR The minor loop offset is applied to the SADDR Destination Minor Loop Offset enable DMLOE...
Page 417 Chapter 23 Direct Memory Access Controller (eDMA) 23.3.25 TCD Destination Address (DMA_TCDn_DADDR) Address: 4000_8000h base + 1010h offset + (32d × i), where i=0d to 15d DADDR x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* Reset * Notes: •...
Page 418 Memory map/register definition 23.3.27 TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (DMA_TCDn_CITER_ELINKYES) If TCDn_CITER[ELINK] is set, the TCDn_CITER register is defined as follows. Address: 4000_8000h base + 1016h offset + (32d × i), where i=0d to 15d Read ELINK LINKCH...
Page 419 Chapter 23 Direct Memory Access Controller (eDMA) DMA_TCDn_CITER_ELINKYES field descriptions (continued) Field Description NOTE: When the CITER field is initially loaded by software, it must be set to the same value as that contained in the BITER field. NOTE: If the channel is configured to execute a single service request, the initial values of BITER and CITER should be 0x0001.
Page 420 Memory map/register definition DMA_TCDn_CITER_ELINKNO field descriptions (continued) Field Description example, final source and destination address calculations, optionally generating an interrupt to signal channel completion before reloading the CITER field from the Beginning Iteration Count (BITER) field. NOTE: When the CITER field is initially loaded by software, it must be set to the same value as that contained in the BITER field.
Page 421 Chapter 23 Direct Memory Access Controller (eDMA) 23.3.30 TCD Control and Status (DMA_TCDn_CSR) Address: 4000_8000h base + 101Ch offset + (32d × i), where i=0d to 15d Read MAJORLINKCH Write Reset Read MAJORELI DONE ACTIVE DREQ INTHALF INTMAJOR START Write Reset * Notes: •...
Page 422 Memory map/register definition DMA_TCDn_CSR field descriptions (continued) Field Description This flag signals the channel is currently in execution. It is set when channel service begins, and is cleared by the eDMA as the minor loop completes or when any error condition is detected. Enable channel-to-channel linking on major loop complete MAJORELINK As the channel completes the major loop, this flag enables the linking to another channel, defined by...
Page 423 Chapter 23 Direct Memory Access Controller (eDMA) DMA_TCDn_CSR field descriptions (continued) Field Description If this flag is set, the channel is requesting service. The eDMA hardware automatically clears this flag after the channel begins execution. The channel is not explicitly started. The channel is explicitly started via a software initiated service request.
Page 424 Memory map/register definition DMA_TCDn_BITER_ELINKYES field descriptions (continued) Field Description NOTE: When the software loads the TCD, this field must be set equal to the corresponding CITER field; otherwise, a configuration error is reported. As the major iteration count is exhausted, the contents of this field are reloaded into the CITER field.
Page 425: Functional Description
Chapter 23 Direct Memory Access Controller (eDMA) DMA_TCDn_BITER_ELINKNO field descriptions (continued) Field Description The channel-to-channel linking is disabled The channel-to-channel linking is enabled BITER Starting Major Iteration Count As the transfer control descriptor is first loaded by software, this 9-bit (ELINK = 1) or 15-bit (ELINK = 0) field must be equal to the value in the CITER field.
Page 426 Functional description eDMA Write Address Write Data Transfer Control Descriptor (TCD) eDMA Engine Program Model/ Read Data Channel Arbitration Read Data Address Path Control Data Path Write Data Address eDMA Peripheral eDMA Done Request Figure 23-290. eDMA operation, part 1 This example uses the assertion of the eDMA peripheral request signal to request service for channel n.
Page 427 Chapter 23 Direct Memory Access Controller (eDMA) eDMA Write Address Write Data Transfer Control Descriptor (TCD) eDMA Engine Program Model/ Read Data Channel Arbitration Read Data Address Path Control Data Path Write Data Address eDMA Peripheral eDMA Done Request Figure 23-291. eDMA operation, part 2 The modules associated with the data transfer (address path, data path, and control) sequence through the required source reads and destination writes to perform the actual data movement.
Page 428: Fault Reporting And Handling
Functional description eDMA Write Address Write Data Transfer Control Descriptor (TCD) eDMA En g in e Program Model/ Read Data Channel Arbitration Read Data Address Path Control Data Path Write Data Address eDMA Peripheral eDMA Done Request Figure 23-292. eDMA operation, part 3 23.4.2 Fault reporting and handling Channel errors are reported in the Error Status register (DMAx_ES) and can be caused •...
Page 429 Chapter 23 Direct Memory Access Controller (eDMA) • All source reads and destination writes must be configured to the natural boundary of the programmed transfer size respectively. • In fixed arbitration mode, a configuration error is caused by any two channel priorities being equal.
Page 430 Functional description occurs on the last read prior to beginning the write sequence, the write executes using the data captured during the bus error. If a bus error occurs on the last write prior to switching to the next read sequence, the read sequence executes before the channel terminates due to the destination bus error.
Page 431: Channel Preemption
Chapter 23 Direct Memory Access Controller (eDMA) 23.4.3 Channel preemption Channel preemption is enabled on a per-channel basis by setting the DCHPRIn[ECP] bit. Channel preemption allows the executing channel’s data transfers to temporarily suspend in favor of starting a higher priority channel. After the preempting channel has completed all its minor loop data transfers, the preempted channel is restored and resumes execution.
Page 432 Functional description • Internal SRAM can be accessed with zero wait-states when viewed from the system bus data phase • All internal peripheral bus reads require two wait-states, and internal peripheral bus writes three wait-states, when viewed from the system bus data phase •...
Page 433 Chapter 23 Direct Memory Access Controller (eDMA) Table 23-294. Hardware service request process Cycle Description With internal peripheral With SRAM read and bus read and internal internal peripheral bus SRAM write write eDMA peripheral request is asserted. The eDMA peripheral request is registered locally in the eDMA module and qualified.
Page 434 Functional description Table 23-295. eDMA peak request rate (MReq/sec) Request rate Request rate System frequency (MHz) with zero wait states with wait states 66.6 83.3 100.0 11.1 133.3 14.8 11.6 150.0 16.6 13.0 A general formula to compute the peak request rate with overlapping requests is: PEAKreq = freq / [ entry + (1 + read_ws) + (1 + write_ws) + exit ] where: Table 23-296.
Page 435: Initialization/Application Information
Chapter 23 Direct Memory Access Controller (eDMA) PEAKreq = 150 MHz / [ 4 + (1 + 2) + (1 + 1) + 3 ] cycles = 12.5 Mreq/sec Assuming an even distribution of the two transfer types, the average peak request rate would be: PEAKreq = (11.5 Mreq/sec + 12.5 Mreq/sec) / 2 = 12.0 Mreq/sec The minimum number of cycles to perform a single read/write, zero wait states on the...
Page 436 Initialization/application information 5. Enable any hardware service requests via the ERQH and ERQL registers. 6. Request channel service via either: • Software: setting the TCDn_CSR[START] • Hardware: slave device asserting its eDMA peripheral request signal After any channel requests service, a channel is selected for execution based on the arbitration and priority levels written into the programmer's model.
Page 437: Programming Errors
Chapter 23 Direct Memory Access Controller (eDMA) Current major loop iteration Source or destination memory count (CITER) DMA request DMA request DMA request Figure 23-293. Example of multiple loop iterations The following figure lists the memory array terms and how the TCD settings interrelate. xADDR: (Starting address) xSIZE: (size of one Minor loop...
Page 438: Arbitration Mode Considerations
Initialization/application information For all error types other than channel priority error, the channel number causing the error is recorded in the Error Status register (DMAx_ES). If the error source is not removed before the next activation of the problem channel, the error is detected and recorded again.
Page 439 Chapter 23 Direct Memory Access Controller (eDMA) For example, the following TCD entry is configured to transfer 16 bytes of data. The eDMA is programmed for one iteration of the major loop transferring 16 bytes per iteration. The source memory has a byte wide memory port located at 0x1000. The destination memory has a 32-bit port located at 0x2000.
Page 440: Multiple Requests
Initialization/application information h. Write 32-bits to location 0x200C → last iteration of the minor loop → major loop complete. 6. The eDMA engine writes: TCDn_SADDR = 0x1000, TCDn_DADDR = 0x2000, TCDn_CITER = 1 (TCDn_BITER). 7. The eDMA engine writes: TCDn_CSR[ACTIVE] = 0, TCDn_CSR[DONE] = 1, INT[n] = 1.
Page 441 Chapter 23 Direct Memory Access Controller (eDMA) f. Write 32-bits to location 0x2008 → third iteration of the minor loop. g. Read byte from location 0x100C, read byte from location 0x100D, read byte from 0x100E, read byte from 0x100F. h. Write 32-bits to location 0x200C → last iteration of the minor loop. 6.
Page 442: Using The Modulo Feature
Initialization/application information 15. eDMA engine writes: TCDn_CSR[ACTIVE] = 0, TCDn_CSR[DONE] = 1, INT[n] = 16. The channel retires → major loop complete. The eDMA goes idle or services the next channel. 23.5.4.3 Using the modulo feature The modulo feature of the eDMA provides the ability to implement a circular data queue in which the size of the queue is a power of 2.
Page 443: Reading The Transfer Descriptors Of Active Channels
Chapter 23 Direct Memory Access Controller (eDMA) to test the TCDn_CSR[START] bit and the TCDn_CSR[ACTIVE] bit. The minor-loop- complete condition is indicated by both bits reading zero after the TCDn_CSR[START] was set. Polling the TCDn_CSR[ACTIVE] bit may be inconclusive, because the active status may be missed if the channel execution is short in duration.
Page 444: Checking Channel Preemption Status
Initialization/application information DADDR, and NBYTES, which decrement to zero as the transfer progresses, can give an indication of the progress of the transfer. All other values are read back from the TCD local memory. 23.5.5.3 Checking channel preemption status Preemption is available only when fixed arbitration is selected as the channel arbitration mode.
Page 445: Dynamic Programming
Chapter 23 Direct Memory Access Controller (eDMA) 2. Minor loop done → set TCD12_CSR[START] bit 3. Minor loop done → set TCD12_CSR[START] bit 4. Minor loop done, major loop done→ set TCD7_CSR[START] bit When minor loop linking is enabled (TCDn_CITER[E_LINK] = 1), the TCDn_CITER[CITER] field uses a nine bit vector to form the current iteration count.
Page 446: Dynamic Channel Linking
Initialization/application information 1. Switch to Round-Robin Channel Arbitration mode, change the channel priorities, then switch back to Fixed Arbitration mode, 2. Disable all the channels, change the channel priorities, then enable the appropriate channels. 23.5.7.2 Dynamic channel linking Dynamic channel linking is the process of setting the TCD.major.e_link bit during channel execution.
Page 447: Dynamic Scatter/Gather
Chapter 23 Direct Memory Access Controller (eDMA) 23.5.7.3 Dynamic scatter/gather Scatter/gather is the process of automatically loading a new TCD into a channel. It allows a DMA channel to use multiple TCDs; this enables a DMA channel to scatter the DMA data to multiple destinations or gather it from multiple sources.When scatter/gather is enabled and the channel has finished its major loop, a new TCD is fetched from system memory and loaded into that channel’s descriptor location in eDMA programmer’s...
Page 448 Initialization/application information Should a dynamic scatter/gather attempt fail, setting the TCD.d_req bit will prevent a future hardware activation of this channel. This stops the channel from executing with a destination address (daddr) that was calculated using a scatter/gather address (written in the next step) instead of a dlast final offest value. 3.
Page 449 Chapter 23 Direct Memory Access Controller (eDMA) If e_sg = 0b and the dlast_sga changed, the dynamic link attempt was successful (the new TCD’s e_sg value cleared the e_sg bit). KV4x Reference Manual, Rev. 2, 02/2015 Preliminary Freescale Semiconductor, Inc.
Page 450 Initialization/application information KV4x Reference Manual, Rev. 2, 02/2015 Preliminary Freescale Semiconductor, Inc.
Page 451: Chapter 24 External Watchdog Monitor (Ewm)
Chapter 24 External Watchdog Monitor (EWM) 24.1 Chip-specific EWM information 24.1.1 EWM clocks This table shows the EWM clocks and the corresponding chip clocks. Table 24-1. EWM clock connections Module clock Chip clock Low Power Clock 1 kHz LPO Clock 24.1.2 EWM low-power modes This table shows the EWM low-power modes and the corresponding chip low-power modes.
Page 452 Introduction 24.2 Introduction The watchdog is generally used to monitor the flow and execution of embedded software within an MCU. The watchdog consists of a counter that if allowed to overflow, forces an internal reset (asynchronous) to all on-chip peripherals and optionally assert the RESET pin to reset external devices/circuits.
Page 453: Modes Of Operation
Chapter 24 External Watchdog Monitor (EWM) • One output port, EWM_out, when asserted is used to reset or place the external circuit into safe mode. • One Input port, EWM_in, allows an external circuit to control the EWM_out signal. 24.2.2 Modes of Operation This section describes the module's operating modes.
Page 454: Ewm Signal Descriptions
EWM Signal Descriptions Clock Gating Low Power Cell Clock Reset to Counter Counter Overflow Enable EWM refresh CPU Reset EWM_out EWM enable Counter > Compare High EWM Out Counter < Compare Low Logic EWM_out ((EWM_in ^ assert_in) || ~EWM_in_enable) Note 1: Compare High > Counter value > Compare Low Figure 24-1.
Page 455 Chapter 24 External Watchdog Monitor (EWM) EWM memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4006_1000 Control Register (EWM_CTRL) 24.4.1/455 4006_1001 Service Register (EWM_SERV) (always 24.4.2/456 reads 0) 4006_1002 Compare Low Register (EWM_CMPL) 24.4.3/456 4006_1003 Compare High Register (EWM_CMPH)
Page 456 Memory Map/Register Definition 24.4.2 Service Register (EWM_SERV) The SERV register provides the interface from the CPU to the EWM module. It is write- only and reads of this register return zero. Address: 4006_1000h base + 1h offset = 4006_1001h Read Write SERVICE Reset...
Page 457: Functional Description
Chapter 24 External Watchdog Monitor (EWM) 24.4.4 Compare High Register (EWM_CMPH) The CMPH register is reset to 0xFF after a CPU reset. This provides a maximum of 256 clocks time, for the CPU to service the EWM counter. NOTE This register can be written only once after a CPU reset. Writing this register more than once generates a bus transfer error.
Page 458 Functional Description The EWM_out signal is asserted in any of the following conditions: • Servicing the EWM when the counter value is less than CMPL value. • If the EWM counter value reaches the CMPH value, and no EWM service has occurred.
Page 459: Ewm Counter
Chapter 24 External Watchdog Monitor (EWM) Note You must update the CMPH and CMPL registers prior to enabling the EWM. After enabling the EWM, the counter resets to zero, therefore providing a reasonable time after a power-on reset for the external monitoring circuit to stabilize and ensure that the EWM_in pin is deasserted.
Page 460: Ewm Interrupt
Functional Description Table 24-9. EWM Refresh Mechanisms Condition Mechanism A unique EWM service occurs when CMPL The software behaves as expected and the counter of the EWM is reset to zero, < Counter < CMPH. and EWM_out pin remains in the deasserted state. Note: EWM_in pin is also assumed to be in the deasserted state.
Page 461: Chapter 25 Watchdog Timer (Wdog)
Chapter 25 Watchdog Timer (WDOG) 25.1 Chip-specific WDOG information 25.1.1 WDOG clocks This table shows the WDOG module clocks and the corresponding chip clocks. Table 25-1. WDOG clock connections Module clock Chip clock LPO Oscillator 1 kHz LPO Clock Fast Test Clock Bus Clock System Bus Clock Bus Clock...
Page 462 Introduction 25.2 Introduction The Watchdog Timer (WDOG) keeps a watch on the system functioning and resets it in case of its failure. Reasons for failure include run-away software code and the stoppage of the system clock that in a safety critical system can lead to serious consequences. In such cases, the watchdog brings the system into a safe state of operation.
Page 463: Functional Overview
Chapter 25 Watchdog Timer (WDOG) NOTE Reading the watchdog timer counter while running the watchdog on the bus clock might not give the accurate counter value. • Windowed refresh option • Provides robust check that program flow is faster than expected. •...
Page 464 Functional overview WDOG Disable Control/Configuration Unlock Sequence bit changes N bus clk cycles after 2 Writes of data within K bus clock unlocking cycles of each other Refresh Sequence 2 writes of data within K 0xC520 bus clock cycles of each N bus clk cycles other 0xD928...
Page 465: Unlocking And Updating The Watchdog
Chapter 25 Watchdog Timer (WDOG) You can select a windowed mode of operation that expects the servicing to be done only in a particular window of the time-out period. An attempted servicing of the watchdog outside this window results in a reset. By operating in this mode, you can get an indication of whether the code is running faster than expected.
Page 466: Watchdog Configuration Time (Wct)
Functional overview • Write any value other than 0xC520 or 0xD928 to the unlock register. • ALLOW_UPDATE is set and a gap of more than 20 bus clock cycles is inserted between the writing of the unlock sequence values. An attempted refresh operation between the two writes of the unlock sequence and in the WCT time following a successful unlock, goes undetected.
Page 467: Refreshing The Watchdog
Chapter 25 Watchdog Timer (WDOG) 25.4.3 Refreshing the watchdog A robust refreshing mechanism has been chosen for the watchdog. A valid refresh is a write of 0xA602 followed by 0xB480 within 20 bus clock cycles to watchdog refresh register. If these two values are written more than 20 bus cycles apart or if something other than these two values is written to the register, a watchdog reset, or interrupt-then- reset if enabled, is issued to the system.
Page 468: Debug Modes Of Operation
Testing the watchdog Table 25-3. Low-power modes of operation Mode Behavior Wait If the WDOG is enabled (WAIT_EN = 1), it can run on bus clock or low-power oscillator clock (CLK_SRC = x) to generate interrupt (IRQ_RST_EN=1) followed by a reset on time-out. After reset the WDOG reset counter increments by one.
Page 469: Quick Test
Chapter 25 Watchdog Timer (WDOG) this end, two tests are implemented for the watchdog, as described in Quick Test Byte Test. A control bit is provided to put the watchdog into functional test mode. There is also an overriding test-disable control bit which allows the functional test mode to be disabled permanently.
Page 470 Testing the watchdog 25.5.2 Byte test The byte test is a more thorough a test of the watchdog timer. In this test, the timer is split up into its constituent byte-wide stages that are run independently and tested for time-out against the corresponding byte of the time-out value register.
Page 471: Backup Reset Generator
Chapter 25 Watchdog Timer (WDOG) 25.6 Backup reset generator The backup reset generator generates the final reset which goes out to the system. It has a backup mechanism which ensures that in case the bus clock stops and prevents the main state machine from generating a reset exception/interrupt, the watchdog timer's time-out is separately routed out as a reset to the system.
Page 472: Memory Map And Register Definition
Memory map and register definition The gap of WCT between interrupt and reset means that the WDOG time-out value must be greater than WCT. Otherwise, if the interrupt was generated due to a time-out, a second consecutive time-out will occur in that WCT gap. This will trigger the backup reset generator to generate a reset to the system, prematurely ending the interrupt service routine execution.
Page 473 Chapter 25 Watchdog Timer (WDOG) WDOG_STCTRLH field descriptions Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. Allows the WDOG’s functional test mode to be disabled permanently. After it is set, it can only be cleared DISTESTWDOG by a reset.
Page 474 Memory map and register definition WDOG_STCTRLH field descriptions (continued) Field Description Used to enable the debug breadcrumbs feature. A change in this bit is updated immediately, as opposed IRQRSTEN to updating after WCT. WDOG time-out generates reset only. WDOG time-out initially generates an interrupt. After WCT, it generates a reset. Selects clock source for the WDOG timer and other internal timing operations.
Page 475 Chapter 25 Watchdog Timer (WDOG) 25.8.3 Watchdog Time-out Value Register High (WDOG_TOVALH) Address: 4005_2000h base + 4h offset = 4005_2004h Read TOVALHIGH Write Reset WDOG_TOVALH field descriptions Field Description TOVALHIGH Defines the upper 16 bits of the 32-bit time-out value for the watchdog timer. It is defined in terms of cycles of the watchdog clock.
Page 476 Memory map and register definition 25.8.5 Watchdog Window Register High (WDOG_WINH) NOTE You must set the Window Register value lower than the Time- out Value Register. Address: 4005_2000h base + 8h offset = 4005_2008h Read WINHIGH Write Reset WDOG_WINH field descriptions Field Description WINHIGH...
Page 477 Chapter 25 Watchdog Timer (WDOG) 25.8.7 Watchdog Refresh register (WDOG_REFRESH) Address: 4005_2000h base + Ch offset = 4005_200Ch Read WDOGREFRESH Write Reset WDOG_REFRESH field descriptions Field Description WDOGREFRESH Watchdog refresh register. A sequence of 0xA602 followed by 0xB480 within 20 bus clock cycles written to this register refreshes the WDOG and prevents it from resetting the system.
Page 478 Memory map and register definition 25.8.10 Watchdog Timer Output Register Low (WDOG_TMROUTL) During Stop mode, the WDOG_TIMER_OUT will be caught at the pre-stop value of the watchdog timer. After exiting Stop mode, a maximum delay of 1 WDOG_CLK cycle + 3 bus clock cycles will occur before the WDOG_TIMER_OUT starts following the watchdog timer.
Page 479: Refresh And Unlock Operations With 8-Bit Access
Chapter 25 Watchdog Timer (WDOG) WDOG_PRESC field descriptions Field Description 15–11 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 10–8 3-bit prescaler for the watchdog clock source. A value of zero indicates no division of the input WDOG PRESCVAL clock.
Page 480: Restrictions On Watchdog Operation
Restrictions on watchdog operation Table 25-17. Refresh for 8-bit access Sequence value1 or Mismatch WDOG_REFRESH[15:8] WDOG_REFRESH[7:0] value2 match exception Current Value 0xB4 0x80 Value2 match Write 1 0xB4 0x02 No match Write 2 0xA6 0x02 Value1 match Write 3 0xB4 0x02 No match Write 4...
Page 481 Chapter 25 Watchdog Timer (WDOG) watchdog functional test. A maximum time period of ~2 clock A cycles plus ~2 clock B cycles elapses from the time a switch is requested to the occurrence of the actual clock switch, where clock A and B are the two input clocks to the clock mux. •...
Page 482 Restrictions on watchdog operation • After emerging from a reset due to a watchdog functional test, you still need to go through the mandatory steps of unlocking and configuring the watchdog. • You must ensure that both the clock inputs to the glitchless clock multiplexers are alive during the switching of clocks.
Page 483: Chapter 26 Inter-Peripheral Crossbar Switch A (Xbara)
Chapter 26 Inter-Peripheral Crossbar Switch A (XBARA) 26.1 Chip-specific XBARA information 26.1.1 XBARA input signal assignment Table 26-1. XBARA input assignment XBARA Input Assigned Output XBARA_IN0 XBARA_IN1 XBARA_IN2 XB_IN2 XBARA_IN3 XB_IN3 XBARA_IN4 XB_IN4 XBARA_IN5 XB_IN5 XBARA_IN6 XB_IN6 XBARA_IN7 XB_IN7 XBARA_IN8 XB_IN8 XBARA_IN9 XB_IN9...
Page 484 Chip-specific XBARA information Table 26-1. XBARA input assignment (continued) XBARA Input Assigned Output XBARA_IN23 PWMA1_TRG1 XBARA_IN24 PWMA2_TRG0 XBARA_IN25 PWMA2_TRG1 XBARA_IN26 PWMA3_TRG0 XBARA_IN27 PWMA3_TRG1 XBARA_IN28 — XBARA_IN29 PDB0_OUT XBARA_IN30 — XBARA_IN31 PDB1_OUT XBARA_IN32 — XBARA_IN33 ADCA Scan complete XBARA_IN34 — XBARA_IN35 ADCB Scan complete XBARA_IN36 FTM1_allTRIG...
Page 485 Chapter 26 Inter-Peripheral Crossbar Switch A (XBARA) Table 26-2. XBARA signal output assignment (continued) XBARA Output Assigned Input XBARA_OUT2 DMAMUX20 XBARA_OUT3 DMAMUX21 XBARA_OUT4 XB_OUT4 XBARA_OUT5 XB_OUT5 XBARA_OUT6 XB_OUT6 XBARA_OUT7 XB_OUT7 XBARA_OUT8 XB_OUT8 XBARA_OUT9 XB_OUT9 XBARA_OUT10 XB_OUT10 XBARA_OUT11 XB_OUT11 XBARA_OUT12 ADCA_TRIG XBARA_OUT13 ADCB_TRIG XBARA_OUT14...
Page 486 Introduction Table 26-2. XBARA signal output assignment (continued) XBARA Output Assigned Input XBARA_OUT41 PDB1_IN_CH_1100 XBARA_OUT42 FTM1 channel 1 input capture XBARA_OUT43 — XBARA_OUT44 ENC_PHA XBARA_OUT45 ENC_PHB XBARA_OUT46 ENC_INDEX XBARA_OUT47 ENC_HOME XBARA_OUT48 ENC_CAP/Trigger XBARA_OUT49 FTM0_FAULT3 XBARA_OUT50 FTM1_FAULT1 XBARA_OUT51 — XBARA_OUT52 FTM3_FAULT3 XBARA_OUT53 —...
Page 487: Modes Of Operation
Chapter 26 Inter-Peripheral Crossbar Switch A (XBARA) 26.2.2 Features The XBAR module design includes these distinctive features: • M identical N-input muxes with individual select fields. • Edge detection with associated interrupt or DMA request generation for a subset of mux outputs.
Page 488: Signal Descriptions
Signal Descriptions DMA_ACK 0 DMA_REQ 0 DMA 0 INT_REQ 0 CTRL 0 XBAR_IN 0 XBAR_IN 1 XBAR_OUT 0 XBAR_IN N-1 DMA_ACK 1 DMA_REQ 1 DMA 1 SEL 0 INT_REQ 1 CTRL 1 IP_bus XBAR_OUT 1 SEL 1 DMA_ACK M-1 DMA_REQ M-1 CTRL M-1 INT_REQ M-1 XBAR_OUT M-1...
Page 489: Memory Map And Register Descriptions
Chapter 26 Inter-Peripheral Crossbar Switch A (XBARA) At reset, each output XBAR_OUT[*] contains the reset value of the signal driving XBAR_IN[0]. 26.3.1 XBAR_OUT[0:NUM_OUT-1] - MUX Outputs This is a one-dimensional array of the mux outputs. The value on each output XBAR_OUT[n] is determined by the setting of the corresponding memory mapped register SELn such that XBAR_OUT[n] = XBAR_IN[SELn].
Page 490 Memory Map and Register Descriptions presents the value of XBAR_IN[SELn]. Each select register contains two SELn fields. In the first select register, the LSBs contain the select field for mux 0, and the MSBs contain the select field for mux 1. The pattern repeats in subsequent select registers. The actual signals connected to XBAR_IN and XBAR_OUT are application specific and are described in the Chip Configuration details.
Page 491 Chapter 26 Inter-Peripheral Crossbar Switch A (XBARA) XBARA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4005_903A Crossbar A Select Register 29 (XBARA_SEL29) 0000h 26.4.30/505 4005_903C Crossbar A Control Register 0 (XBARA_CTRL0) 0000h 26.4.31/506 4005_903E...
Page 492 Memory Map and Register Descriptions XBARA_SEL1 field descriptions (continued) Field Description 7–6 This field is reserved. Reserved This read-only field is reserved and always has the value 0. SEL2 Input (XBARA_INn) to be muxed to XBARA_OUT2 (refer to Functional Description section for input/output assignment) 26.4.3 Crossbar A Select Register 2 (XBARA_SEL2) Address: 4005_9000h base + 4h offset = 4005_9004h...
Page 493 Chapter 26 Inter-Peripheral Crossbar Switch A (XBARA) XBARA_SEL3 field descriptions (continued) Field Description SEL6 Input (XBARA_INn) to be muxed to XBARA_OUT6 (refer to Functional Description section for input/output assignment) 26.4.5 Crossbar A Select Register 4 (XBARA_SEL4) Address: 4005_9000h base + 8h offset = 4005_9008h Read SEL9 SEL8...
Page 494 Memory Map and Register Descriptions 26.4.7 Crossbar A Select Register 6 (XBARA_SEL6) Address: 4005_9000h base + Ch offset = 4005_900Ch Read SEL13 SEL12 Write Reset XBARA_SEL6 field descriptions Field Description 15–14 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 13–8 Input (XBARA_INn) to be muxed to XBARA_OUT13 (refer to Functional Description section for input/ SEL13...
Page 495 Chapter 26 Inter-Peripheral Crossbar Switch A (XBARA) 26.4.9 Crossbar A Select Register 8 (XBARA_SEL8) Address: 4005_9000h base + 10h offset = 4005_9010h Read SEL17 SEL16 Write Reset XBARA_SEL8 field descriptions Field Description 15–14 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 13–8 Input (XBARA_INn) to be muxed to XBARA_OUT17 (refer to Functional Description section for input/ SEL17...
Page 496 Memory Map and Register Descriptions 26.4.11 Crossbar A Select Register 10 (XBARA_SEL10) Address: 4005_9000h base + 14h offset = 4005_9014h Read SEL21 SEL20 Write Reset XBARA_SEL10 field descriptions Field Description 15–14 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 13–8 Input (XBARA_INn) to be muxed to XBARA_OUT21 (refer to Functional Description section for input/ SEL21...
Page 497 Chapter 26 Inter-Peripheral Crossbar Switch A (XBARA) 26.4.13 Crossbar A Select Register 12 (XBARA_SEL12) Address: 4005_9000h base + 18h offset = 4005_9018h Read SEL25 SEL24 Write Reset XBARA_SEL12 field descriptions Field Description 15–14 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 13–8 Input (XBARA_INn) to be muxed to XBARA_OUT25 (refer to Functional Description section for input/ SEL25...
Page 498 Memory Map and Register Descriptions 26.4.15 Crossbar A Select Register 14 (XBARA_SEL14) Address: 4005_9000h base + 1Ch offset = 4005_901Ch Read SEL29 SEL28 Write Reset XBARA_SEL14 field descriptions Field Description 15–14 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 13–8 Input (XBARA_INn) to be muxed to XBARA_OUT29 (refer to Functional Description section for input/ SEL29...
Page 499 Chapter 26 Inter-Peripheral Crossbar Switch A (XBARA) 26.4.17 Crossbar A Select Register 16 (XBARA_SEL16) Address: 4005_9000h base + 20h offset = 4005_9020h Read SEL33 SEL32 Write Reset XBARA_SEL16 field descriptions Field Description 15–14 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 13–8 Input (XBARA_INn) to be muxed to XBARA_OUT33 (refer to Functional Description section for input/ SEL33...
Page 500 Memory Map and Register Descriptions 26.4.19 Crossbar A Select Register 18 (XBARA_SEL18) Address: 4005_9000h base + 24h offset = 4005_9024h Read SEL37 SEL36 Write Reset XBARA_SEL18 field descriptions Field Description 15–14 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 13–8 Input (XBARA_INn) to be muxed to XBARA_OUT37 (refer to Functional Description section for input/ SEL37...
Page 501 Chapter 26 Inter-Peripheral Crossbar Switch A (XBARA) 26.4.21 Crossbar A Select Register 20 (XBARA_SEL20) Address: 4005_9000h base + 28h offset = 4005_9028h Read SEL41 SEL40 Write Reset XBARA_SEL20 field descriptions Field Description 15–14 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 13–8 Input (XBARA_INn) to be muxed to XBARA_OUT41 (refer to Functional Description section for input/ SEL41...
Page 502 Memory Map and Register Descriptions 26.4.23 Crossbar A Select Register 22 (XBARA_SEL22) Address: 4005_9000h base + 2Ch offset = 4005_902Ch Read SEL45 SEL44 Write Reset XBARA_SEL22 field descriptions Field Description 15–14 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 13–8 Input (XBARA_INn) to be muxed to XBARA_OUT45 (refer to Functional Description section for input/ SEL45...
Page 503 Chapter 26 Inter-Peripheral Crossbar Switch A (XBARA) 26.4.25 Crossbar A Select Register 24 (XBARA_SEL24) Address: 4005_9000h base + 30h offset = 4005_9030h Read SEL49 SEL48 Write Reset XBARA_SEL24 field descriptions Field Description 15–14 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 13–8 Input (XBARA_INn) to be muxed to XBARA_OUT49 (refer to Functional Description section for input/ SEL49...
Page 504 Memory Map and Register Descriptions 26.4.27 Crossbar A Select Register 26 (XBARA_SEL26) Address: 4005_9000h base + 34h offset = 4005_9034h Read SEL53 SEL52 Write Reset XBARA_SEL26 field descriptions Field Description 15–14 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 13–8 Input (XBARA_INn) to be muxed to XBARA_OUT53 (refer to Functional Description section for input/ SEL53...
Page 505 Chapter 26 Inter-Peripheral Crossbar Switch A (XBARA) 26.4.29 Crossbar A Select Register 28 (XBARA_SEL28) Address: 4005_9000h base + 38h offset = 4005_9038h Read SEL57 SEL56 Write Reset XBARA_SEL28 field descriptions Field Description 15–14 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 13–8 Input (XBARA_INn) to be muxed to XBARA_OUT57 (refer to Functional Description section for input/ SEL57...
Page 506 Memory Map and Register Descriptions 26.4.31 Crossbar A Control Register 0 (XBARA_CTRL0) Use this register to configure edge detection, interrupt, and DMA features for the XBAR_OUT0 and XBAR_OUT1 outputs. The XBAR_CTRL registers are organized similarly to the XBAR_SEL registers, with control fields for two XBAR_OUT outputs in each register.
Page 507 Chapter 26 Inter-Peripheral Crossbar Switch A (XBARA) XBARA_CTRL0 field descriptions (continued) Field Description This bit enables the interrupt function on the corresponding XBAR_OUT1 output. When the interrupt is enabled, the output INT_REQ1 reflects the value STS1. When the interrupt is disabled, INT_REQ1 remains low.
Page 508 Memory Map and Register Descriptions XBARA_CTRL0 field descriptions (continued) Field Description Restriction: IEN0 and DEN0 should not both be set to 1. DMA disabled DMA enabled 26.4.32 Crossbar A Control Register 1 (XBARA_CTRL1) Use this register to configure edge detection, interrupt, and DMA features for the XBAR_OUT2 and XBAR_OUT3 outputs.
Page 509 Chapter 26 Inter-Peripheral Crossbar Switch A (XBARA) XBARA_CTRL1 field descriptions (continued) Field Description 11–10 Active edge for edge detection on XBAR_OUT3 EDGE3 This field selects which edges on XBAR_OUT3 cause STS3 to assert. STS3 never asserts STS3 asserts on rising edges of XBAR_OUT3 STS3 asserts on falling edges of XBAR_OUT3 STS3 asserts on rising and falling edges of XBAR_OUT3 Interrupt Enable for XBAR_OUT3...
Page 510 Functional Description XBARA_CTRL1 field descriptions (continued) Field Description This bit enables the interrupt function on the corresponding XBAR_OUT2 output. When the interrupt is enabled, the output INT_REQ2 reflects the value STS2. When the interrupt is disabled, INT_REQ2 remains low. The interrupt request is cleared by writing a 1 to STS2. Restriction: IEN2 and DEN2 should not both be set to 1.
Page 511: Interrupts And Dma Requests
Chapter 26 Inter-Peripheral Crossbar Switch A (XBARA) 26.6 Resets The XBAR module can be reset by only a hard reset, which forces all registers to their reset state. 26.7 Clocks All sequential functionality is controlled by the Bus Clock. 26.8 Interrupts and DMA Requests For each XBAR_OUT[*] output with XBAR_CTRL register support, DMA or interrupt functionality can be enabled by setting the corresponding XBAR_CTRL register bit DENn or IENn to 1.
Page 512 Interrupts and DMA Requests KV4x Reference Manual, Rev. 2, 02/2015 Preliminary Freescale Semiconductor, Inc.
Page 513: Chapter 27 Inter-Peripheral Crossbar Switch B (Xbarb)
Chapter 27 Inter-Peripheral Crossbar Switch B (XBARB) 27.1 chip-specific XBARB information 27.1.1 XBARB signal input assignment Table 27-1. XBARB signal input assignment XBARB Input Assigned Output XBARB_IN0 CMP0_OUT XBARB_IN1 CMP1_OUT XBARB_IN2 CMP2_OUT XBARB_IN3 CMP3_OUT XBARB_IN4 FTM0_CH_allTRIG XBARB_IN5 FTM0_INIT XBARB_IN6 FTM3_CH_allTRIG XBARB_IN7 FTM3_INIT XBARB_IN8...
Page 514 Introduction Table 27-1. XBARB signal input assignment (continued) XBARB Input Assigned Output XBARB_IN23 DMA ch7_done XBARB_IN24 PIT ch0 XBARB_IN25 PIT ch1 XBARB_IN26 PDB1_OUT XBARB_IN27 ADCB Scan complete 27.1.2 XBARB signal output assignment Table 27-2. XBARB signal output assignment XBARB Output Assigned Input XBARB_OUT0 AOI_IN0...
Page 515: Memory Map And Register Descriptions
Chapter 27 Inter-Peripheral Crossbar Switch B (XBARB) 27.3 Memory Map and Register Descriptions This section provides information about the XBARB instance of the inter-peripheral crossbar switch. Refer to the XBARA register details for information about that instance of the module. This XBAR module has only select registers.
Page 516 Memory Map and Register Descriptions XBARB_SEL0 field descriptions Field Description 15–13 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 12–8 Input (XBARB_INn) to be muxed to XBARB_OUT1 (refer to Functional Description section for input/output SEL1 assignment) 7–5...
Page 517 Chapter 27 Inter-Peripheral Crossbar Switch B (XBARB) XBARB_SEL2 field descriptions (continued) Field Description 12–8 Input (XBARB_INn) to be muxed to XBARB_OUT5 (refer to Functional Description section for input/output SEL5 assignment) 7–5 This field is reserved. Reserved This read-only field is reserved and always has the value 0. SEL4 Input (XBARB_INn) to be muxed to XBARB_OUT4 (refer to Functional Description section for input/output assignment)
Page 518 Memory Map and Register Descriptions XBARB_SEL4 field descriptions (continued) Field Description 7–5 This field is reserved. Reserved This read-only field is reserved and always has the value 0. SEL8 Input (XBARB_INn) to be muxed to XBARB_OUT8 (refer to Functional Description section for input/output assignment) 27.3.6 Crossbar B Select Register 5 (XBARB_SEL5) Address: 4005_A000h base + Ah offset = 4005_A00Ah...
Page 519 Chapter 27 Inter-Peripheral Crossbar Switch B (XBARB) XBARB_SEL6 field descriptions (continued) Field Description SEL12 Input (XBARB_INn) to be muxed to XBARB_OUT12 (refer to Functional Description section for input/ output assignment) 27.3.8 Crossbar B Select Register 7 (XBARB_SEL7) Address: 4005_A000h base + Eh offset = 4005_A00Eh Read SEL15 SEL14...
Page 520 Memory Map and Register Descriptions KV4x Reference Manual, Rev. 2, 02/2015 Preliminary Freescale Semiconductor, Inc.
Page 521 Chapter 28 Crossbar AND/OR/INVERT (AOI) Module 28.1 Chip-specific AOI information 28.1.1 AOI signal assignment The AOI block has 16 input signals that are connected directly to the 16 output signals of XBARB. The AOI has 4 output signals that are connected to XBARA inputs. Table 28-1.
Page 522 Introduction 28.2 Introduction The AND/OR/INVERT module (known simply as the AOI module) supports the generation of a configurable number of EVENT signals. Each output EVENTn is a configurable and/or/invert function of four associated AOI inputs: An, Bn, Cn, and Dn. This module is designed to be integrated in conjuction with one or more inter-peripheral crossbar switch (XBAR) modules.
Page 523 Chapter 28 Crossbar AND/OR/INVERT (AOI) Module Input A PT0_AC Input B PT0_BC Input C PT0_CC Input D PT0_DC PT1_AC PT1_BC PT1_CC PT1_DC Event PT2_AC PT2_BC PT2_CC PT2_DC PT3_AC PT3_BC PT3_CC PT3_DC Figure 28-1. Simplified AOI Block Diagram KV4x Reference Manual, Rev. 2, 02/2015 Preliminary Freescale Semiconductor, Inc.
Page 524: Modes Of Operation
External Signal Description 28.2.2 Features The major features of the AOI module are summarized below: • Highly programmable module for creating combinational boolean events for use as hardware triggers • Each channel has four event inputs and one output • Evaluates a combinational boolean expression as the sum of four products where each product term includes all four selected input sources available as true or complement values •...
Page 525 Chapter 28 Crossbar AND/OR/INVERT (AOI) Module The AOI module supports a specific number of event outputs. Each output EVENTn outputs a four-term AOI function of four binary inputs: An, Bn, Cn, and Dn. A pair of 16-bit registers configures this four-term AOI function: The two registers BFCRT01n and BFCRT23n define the configuration for the evaluation of the Boolean function defining EVENTn, where n is the event output channel number.
Page 526 Memory Map and Register Descriptions 28.4.1 Boolean Function Term 0 and 1 Configuration Register for EVENTn (AOI_BFCRT01n) Address: 4005_B000h base + 0h offset + (4d × i), where i=0d to 3d Read PT0_AC PT0_BC PT0_CC PT0_DC PT1_AC PT1_BC PT1_CC PT1_DC Write Reset AOI_BFCRT01n field descriptions...
Page 527 Chapter 28 Crossbar AND/OR/INVERT (AOI) Module AOI_BFCRT01n field descriptions (continued) Field Description Complement the A input in this product term Force the A input in this product term to a logical one 5–4 Product term 1, B input configuration PT1_BC This 2-bit field defines the Boolean evaluation associated with the selected input B in product term 1.
Page 528 Memory Map and Register Descriptions AOI_BFCRT23n field descriptions (continued) Field Description 13–12 Product term 2, B input configuration PT2_BC This 2-bit field defines the Boolean evaluation associated with the selected input B in product term 2. Force the B input in this product term to a logical zero Pass the B input in this product term Complement the B input in this product term Force the B input in this product term to a logical one...
Page 529: Functional Description
Chapter 28 Crossbar AND/OR/INVERT (AOI) Module AOI_BFCRT23n field descriptions (continued) Field Description Force the D input in this product term to a logical zero Pass the D input in this product term Complement the D input in this product term Force the D input in this product term to a logical one 28.5 Functional Description The AOI is a highly programmable module for creating combinational boolean outputs...
Page 530 Functional Description 4-output AOI A0-D0 Module A0-D0 EVENT0 A1-D1 EVENT1 Inter Peripheral Crossbar A2-D2 EVENT2 Switch A3-D3 EVENT3 Inter Peripheral Crossbar Switch Figure 28-12. Integration Example of AOI with two Inter-Peripheral Crossbar Switches 28.5.1 Configuration Examples for the Boolean Function Evaluation This section presents examples of the programming model configuration for simple boolean expressions.
Page 531 Chapter 28 Crossbar AND/OR/INVERT (AOI) Module | (0,An,~An,1) & (0,Bn,~Bn,1) & (0,Cn,~Cn,1) & (0,Dn,~Dn,1)// product term 2 | (0,An,~An,1) & (0,Bn,~Bn,1) & (0,Cn,~Cn,1) & (0,Dn,~Dn,1)// product term 3 where each selected input term in each product term can be configured to produce a logical 0 or 1 or pass the true or complement of the selected event input.
Page 532 Functional Description 28.5.2 AOI Timing Between Inputs and Outputs Each EVENTn output of the AOI module is a combination function of its four dedicated inputs An, Bn, Cn, and Dn. Propagation through the AOI and any associated inter- peripheral crossbar switch modules is intended to be single bus clock cycle. KV4x Reference Manual, Rev.
Page 533: Chapter 29 Oscillator (Osc)
Chapter 29 Oscillator (OSC) 29.1 Introduction The OSC module is a crystal oscillator. The module, in conjunction with an external crystal or resonator, generates a reference clock for the MCU. 29.2 Features and Modes Key features of the module are listed here. •...
Page 534: Block Diagram
Block Diagram 29.3 Block Diagram The OSC module uses a crystal or resonator to generate three filtered oscillator clock signals.Three clocks are output from OSC module: OSCCLK for MCU system, OSCERCLK for on-chip peripherals, and . The OSCCLK can only work in run mode. OSCERCLK and can work in low power modes.
Page 535: External Crystal / Resonator Connections
Chapter 29 Oscillator (OSC) Refer to signal multiplexing information for this MCU for more details. Table 29-1. OSC Signal Descriptions Signal Description EXTAL External clock/Oscillator input XTAL Oscillator output 29.5 External Crystal / Resonator Connections The connections for a crystal/resonator frequency reference are shown in the figures found here.
Page 536: External Clock Connections
External Clock Connections EXTAL XTAL Crystal or Resonator Figure 29-3. Crystal/Ceramic Resonator Connections - Connection 2 NOTE Connection 1 and Connection 2 should use internal capacitors as the load of the oscillator by configuring the CR[SCxP] bits. EXTAL XTAL Crystal or Resonator Figure 29-4.
Page 537: Osc Memory Map/Register Definition
Chapter 29 Oscillator (OSC) XTAL EXTAL Clock Input Figure 29-5. External Clock Connections 29.7 Memory Map/Register Definitions Some oscillator module register bits are typically incorporated into other peripherals such as MCG or SIM. 29.7.1 OSC Memory Map/Register Definition OSC memory map Absolute Width Section/...
Page 538 OSC Memory Map/Register Definition OSC_CR field descriptions Field Description External Reference Enable ERCLKEN Enables external reference clock (OSCERCLK). External reference clock is inactive. External reference clock is enabled. This field is reserved. Reserved This read-only field is reserved and always has the value 0. External Reference Stop Enable EREFSTEN Controls whether or not the external reference clock (OSCERCLK) remains enabled when MCU enters...
Page 539: Osc Module States
Chapter 29 Oscillator (OSC) 29.7.1.2 OSC_DIV (OSC_OSC_DIV) OSC CLock divider register. Address: 4006_5000h base + 2h offset = 4006_5002h Read ERPS Write Reset OSC_OSC_DIV field descriptions Field Description 7–6 ERCLK prescaler. These two bits are used to divide the ERCLK output. The un-divided ERCLK output is ERPS not affected by these two bits.
Page 540 Functional Description Oscillator OFF OSCCLK OSC_CLK_OUT = Static not requested OSCCLK requested OSCCLK requested && && Select OSC internal clock Select clock from EXTAL signal Start-Up External Clock Mode Oscillator ON, not yet stable Oscillator ON OSC_CLK_OUT = Static OSC_CLK_OUT = EXTAL CNT_DONE_4096 Stable Oscillator ON, Stable...
Page 541: Oscillator Startup
Chapter 29 Oscillator (OSC) 29.8.1.2 Oscillator startup The OSC enters startup state when it is configured to generate clocks (internally the OSC_EN transitions high) using the internal oscillator circuits by setting the external reference clock selection bit. In this state, the OSC module is enabled and oscillations are starting up, but have not yet stabilized.
Page 542: Low-Frequency, High-Gain Mode
Functional Description Table 29-6. Oscillator modes (continued) Mode Frequency Range High-frequency mode1, high-gain (3 MHz) up to f (8 MHz) osc_hi_1 osc_hi_1 High-frequency mode1, low-power High-frequency mode2, high-gain (8 MHz) up to f (32 MHz) osc_hi_2 osc_hi_2 High-frequency mode2, low-power NOTE For information about low power modes of operation used in this chip and their alignment with some OSC modes, see the...
Page 543: High-Frequency, High-Gain Mode
Chapter 29 Oscillator (OSC) 29.8.2.3 High-Frequency, High-Gain Mode In high-frequency, high-gain mode, the oscillator uses a simple inverter-style amplifier. The gain is set to achieve rail-to-rail oscillation amplitudes. This mode provides low pass frequency filtering as well as hysteresis for voltage filtering and converts the output to logic levels.
Page 544: Low Power Modes Operation
Low power modes operation 29.10 Low power modes operation When the MCU enters Stop modes, the OSC is functional depending on CR[ERCLKEN] and CR[EREFSETN] bit settings. If both these bits are set, the OSC is in operation. After waking up from Very Low Leakage Stop (VLLSx) modes, all OSC register bits are reset and initialization is required through software.
Page 545: Chapter 30 Multipurpose Clock Generator (Mcg)
Chapter 30 Multipurpose Clock Generator (MCG) 30.1 Introduction The multipurpose clock generator (MCG) module provides several clock source choices for the MCU. The module contains a frequency-locked loop (FLL) and a phase-locked loop (PLL). The FLL is controllable by either an internal or an external reference clock. The PLL is controllable by the external reference clock.
Page 546 Introduction • Voltage-controlled oscillator (VCO) • External reference clock is used as the PLL source. • Modulo VCO frequency divider • Phase/Frequency detector • Integrated loop filter • Can be used as a clock source for other on-chip peripherals. • Internal reference clock generator: •...
Page 547 Chapter 30 Multipurpose Clock Generator (MCG) • MCG Fixed Frequency Clock (MCGFFCLK) is provided as a clock source for other on-chip peripherals • MCG Internal Reference Clock (MCGIRCLK) is provided as a clock source for other on-chip peripherals This figure presents the block diagram of the MCG module. KV4x Reference Manual, Rev.
Page 548 Introduction Crystal Oscillator External Reference Clock CLKS OSCINIT0 PLLCLKEN0 MCG Crystal Oscillator Enable Detect EREFS0 IREFS PLLS HGO0 ATMS RANGE0 STOP IREFSTEN SELCLK Auto Trim Machine IRCLKEN MCGIRCLK SCTRIM Internal IRCS CLKS CLKS Reference SCFTRIM Slow Clock Clock IRCSCLK Generator Fast Clock FCTRIM n=0-7...
Page 549: Modes Of Operation
Chapter 30 Multipurpose Clock Generator (MCG) 30.1.2 Modes of Operation The MCG has the following modes of operation: FEI, FEE, FBI, FBE, PBE, PEE, BLPI, BLPE, and Stop. For details, see MCG modes of operation. 30.2 External Signal Description There are no MCG signals that connect off chip. 30.3 Memory Map/Register Definition This section includes the memory map and register definition.
Page 550 Memory Map/Register Definition 30.3.1 MCG Control 1 Register (MCG_C1) Address: 4006_4000h base + 0h offset = 4006_4000h Read CLKS FRDIV IREFS IRCLKEN IREFSTEN Write Reset MCG_C1 field descriptions Field Description 7–6 Clock Source Select CLKS Selects the clock source for MCGOUTCLK . Encoding 0 —...
Page 551 Chapter 30 Multipurpose Clock Generator (MCG) 30.3.2 MCG Control 2 Register (MCG_C2) Address: 4006_4000h base + 1h offset = 4006_4001h Read LOCRE0 FCFTRIM RANGE EREFS IRCS Write Reset MCG_C2 field descriptions Field Description Loss of Clock Reset Enable LOCRE0 Determines whether an interrupt or a reset request is made following a loss of OSC0 external reference clock.
Page 552 Memory Map/Register Definition MCG_C2 field descriptions (continued) Field Description Internal Reference Clock Select IRCS Selects between the fast or slow internal reference clock source. Slow internal reference clock selected. Fast internal reference clock selected. 30.3.3 MCG Control 3 Register (MCG_C3) Address: 4006_4000h base + 2h offset = 4006_4002h Read SCTRIM...
Page 553 Chapter 30 Multipurpose Clock Generator (MCG) 30.3.4 MCG Control 4 Register (MCG_C4) NOTE Reset values for DRST and DMX32 bits are 0. Address: 4006_4000h base + 3h offset = 4006_4003h Read DMX32 DRST_DRS FCTRIM SCFTRIM Write Reset * Notes: • x = Undefined at reset.
Page 554 Memory Map/Register Definition MCG_C4 field descriptions (continued) Field Description Encoding 1 — Mid range. Encoding 2 — Mid-high range. Encoding 3 — High range. 4–1 Fast Internal Reference Clock Trim Setting FCTRIM FCTRIM controls the fast internal reference clock frequency by controlling the fast internal reference clock period.
Page 555 Chapter 30 Multipurpose Clock Generator (MCG) MCG_C5 field descriptions (continued) Field Description Enables the PLL Clock during Normal Stop (In Low Power Stop mode, the PLL clock gets disabled even if PLLSTEN=1). All other power modes, PLLSTEN bit has no affect and does not enable the PLL Clock to run if it is written to 1.
Page 556 Memory Map/Register Definition MCG_C6 field descriptions (continued) Field Description No interrupt request is generated on loss of lock. Generate an interrupt request on loss of lock. PLL Select PLLS Controls whether the PLL or FLL output is selected as the MCG source when CLKS[1:0]=00. If the PLLS bit is cleared and PLLCLKEN 0 is not set, the PLL is disabled in all modes.
Page 557 Chapter 30 Multipurpose Clock Generator (MCG) 30.3.7 MCG Status Register (MCG_S) Address: 4006_4000h base + 6h offset = 4006_4006h Read LOLS0 LOCK0 PLLST IREFST CLKST OSCINIT0 IRCST Write Reset MCG_S field descriptions Field Description Loss of Lock Status LOLS0 This bit is a sticky bit indicating the lock status for the PLL. LOLS is set if after acquiring lock, the PLL output frequency has fallen outside the lock exit frequency tolerance, D .
Page 558 Memory Map/Register Definition MCG_S field descriptions (continued) Field Description 3–2 Clock Mode Status CLKST These bits indicate the current clock mode. The CLKST bits do not update immediately after a write to the CLKS bits due to internal synchronization between clock domains. Encoding 0 —...
Page 559 Chapter 30 Multipurpose Clock Generator (MCG) MCG_SC field descriptions (continued) Field Description Automatic Trim Machine Select ATMS Selects the IRCS clock for Auto Trim Test. 32 kHz Internal Reference Clock selected. 4 MHz Internal Reference Clock selected. Automatic Trim Machine Fail Flag ATMF Fail flag for the Automatic Trim Machine (ATM).
Page 560 Memory Map/Register Definition 30.3.9 MCG Auto Trim Compare Value High Register (MCG_ATCVH) Address: 4006_4000h base + Ah offset = 4006_400Ah Read ATCVH Write Reset MCG_ATCVH field descriptions Field Description ATCVH ATM Compare Value High Values are used by Auto Trim Machine to compare and adjust Internal Reference trim values during ATM SAR conversion.
Page 561: Functional Description
Chapter 30 Multipurpose Clock Generator (MCG) MCG_C8 field descriptions Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. PLL Loss of Lock Reset Enable LOLRE Determines if an interrupt or a reset request is made following a PLL loss of lock. Interrupt request is generated on a PLL loss of lock indication.
Page 562: Mcg Modes Of Operation
Functional description Reset BLPE BLPI Entered from any state when Returns to the state that was active before the MCU enters Stop mode Stop the MCU entered Stop mode, unless a reset occurs while in Stop mode. Figure 30-13. MCG mode state diagram NOTE •...
Page 563 Chapter 30 Multipurpose Clock Generator (MCG) Table 30-15. MCG modes of operation Mode Description FLL Engaged Internal FLL engaged internal (FEI) is the default mode of operation and is entered when all the following (FEI) condtions occur: • 00 is written to C1[CLKS]. •...
Page 564 Functional description Table 30-15. MCG modes of operation (continued) Mode Description In FBE mode, the MCGOUTCLK is derived from the external reference clock. The FLL is operational but its output is not used. This mode is useful to allow the FLL to acquire its target frequency while the MCGOUTCLK is driven from the external reference clock.
Page 565: Mcg Mode Switching
Chapter 30 Multipurpose Clock Generator (MCG) Table 30-15. MCG modes of operation (continued) Mode Description Stop Entered whenever the MCU enters a Stop state. The power modes are chip specific. For power mode assignments, see the chapter that describes how modules are configured and MCG behavior during Stop recovery.
Page 566: Low-Power Bit Usage
Functional description range within three clocks of the selected DCO clock. After switching to the new DCO (indicated by the updated C4[DRST_DRS] read bits), the FLL remains unlocked for several reference cycles. The FLL lock time is provided in the device data sheet as fll_acquire 30.4.2 Low-power bit usage C2[LP] is provided to allow the FLL or PLL to be disabled and thus conserve power...
Page 567: External Reference Clock
Chapter 30 Multipurpose Clock Generator (MCG) 30.4.4 External Reference Clock The MCG module can support an external reference clock in all modes. See the device datasheet for external reference frequency range. When C1[IREFS] is set, the external reference clock will not be used by the FLL or PLL. In these modes, the frequency can be equal to the maximum frequency the chip-level timing specifications will support.
Page 568: Mcg Auto Trim (Atm)
Functional description 30.4.7 MCG Auto TRIM (ATM) The MCG Auto Trim (ATM) is a MCG feature that when enabled, it configures the MCG hardware to automatically trim the MCG Internal Reference Clocks using an external clock as a reference. The selection between which MCG IRC clock gets tested and enabled is controlled by the ATC[ATMS] control bit (ATC[ATMS]=0 selects the 32 kHz IRC and ATC[ATMS]=1 selects the 4 MHz IRC).
Page 569: Initialization / Application Information
Chapter 30 Multipurpose Clock Generator (MCG) If the auto trim is being performed on the 4 MHz IRC, the calculated expected count value must be multiplied by 128 before storing it in the ATCV register. Therefore, the ATCV Expected Count Value for trimming the 4 MHz IRC is calculated using the following formula.
Page 570 Initialization / Application information • If entering FBE, clear C1[IREFS] to switch to the external reference and change C1[CLKS] to 2'b10 so that the external reference clock is selected as the system clock source. The C1[FRDIV] bits should also be set appropriately here according to the external reference frequency to keep the FLL reference clock in the range of 31.25 kHz to 39.0625 kHz.
Page 571: Using A 32.768 Khz Reference
Chapter 30 Multipurpose Clock Generator (MCG) • When using a 32.768 kHz external reference, if the maximum mid-range DCO frequency that can be achieved with a 32.768 kHz reference is desired, set C4[DRST_DRS] bits to 2'b01 and set C4[DMX32] bit to 1. The resulting DCO output (MCGOUTCLK) frequency with the new multiplier of 1464 will be 48 MHz.
Page 572 Initialization / Application information If C4[DRST_DRS] bits are set to 2'b01, the multiplication factor is doubled to 1280, and the resulting DCO output frequency is 41.94 MHz at mid-low-range. If C4[DRST_DRS] bits are set to 2'b10, the multiplication factor is set to 1920, and the resulting DCO output frequency is 62.91 MHz at mid high-range.
Page 573 Chapter 30 Multipurpose Clock Generator (MCG) Table 30-16. MCGOUTCLK Frequency Calculation Options (continued) Clock Mode Note MCGOUTCLK FBI (FLL bypassed internal) MCGIRCLK Selectable between slow and fast PEE (PLL engaged external) (OSCCLK / PLL_R) × M / 2 OSCCLK / PLL_R must be in the range of 8 –...
Page 574 Initialization / Application information • C1[FRDIV] set to 3'b100, or divide-by-512 because 8 MHz / 512 = 31.25 kHz which is in the 31.25 kHz to 39.0625 kHz range required by the FLL • C1[IREFS] cleared to 0, selecting the external reference clock and enabling the external oscillator.
Page 575 Chapter 30 Multipurpose Clock Generator (MCG) d. PBE: Loop until S[PLLST] is set, indicating that the current source for the PLLS clock is the PLL. e. PBE: Then loop until S[LOCK0] is set, indicating that the PLL has acquired lock. 4.
Page 576 Initialization / Application information START IN FEI MODE C6 = 0x4E C2 = 0x2C BLPE MODE ? (S[LP]=1) C1 = 0x40 C2 = 0x2C (S[LP]=0) CHECK S[OSCINIT0] = 1? CHECK S[PLLST] = 1? CHECK S[IREFST] = 0? CHECK S[LOCK0] = 1? CHECK S[CLKST] = %10? C1 = 0x20...
Page 577: Example 2: Moving From Pee To Blpi Mode: Mcgoutclk Frequency =32 Khz
Chapter 30 Multipurpose Clock Generator (MCG) 30.5.3.2 Example 2: Moving from PEE to BLPI mode: MCGOUTCLK frequency =32 kHz In this example, the MCG will move through the proper operational modes from PEE mode with a 16 MHz crystal configured for a 120 MHz MCGOUTCLK frequency (see previous example) to BLPI mode with a 32 kHz MCGOUTCLK frequency.
Page 578 Initialization / Application information • C1[IREFS] set to 1 to select the internal reference clock as the reference clock source. • C1[FRDIV] remain unchanged because the reference divider does not affect the internal reference. b. Loop until S[IREFST] is 1, indicating the internal reference clock has been selected as the reference clock source.
Page 579 Chapter 30 Multipurpose Clock Generator (MCG) START IN PEE MODE C1 = 0x40 CHECK S[PLLST] = 0? CHECK S[CLKST] = %10 ? C1 = 0x64 ENTER CHECK BLPE MODE ? S[IREFST] = 0? C2 = 0x2E (C2[LP] = 1) CHECK S[CLKST] = %01? C6 = 0x00 C2 = 0x22...
Page 580 Initialization / Application information KV4x Reference Manual, Rev. 2, 02/2015 Preliminary Freescale Semiconductor, Inc.
Page 581: Chapter 31 Flash Memory Controller (Fmc)
Chapter 31 Flash Memory Controller (FMC) 31.1 Introduction The Flash Memory Controller (FMC) is a memory acceleration unit that provides: • an interface between the device and the nonvolatile memory. • buffers that can accelerate flash memory transfers. 31.1.1 Overview The Flash Memory Controller manages the interface between the device and the flash memory.
Page 582: Modes Of Operation
Modes of operation • For bank 0: Read accesses to consecutive 32-bit spaces in memory return the second, third, and fourth read data with no wait states. The memory returns 128 bits via the 32-bit bus access. • Crossbar master access protection for setting no access, read-only access, write- only access, or read/write access for each crossbar master.
Page 583 Chapter 31 Flash Memory Controller (FMC) Table 31-2. FMC register access Registers Read access Write access Mode Length Mode Length Control registers: Supervisor (privileged) 32 bits Supervisor (privileged) 32 bits PFAPR, PFB0CR, mode or user mode mode only PFB1CR Cache registers Supervisor (privileged) 32 bits Supervisor (privileged)
Page 584 Memory map and register descriptions FMC memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4001_F000 Flash Access Protection Register (FMC_PFAPR) 00F0_00FFh 31.4.1/586 4001_F004 Flash Bank 0 Control Register (FMC_PFB0CR) 3004_001Fh 31.4.2/588 4001_F008 Reserved (FMC_Reserved) 3000_0000h 31.4.3/590 4001_F100...
Page 585 Chapter 31 Flash Memory Controller (FMC) FMC memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) Cache Data Storage (uppermost word) 31.4.16/ 4001_F240 0000_0000h (FMC_DATAW2S0UM) Cache Data Storage (mid-upper word) 31.4.17/ 4001_F244 0000_0000h (FMC_DATAW2S0MU) Cache Data Storage (mid-lower word) 31.4.18/...
Page 586 Memory map and register descriptions 31.4.1 Flash Access Protection Register (FMC_PFAPR) Address: 4001_F000h base + 0h offset = 4001_F000h Reserved Reserved Reset Reserved Reserved Reserved M2AP[1:0] M1AP[1:0] M0AP[1:0] Reset FMC_PFAPR field descriptions Field Description 31–24 This field is reserved. Reserved 23–20 This field is reserved.
Page 587 Chapter 31 Flash Memory Controller (FMC) FMC_PFAPR field descriptions (continued) Field Description Master 0 Prefetch Disable M0PFD These bits control whether prefetching is enabled, based on the logical number of the requesting crossbar switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits. Prefetching for this master is enabled.
Page 588 Memory map and register descriptions 31.4.2 Flash Bank 0 Control Register (FMC_PFB0CR) Address: 4001_F000h base + 4h offset = 4001_F004h B0RWSC[3:0] B0MW[1:0] CLCK_WAY[3:0] S_B_ CINV_WAY[3:0] Reset CRC[2:0] Reset FMC_PFB0CR field descriptions Field Description 31–28 Bank 0 Read Wait State Control B0RWSC[3:0] This read-only field defines the number of wait states required to access the bank 0 flash memory.
Page 589 Chapter 31 Flash Memory Controller (FMC) FMC_PFB0CR field descriptions (continued) Field Description These bits determine if the given cache way is to be invalidated (cleared). When a bit within this field is written, the corresponding cache way is immediately invalidated: the way's tag, data, and valid contents are cleared.
Page 590 Memory map and register descriptions FMC_PFB0CR field descriptions (continued) Field Description Do not cache instruction fetches. Cache instruction fetches. Bank 0 Data Prefetch Enable B0DPE This bit controls whether prefetches (or speculative accesses) are initiated in response to data references. Do not prefetch in response to data references.
Page 591 Chapter 31 Flash Memory Controller (FMC) FMC_Reserved field descriptions (continued) Field Description 18–17 This field is reserved. Reserved This field is reserved. Reserved This read-only field is reserved and always has the value 0. 15–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0.
Page 592 Memory map and register descriptions 31.4.5 Cache Tag Storage (FMC_TAGVDW1Sn) The 128-entry cache is a 4-way, set-associative cache with 2 sets. The ways are numbered 0-3 and the sets are numbered 0-1. In TAGVDWxSy, x denotes the way, and y denotes the set.
Page 593 Chapter 31 Flash Memory Controller (FMC) 31.4.6 Cache Tag Storage (FMC_TAGVDW2Sn) The 128-entry cache is a 4-way, set-associative cache with 2 sets. The ways are numbered 0-3 and the sets are numbered 0-1. In TAGVDWxSy, x denotes the way, and y denotes the set.
Page 594 Memory map and register descriptions 31.4.7 Cache Tag Storage (FMC_TAGVDW3Sn) The 128-entry cache is a 4-way, set-associative cache with 2 sets. The ways are numbered 0-3 and the sets are numbered 0-1. In TAGVDWxSy, x denotes the way, and y denotes the set.
Page 595 Chapter 31 Flash Memory Controller (FMC) 31.4.8 Cache Data Storage (uppermost word) (FMC_DATAW0SnUM) The cache of sixteen 128-bit entries is a 4-way, set-associative cache with 2 sets. The ways are numbered 0-3 and the sets are numbered 0-1. In DATAWxSyUM, DATAWxSyMU, DATAWxSyML, and DATAWxSyLM, x denotes the way, y denotes the set, and the final two letters identify the word: UM (uppermost), MU (mid-upper), ML (mid-lower), and LM (lowermost).
Page 596 Memory map and register descriptions 31.4.10 Cache Data Storage (mid-lower word) (FMC_DATAW0SnML) The cache of sixteen 128-bit entries is a 4-way, set-associative cache with 2 sets. The ways are numbered 0-3 and the sets are numbered 0-1. In DATAWxSyUM, DATAWxSyMU, DATAWxSyML, and DATAWxSyLM, x denotes the way, y denotes the set, and the final two letters identify the word: UM (uppermost), MU (mid-upper), ML (mid-lower), and LM (lowermost).
Page 597 Chapter 31 Flash Memory Controller (FMC) 31.4.12 Cache Data Storage (uppermost word) (FMC_DATAW1SnUM) The cache of sixteen 128-bit entries is a 4-way, set-associative cache with 2 sets. The ways are numbered 0-3 and the sets are numbered 0-1. In DATAWxSyUM, DATAWxSyMU, DATAWxSyML, and DATAWxSyLM, x denotes the way, y denotes the set, and the final two letters identify the word: UM (uppermost), MU (mid-upper), ML (mid-lower), and LM (lowermost).
Page 598 Memory map and register descriptions 31.4.14 Cache Data Storage (mid-lower word) (FMC_DATAW1SnML) The cache of sixteen 128-bit entries is a 4-way, set-associative cache with 2 sets. The ways are numbered 0-3 and the sets are numbered 0-1. In DATAWxSyUM, DATAWxSyMU, DATAWxSyML, and DATAWxSyLM, x denotes the way, y denotes the set, and the final two letters identify the word: UM (uppermost), MU (mid-upper), ML (mid-lower), and LM (lowermost).
Page 599 Chapter 31 Flash Memory Controller (FMC) 31.4.16 Cache Data Storage (uppermost word) (FMC_DATAW2SnUM) The cache of sixteen 128-bit entries is a 4-way, set-associative cache with 2 sets. The ways are numbered 0-3 and the sets are numbered 0-1. In DATAWxSyUM, DATAWxSyMU, DATAWxSyML, and DATAWxSyLM, x denotes the way, y denotes the set, and the final two letters identify the word: UM (uppermost), MU (mid-upper), ML (mid-lower), and LM (lowermost).
Page 600 Memory map and register descriptions 31.4.18 Cache Data Storage (mid-lower word) (FMC_DATAW2SnML) The cache of sixteen 128-bit entries is a 4-way, set-associative cache with 2 sets. The ways are numbered 0-3 and the sets are numbered 0-1. In DATAWxSyUM, DATAWxSyMU, DATAWxSyML, and DATAWxSyLM, x denotes the way, y denotes the set, and the final two letters identify the word: UM (uppermost), MU (mid-upper), ML (mid-lower), and LM (lowermost).
Page 601 Chapter 31 Flash Memory Controller (FMC) 31.4.20 Cache Data Storage (uppermost word) (FMC_DATAW3SnUM) The cache of sixteen 128-bit entries is a 4-way, set-associative cache with 2 sets. The ways are numbered 0-3 and the sets are numbered 0-1. In DATAWxSyUM, DATAWxSyMU, DATAWxSyML, and DATAWxSyLM, x denotes the way, y denotes the set, and the final two letters identify the word: UM (uppermost), MU (mid-upper), ML (mid-lower), and LM (lowermost).
Page 602 Memory map and register descriptions 31.4.22 Cache Data Storage (mid-lower word) (FMC_DATAW3SnML) The cache of sixteen 128-bit entries is a 4-way, set-associative cache with 2 sets. The ways are numbered 0-3 and the sets are numbered 0-1 . In DATAWxSyUM, DATAWxSyMU, DATAWxSyML, and DATAWxSyLM, x denotes the way, y denotes the set, and the final two letters identify the word: UM (uppermost), MU (mid-upper), ML (mid-lower), and LM (lowermost).
Page 603: Functional Description
Chapter 31 Flash Memory Controller (FMC) 31.5 Functional description The FMC is a flash acceleration unit with flexible buffers for user configuration. Besides managing the interface between the device and the flash memory, the FMC can be used to restrict access from crossbar switch masters and customize the cache and buffers to provide single-cycle system-clock data-access times.
Page 604: Speculative Reads
Functional description As an application example: if both instruction fetches and data references are accessing flash memory, then control is available to send instruction fetches, data references, or both to the cache or the single-entry buffer. Likewise, speculation can be enabled or disabled for either type of access.
Page 605: Initialization And Application Information
Chapter 31 Flash Memory Controller (FMC) 31.6 Initialization and application information The FMC does not require user initialization. Flash acceleration features are enabled by default. The FMC has no visibility into flash memory erase and program cycles because the Flash Memory module manages them directly.
Page 606 Initialization and application information KV4x Reference Manual, Rev. 2, 02/2015 Preliminary Freescale Semiconductor, Inc.
Page 607: Chapter 32 Flash Memory Module (Ftfa)
Chapter 32 Flash Memory Module (FTFA) 32.1 Introduction The flash memory module includes the following accessible memory regions: • Program flash memory for vector space and code store Flash memory is ideal for single-supply applications, permitting in-the-field erase and reprogramming operations without the need for any external high voltage power sources. The flash memory module includes a memory controller that executes commands to modify flash memory contents.
Page 608: Program Flash Memory Features
Introduction 32.1.1 Features The flash memory module includes the following features. NOTE See the device's Chip Configuration details for the exact amount of flash memory available on your device. 32.1.1.1 Program Flash Memory Features • Sector size of 4 KB •...
Page 609 Chapter 32 Flash Memory Module (FTFA) Interrupt Program flash Status Register access registers Memory controller Control registers To MCU's flash controller Figure 32-1. Flash Block Diagram 32.1.3 Glossary Command write sequence — A series of MCU writes to the flash FCCOB register group that initiates and controls the execution of flash algorithms that are built into the flash memory module.
Page 610: Memory Map And Registers
External Signal Description NVM Normal Mode — An NVM mode that provides basic user access to flash memory module resources. The CPU or other bus masters initiate flash program and erase operations (or other flash commands) using writes to the FCCOB register group in the flash memory module.
Page 611: Flash Configuration Field Description
Chapter 32 Flash Memory Module (FTFA) 32.3.1 Flash Configuration Field Description The program flash memory contains a 16-byte flash configuration field that stores default protection settings (loaded on reset) and security information that allows the MCU to restrict access to the flash memory module. Flash Configuration Field Byte Size (Bytes) Field Description...
Page 612: Program Once Field
Memory Map and Registers Address Range Size (Bytes) Field Description 0xAC – 0xAF Program Once XACCL-2 Field (index = 0x11) 0xB0 – 0xB3 Program Once SACCH-1 Field (index = 0x12) 0xB4 – 0xB7 Program Once SACCL-1 Field (index = 0x12) 0xB8 –...
Page 613 Chapter 32 Flash Memory Module (FTFA) FTFA memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 32.3.3.1/ 4002_0000 Flash Status Register (FTFA_FSTAT) 32.3.3.2/ 4002_0001 Flash Configuration Register (FTFA_FCNFG) 32.3.3.3/ 4002_0002 Flash Security Register (FTFA_FSEC) Undefined 32.3.3.4/ 4002_0003...
Page 614 Memory Map and Registers FTFA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 32.3.3.7/ 4002_001A Execute-only Access Registers (FTFA_XACCH1) Undefined 32.3.3.7/ 4002_001B Execute-only Access Registers (FTFA_XACCH0) Undefined 32.3.3.7/ 4002_001C Execute-only Access Registers (FTFA_XACCL3) Undefined 32.3.3.7/ 4002_001D Execute-only Access Registers (FTFA_XACCL2)
Page 615 Chapter 32 Flash Memory Module (FTFA) any more commands until the flag is cleared (by writing a one to it). Address: 4002_0000h base + 0h offset = 4002_0000h Read CCIF RDCOLERR ACCERR FPVIOL MGSTAT0 Write Reset FTFA_FSTAT field descriptions Field Description Command Complete Interrupt Flag CCIF...
Page 616 Memory Map and Registers FTFA_FSTAT field descriptions (continued) Field Description The MGSTAT0 status flag is set if an error is detected during execution of a flash command or during the flash reset sequence. As a status flag, this field cannot (and need not) be cleared by the user like the other error flags in this register.
Page 617 Chapter 32 Flash Memory Module (FTFA) FTFA_FCNFG field descriptions (continued) Field Description No request or request complete Request to: 1. run the Erase All Blocks command, 2. verify the erased state, 3. program the security byte in the Flash Configuration Field to the unsecure state, and 4.
Page 618 Memory Map and Registers FTFA_FSEC field descriptions (continued) Field Description Backdoor key access disabled Backdoor key access disabled (preferred KEYEN state to disable backdoor key access) Backdoor key access enabled Backdoor key access disabled 5–4 Mass Erase Enable MEEN Enables and disables mass erase capability of the flash memory module. When SEC is set to unsecure, the MEEN setting does not matter.
Page 619 Chapter 32 Flash Memory Module (FTFA) During the reset sequence, the register is loaded from the flash nonvolatile option byte in the Flash Configuration Field located in program flash memory. The flash basis for the values is signified by X in the reset value. However, the register is written to 0xFF if the contents of the flash nonvolatile option byte are 0x00.
Page 620 Memory Map and Registers FTFA_FCCOBn field descriptions (continued) Field Description The following table shows a generic flash command format. The first FCCOB register, FCCOB0, always contains the command code. This 8-bit value defines the command to be executed. The command code is followed by the parameters required for this specific flash command, typically an address and/or data values.
Page 621 Chapter 32 Flash Memory Module (FTFA) KB of program flash memory or less, FPROT1 is not used. For configurations with 8 KB of program flash memory, FPROT2 is not used. The bitfields are defined in each register as follows: Program flash protection register Program flash protection bits FPROT0 PROT[31:24]...
Page 622 Memory Map and Registers FTFA_FPROTn field descriptions (continued) Field Description Trying to alter data in any protected area in the program flash memory results in a protection violation error and sets the FSTAT[FPVIOL] bit. A full block erase of a program flash block is not possible if it contains any protected region.
Page 623 Chapter 32 Flash Memory Module (FTFA) Use the Program Once command to program the execute-only access control fields that are loaded during the reset sequence. Address: 4002_0000h base + 18h offset + (1d × i), where i=0d to 7d Read Write Reset * Notes:...
Page 624 Memory Map and Registers Supervisor-only access register Program Flash IFR address A Program Flash IFR address B SACCH2 0xB1 0xB9 SACCH3 0xB0 0xB8 SACCL0 0xB7 0xBF SACCL1 0xB6 0xBE SACCL2 0xB5 0xBD SACCL3 0xB4 0xBC Use the Program Once command to program the supervisor-only access control fields that are loaded during the reset sequence.
Page 625 Chapter 32 Flash Memory Module (FTFA) • x = Undefined at reset. FTFA_FACSS field descriptions Field Description SGSIZE Segment Size The segment size is a fixed value based on the available program flash size divided by NUMSG. Program Flash Size Segment Size Segment Size Encoding 64 KBytes...
Page 626: Functional Description
Functional Description 32.4 Functional Description The information found here describes functional details of the flash memory module. 32.4.1 Flash Protection Individual regions within the flash memory can be protected from program and erase operations. Protection is controlled by the following registers: •...
Page 627: Flash Access Protection
Chapter 32 Flash Memory Module (FTFA) 32.4.2 Flash Access Protection Individual segments within the program flash memory can be designated for restricted access. Specific flash commands (Program Check, Program Longword, Erase Flash Sector) monitor FXACC contents to protect flash memory but the FSACC contents do not impact flash command operation.
Page 628 Functional Description Program flash 0x0_0000 Program flash size / 64 SACCL3[SA0] Program flash size / 64 SACCL3[SA1] Program flash size / 64 SACCL3[SA2] Program flash size / 64 SACCL3[SA3] Program flash size / 64 SACCL3[SA4] Program flash size / 64 SACCL0[SA31] Program flash size / 64 SACCH3[SA32]...
Page 629: Flash Operation In Low-Power Modes
Chapter 32 Flash Memory Module (FTFA) 32.4.4 Flash Operation in Low-Power Modes 32.4.4.1 Wait Mode When the MCU enters wait mode, the flash memory module is not affected. The flash memory module can recover the MCU from wait via the command complete interrupt (see Interrupts).
Page 630: Flash Program And Erase
Functional Description • Reading from program flash memory space while a flash command is active (CCIF=0). 32.4.7 Flash Program and Erase All flash functions except read require the user to setup and launch a flash command through a series of peripheral bus writes. The user cannot initiate any further flash commands until notified that the current command has completed.
Page 631: Load The Fccob Registers
Chapter 32 Flash Memory Module (FTFA) 32.4.8.1.1 Load the FCCOB Registers The user must load the FCCOB registers with all parameters required by the desired flash command. The individual registers that make up the FCCOB data set can be written in any order.
Page 632: Flash Commands
Functional Description 4. The flash memory module sets FSTAT[CCIF] signifying that the command has completed. The flow for a generic command write sequence is illustrated in the following figure. START Read: FSTAT register FCCOB Availability Check CCIF Previous command complete? = ‘1’? Results from previous command Access Error and...
Page 633: Margin Read Commands
Chapter 32 Flash Memory Module (FTFA) FCMD Command Program flash Function 0x02 Program Check × Tests previously-programmed locations at margin read levels. 0x03 Read Resource IFR, ID Read 4 bytes from program flash IFR or version ID. 0x06 Program Longword ×...
Page 634: Flash Command Description
Functional Description Erased ('1') and programmed ('0') bit states can degrade due to elapsed time and data cycling (number of times a bit is erased and re-programmed). The lifetime of the erased states is relative to the last erase operation. The lifetime of the programmed states is measured from the last program time.
Page 635: Read 1S Section Command
Chapter 32 Flash Memory Module (FTFA) Do not attempt to read a flash block while the flash memory module is running a command (FSTAT[CCIF] = 0) on that same block. The flash memory module may return invalid data to the MCU with the collision error flag (FSTAT[RDCOLERR]) set. CAUTION Flash data must be in the erased state before being programmed.
Page 636: Program Check Command
Functional Description Table 32-47. Read 1s Section Command Error Handling Error condition Error bit Command not available in current mode/security FSTAT[ACCERR] An invalid margin code is supplied. FSTAT[ACCERR] An invalid flash address is supplied. FSTAT[ACCERR] Flash address is not double-phrase aligned. FSTAT[ACCERR] The requested section crosses a Flash block boundary.
Page 637: Read Resource Command
Chapter 32 Flash Memory Module (FTFA) • Byte 2 data is programmed to byte address start+0b01, • Byte 1 data is programmed to byte address start+0b10, • Byte 0 data is programmed to byte address start+0b11. NOTE See the description of margin reads, Margin Read Commands Table 32-49.
Page 638: Program Longword Command
Functional Description Table 32-51. Read Resource Command FCCOB Requirements (continued) FCCOB Number FCCOB Contents [7:0] Read Data [7:0] User-provided values Resource Select Code (see Table 32-52) 1. Must be longword aligned (Flash address [1:0] = 00). Table 32-52. Read Resource Select Codes Resource Description Resource Size...
Page 639 Chapter 32 Flash Memory Module (FTFA) Table 32-54. Program Longword Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0x06 (PGM4) Flash address [23:16] Flash address [15:8] Flash address [7:0] Byte 0 program value Byte 1 program value Byte 2 program value Byte 3 program value 1.
Page 640: Erase Flash Sector Command
Functional Description 32.4.10.5 Erase Flash Sector Command The Erase Flash Sector operation erases all addresses in a flash sector. Table 32-56. Erase Flash Sector Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0x09 (ERSSCR) Flash address [23:16] in the flash sector to be erased Flash address [15:8] in the flash sector to be erased Flash address [7:0] in the flash sector to be erased...
Page 641: Resuming A Suspended Erase Flash Sector Operation
Chapter 32 Flash Memory Module (FTFA) If an Erase Flash Sector operation effectively completes before the flash memory module detects that a suspend request has been made, the flash memory module clears the ERSSUSP bit prior to setting CCIF. When an Erase Flash Sector operation has been successfully suspended, the flash memory module sets CCIF and leaves the ERSSUSP bit set.
Page 642 Functional Description Enter with CCIF = 1 Command Initiation ERSSCR Command (Write FCCOB) Memory Controller Command Processing Launch/Resume Command (Clear CCIF) Resume ERSSCR SUSPACK=1 Next Command CCIF = 1? (Write FCCOB) Restore Erase Algo Start Clear SUSPACK = 0 Interrupt? Execute DONE? Request Suspend...
Page 643: Read 1S All Blocks Command
Chapter 32 Flash Memory Module (FTFA) 32.4.10.6 Read 1s All Blocks Command The Read 1s All Blocks command checks if the program flash blocks have been erased to the specified read margin level, if applicable, and releases security if the readout passes, i.e.
Page 644: Read Once Command
Functional Description 32.4.10.7 Read Once Command The Read Once command provides read access to special 96-byte fields located in the program flash 0 IFR (see Program Flash IFR Map Program Once Field). Access to the Program Once ID field is via 16 records (index values 0x00 - 0x0F), each 4 bytes long.
Page 645: Program Once Command
Chapter 32 Flash Memory Module (FTFA) 32.4.10.8 Program Once Command The Program Once command enables programming to special 96-byte fields in the program flash 0 IFR (see Program Flash IFR Map Program Once Field). Access to the Program Once ID field is via 16 records (index values 0x00 - 0x0F), each 4 bytes long.
Page 646: Erase All Blocks Command
Functional Description Table 32-64. Program Once Command Error Handling (continued) Error Condition Error Bit Any errors have been encountered during the verify operation FSTAT[MGSTAT0] 1. If a Program Once record is initially programmed to 0xFFFF_FFFF (0xFFFF_FFFF_FFFF_FFFF for index 0x10 - 0x13), the Program Once command is allowed to execute again on that same record.
Page 647: Triggering An Erase All External To The Flash Memory Module
Chapter 32 Flash Memory Module (FTFA) 1. User margin read may be run using the Read 1s All Blocks command to verify all bits are erased. 32.4.10.9.1 Triggering an Erase All External to the Flash Memory Module The functionality of the Erase All BlocksErase All Blocks Unsecure command is also available in an uncommanded fashion outside of the flash memory.
Page 648 Functional Description Table 32-67. Verify Backdoor Access Key Command FCCOB Requirements (continued) FCCOB Number FCCOB Contents [7:0] Flash Configuration Field Offset Address Key Byte 7 0x0_0004 After clearing CCIF to launch the Verify Backdoor Access Key command, the flash memory module checks the FSEC[KEYEN] bits to verify that this command is enabled. If not enabled, the flash memory module sets the FSTAT[ACCERR] bit and terminates.
Page 649: Changing The Security State
Chapter 32 Flash Memory Module (FTFA) Flash security features are discussed further in AN4507: Using the Kinetis Security and Flash Protection Features . Note that not all features described in the application note are available on this device. Table 32-69. FSEC register fields FSEC field Description KEYEN...
Page 650: Reset Sequence
Functional Description 1. Follow the command sequence for the Verify Backdoor Access Key command as explained in Verify Backdoor Access Key Command 2. If the Verify Backdoor Access Key command is successful, the chip is unsecured and the FSEC[SEC] bits are forced to the unsecure state An illegal key provided to the Verify Backdoor Access Key command prohibits further use of the Verify Backdoor Access Key command.
Page 651: Chapter 33 Cyclic Redundancy Check (Crc)
Chapter 33 Cyclic redundancy check (CRC) 33.1 Introduction The cyclic redundancy check (CRC) module generates 16/32-bit CRC code for error detection. The CRC module provides a programmable polynomial, WAS, and other parameters required to implement a 16-bit or 32-bit CRC standard. The 16/32-bit code is calculated for 32 bits of data at a time.
Page 652: Modes Of Operation
Memory map and register descriptions FXOR TOTR CRC Data Register [31:24][ CRC Data Register Seed 23:16] Reverse [31:24] [15:8] Logic Reverse [23:16] CRC Data [7:0] [15:8] Logic Logic [7:0] Checksum CRC Engine CRC Polynomial Register Data [31:24] [23:16] Combine Polynomial Logic [15:8] [7:0]...
Page 653 Chapter 33 Cyclic redundancy check (CRC) 33.2.1 CRC Data register (CRC_DATA) The CRC Data register contains the value of the seed, data, and checksum. When CTRL[WAS] is set, any write to the data register is regarded as the seed value. When CTRL[WAS] is cleared, any write to the data register is regarded as data for general CRC computation.
Page 654 Memory map and register descriptions 33.2.2 CRC Polynomial register (CRC_GPOLY) This register contains the value of the polynomial for the CRC calculation. The HIGH field contains the upper 16 bits of the CRC polynomial, which are used only in 32-bit CRC mode.
Page 655: Functional Description
Chapter 33 Cyclic redundancy check (CRC) CRC_CTRL field descriptions Field Description 31–30 Type Of Transpose For Writes Defines the transpose configuration of the data written to the CRC data register. See the description of the transpose feature for the available transpose options. No transposition.
Page 656: Crc Initialization/Reinitialization
Functional description 33.3.1 CRC initialization/reinitialization To enable the CRC calculation, the user must program CRC_CTRL[WAS], CRC_GPOLY,necessary parameters for transposition and CRC result inversion in the applicable registers. Asserting CRC_CTRL[WAS] enables the programming of the seed value into the CRC_DATA register. After a completed CRC calculation, the module can be reinitialized for a new CRC computation by reasserting CRC_CTRL[WAS] and programming a new, or previously used, seed value.
Page 657: Transpose Feature
Chapter 33 Cyclic redundancy check (CRC) 33.3.2.2 32-bit CRC To compute a 32-bit CRC: 1. Set CRC_CTRL[TCRC] to enable 32-bit CRC mode. 2. Program the transpose and complement options in the CTRL register as required for the CRC calculation. See Transpose feature CRC result complement for details.
Page 658 Functional description No transposition occurs. 2. CTRL[TOT] or CTRL[TOTR] is 01 Bits in a byte are transposed, while bytes are not transposed. reg[31:0] becomes {reg[24:31], reg[16:23], reg[8:15], reg[0:7]} Figure 33-5. Transpose type 01 3. CTRL[TOT] or CTRL[TOTR] is 10. Both bits in bytes and bytes are transposed. reg[31:0] becomes = {reg[0:7], reg[8:15],reg[16:23], reg[24:31]} Figure 33-6.
Page 659: Crc Result Complement
Chapter 33 Cyclic redundancy check (CRC) Figure 33-7. Transpose type 11 NOTE For 8-bit and 16-bit write accesses to the CRC data register, the data is transposed with zeros on the unused byte or bytes (taking 32 bits as a whole), but the CRC is calculated on the valid byte(s) only.
Page 660 Functional description KV4x Reference Manual, Rev. 2, 02/2015 Preliminary Freescale Semiconductor, Inc.
Page 661 Chapter 34 12-bit Cyclic Analog-to-Digital Converter (ADC) 34.1 Chip-specific Cyclic ADC information 34.1.1 Cyclic ADC Instantiation It is a dual ADC. The signals of its first ADC are labeled A, as in ANA, ADCA, VREFLA, and VREFHA. The signals of its second ADC are labeled B, as in ANB, ADCB, VREFLB, and VREFHB.
Page 662 Introduction 34.1.3 Cyclic ADC and eFlexPWM Connections Within the chip, the cyclic ADC has internal connections for eFlexPWM control. Table 34-1. Cyclic ADC and eFlexPWM Connections Cyclic ADC Outputs eFlexPWM Inputs an0_pwm PWMA0_EXTB an1_pwm PWMA1_EXTB an2_pwm PWMA2_EXTB an3_pwm PWMA3_EXTB 34.1.4 ADC in low power mode The ADC can be configured to be active in low power mode like STOP/VLPS mode.
Page 663: Zero Crossing
Chapter 34 12-bit Cyclic Analog-to-Digital Converter (ADC) • 12-bit resolution • Designed for maximum ADC clock frequency of 25 MHz with 40 ns period • Sampling rate up to 8.83 million samples per second • Single conversion time of 8.5 ADC clock cycles (8.5 × 40 ns =340 ns) •...
Page 664: Block Diagram
Signal Descriptions 34.2.3 Block Diagram The following figure illustrates the dual ADC configuration. VREFH Voltage ANA0 Reference ANA1 Circuit ANA2 VREFL ANA3 ANA4 ANA5 ANA6 ANA7 Scaling and Cyclic Converter A ANB0 Digital Output Sample/Hold ANB1 Storage Registers ANB2 ANB3 Scaling and Cyclic ANB4 Converter B...
Page 665: External Signal Descriptions
Chapter 34 12-bit Cyclic Analog-to-Digital Converter (ADC) 34.3.2 External Signal Descriptions 34.3.2.1 Analog Input Pins (ANA[0:7] and ANB[0:7]) Each ADC module has sixteen analog input pins that are subdivided into two sets of eight (ANA[0:7] and ANB[0:7]), each with their own S/H unit and converter. This configuration allows simultaneous sampling of two selected channels, one from each subgroup.
Page 666: Memory Map And Registers
Memory Map and Registers 1.0 mH Inductor External Reference Voltage 0.1uF REFH To ADC To ADC REFL Figure 34-3. ADC Voltage Reference Circuit Dedicated power supply pins, V and V , are provided to reduce noise coupling REFH REFL and to improve accuracy. The power to these pins should come from a low noise filtered source.
Page 667 Chapter 34 12-bit Cyclic Analog-to-Digital Converter (ADC) ADC memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 34.4.14/ 4005_C01A ADC Zero Crossing Status Register (ADC_ZXSTAT) 0000h 34.4.15/ 4005_C01C ADC Result Registers with sign extension (ADC_RSLT0) 0000h 34.4.15/ 4005_C01E ADC Result Registers with sign extension (ADC_RSLT1)
Page 668 Memory Map and Registers ADC memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 34.4.16/ 4005_C046 ADC Low Limit Registers (ADC_LOLIM5) 0000h 34.4.16/ 4005_C048 ADC Low Limit Registers (ADC_LOLIM6) 0000h 34.4.16/ 4005_C04A ADC Low Limit Registers (ADC_LOLIM7) 0000h 34.4.16/ 4005_C04C ADC Low Limit Registers (ADC_LOLIM8)
Page 669 Chapter 34 12-bit Cyclic Analog-to-Digital Converter (ADC) ADC memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 34.4.17/ 4005_C072 ADC High Limit Registers (ADC_HILIM11) 7FF8h 34.4.17/ 4005_C074 ADC High Limit Registers (ADC_HILIM12) 7FF8h 34.4.17/ 4005_C076 ADC High Limit Registers (ADC_HILIM13) 7FF8h...
Page 670 Memory Map and Registers ADC memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 34.4.20/ 4005_C09E ADC Calibration Register (ADC_CAL) 0000h 34.4.21/ 4005_C0A0 Gain Control 1 Register (ADC_GC1) 0000h 34.4.22/ 4005_C0A2 Gain Control 2 Register (ADC_GC2) 0000h 34.4.23/ 4005_C0A4 ADC Scan Control Register (ADC_SCTRL)
Page 671 Chapter 34 12-bit Cyclic Analog-to-Digital Converter (ADC) ADC_CTRL1 field descriptions (continued) Field Description DMA is not enabled. DMA is enabled. Stop STOP0 When this bit is asserted, the current scan is stopped and no further scans can start. Any further SYNC0 input pulses (see CTRL1[SYNC0] bit) or writes to the CTRL1[START0] bit are ignored until this bit has been cleared.
Page 672 Memory Map and Registers ADC_CTRL1 field descriptions (continued) Field Description Low Limit Interrupt Enable LLMTIE This bit enables the Low Limit exceeded interrupt when the current result value is less than the low limit register value. The raw result value is compared to LOLIM[LLMT] before the offset register value is subtracted.
Page 673 Chapter 34 12-bit Cyclic Analog-to-Digital Converter (ADC) ADC_CTRL1 field descriptions (continued) Field Description Parallel scans may be simultaneous (CTRL2[SIMULT] is 1) or non-simultaneous. Simultaneous parallel scans perform the A and B converter scan in lock step using one set of shared controls. Non-simultaneous parallel scans operate the A and B converters independently, with each converter using its own set of controls.
Page 674 Memory Map and Registers 34.4.2 ADC Control Register 2 (ADC_CTRL2) Address: 4005_C000h base + 2h offset = 4005_C002h Read DMAEN1 STOP1 SYNC1 EOSIE1 CHNCFG_H Write START1 Reset Read CHNCFG_H SIMULT DIV0 Write Reset ADC_CTRL2 field descriptions Field Description DMA enable DMAEN1 During parallel scan modes when SIMULT=0, this bit enables DMA for converter B.
Page 675 Chapter 34 12-bit Cyclic Analog-to-Digital Converter (ADC) ADC_CTRL2 field descriptions (continued) Field Description During parallel scan modes when CTRL2[SIMULT]=0, setting this bit to 1 permits a B converter parallel scan to be initiated by asserting the SYNC1 input for at least one ADC clock cycle. CTRL2[SYNC1] is cleared in ONCE mode, CTRL1[SMODE=000 or 001], when the first SYNC input is detected.
Page 676 Memory Map and Registers ADC_CTRL2 field descriptions (continued) Field Description When CTRL2[SIMULT]=0, parallel scans in the A and B converters operate independently. The B converter has its own independent set of the above controls (with a 1 suffix) which control its operation and report its status.
Page 677 Chapter 34 12-bit Cyclic Analog-to-Digital Converter (ADC) ADC_ZXCTRL1 field descriptions (continued) Field Description Zero Crossing enabled for negative to positive sign change Zero Crossing enabled for any sign change 9–8 Zero crossing enable 4 ZCE4 Zero Crossing disabled Zero Crossing enabled for positive to negative sign change Zero Crossing enabled for negative to positive sign change Zero Crossing enabled for any sign change 7–6...
Page 678 Memory Map and Registers ADC_ZXCTRL2 field descriptions (continued) Field Description Zero Crossing enabled for positive to negative sign change Zero Crossing enabled for negative to positive sign change Zero Crossing enabled for any sign change 13–12 Zero crossing enable 14 ZCE14 Zero Crossing disabled Zero Crossing enabled for positive to negative sign change...
Page 679 Chapter 34 12-bit Cyclic Analog-to-Digital Converter (ADC) 34.4.5 ADC Channel List Register 1 (ADC_CLIST1) Address: 4005_C000h base + 8h offset = 4005_C008h Read SAMPLE3 SAMPLE2 SAMPLE1 SAMPLE0 Write Reset ADC_CLIST1 field descriptions Field Description 15–12 Sample Field 3 SAMPLE3 Single Ended: ANA0, Differential: ANA0+, ANA1- 0000 0001 Single Ended: ANA1, Differential: ANA0+, ANA1-...
Page 680 Memory Map and Registers ADC_CLIST1 field descriptions (continued) Field Description 7–4 Sample Field 1 SAMPLE1 0000 Single Ended: ANA0, Differential: ANA0+, ANA1- Single Ended: ANA1, Differential: ANA0+, ANA1- 0001 Single Ended: ANA2, Differential: ANA2+, ANA3- 0010 0011 Single Ended: ANA3, Differential: ANA2+, ANA3- 0100 Single Ended: ANA4, Differential: ANA4+, ANA5- 0101...
Page 681 Chapter 34 12-bit Cyclic Analog-to-Digital Converter (ADC) ADC_CLIST2 field descriptions Field Description 15–12 Sample Field 7 SAMPLE7 Single Ended: ANA0, Differential: ANA0+, ANA1- 0000 0001 Single Ended: ANA1, Differential: ANA0+, ANA1- 0010 Single Ended: ANA2, Differential: ANA2+, ANA3- 0011 Single Ended: ANA3, Differential: ANA2+, ANA3- Single Ended: ANA4, Differential: ANA4+, ANA5- 0100 Single Ended: ANA5, Differential: ANA4+, ANA5-...
Page 682 Memory Map and Registers ADC_CLIST2 field descriptions (continued) Field Description Single Ended: ANB2, Differential: ANB2+, ANB3- 1010 1011 Single Ended: ANB3, Differential: ANB2+, ANB3- 1100 Single Ended: ANB4, Differential: ANB4+, ANB5- 1101 Single Ended: ANB5, Differential: ANB4+, ANB5- Single Ended: ANB6, Differential: ANB6+, ANB7- 1110 Single Ended: ANB7, Differential: ANB6+, ANB7- 1111...
Page 683 Chapter 34 12-bit Cyclic Analog-to-Digital Converter (ADC) ADC_CLIST3 field descriptions (continued) Field Description 1000 Single Ended: ANB0, Differential: ANB0+, ANB1- 1001 Single Ended: ANB1, Differential: ANB0+, ANB1- 1010 Single Ended: ANB2, Differential: ANB2+, ANB3- Single Ended: ANB3, Differential: ANB2+, ANB3- 1011 Single Ended: ANB4, Differential: ANB4+, ANB5- 1100...
Page 684 Memory Map and Registers ADC_CLIST3 field descriptions (continued) Field Description Single Ended: ANA1, Differential: ANA0+, ANA1- 0001 0010 Single Ended: ANA2, Differential: ANA2+, ANA3- 0011 Single Ended: ANA3, Differential: ANA2+, ANA3- 0100 Single Ended: ANA4, Differential: ANA4+, ANA5- Single Ended: ANA5, Differential: ANA4+, ANA5- 0101 Single Ended: ANA6, Differential: ANA6+, ANA7- 0110...
Page 685 Chapter 34 12-bit Cyclic Analog-to-Digital Converter (ADC) ADC_CLIST4 field descriptions (continued) Field Description 11–8 Sample Field 14 SAMPLE14 0000 Single Ended: ANA0, Differential: ANA0+, ANA1- 0001 Single Ended: ANA1, Differential: ANA0+, ANA1- 0010 Single Ended: ANA2, Differential: ANA2+, ANA3- Single Ended: ANA3, Differential: ANA2+, ANA3- 0011 Single Ended: ANA4, Differential: ANA4+, ANA5- 0100...
Page 686 Memory Map and Registers ADC_CLIST4 field descriptions (continued) Field Description Single Ended: ANB1, Differential: ANB0+, ANB1- 1001 1010 Single Ended: ANB2, Differential: ANB2+, ANB3- 1011 Single Ended: ANB3, Differential: ANB2+, ANB3- 1100 Single Ended: ANB4, Differential: ANB4+, ANB5- Single Ended: ANB5, Differential: ANB4+, ANB5- 1101 Single Ended: ANB6, Differential: ANB6+, ANB7- 1110...
Page 687 Chapter 34 12-bit Cyclic Analog-to-Digital Converter (ADC) 34.4.10 ADC Status Register (ADC_STAT) This register provides the current status of the ADC module. STAT[HLMTI and LLMTI] bits are cleared by writing 1s to all asserted bits in the limit status register, LIMSTAT. Likewise, the STAT[ZCI] bit, is cleared by writing 1s to all asserted bits in the zero crossing status register, ZXSTAT.
Page 688 Memory Map and Registers ADC_STAT field descriptions (continued) Field Description This interrupt is triggered only by the completion of a B converter scan in non-simultaneous parallel scan modes. A scan cycle has not been completed, no end of scan IRQ pending A scan cycle has been completed, end of scan IRQ pending End of Scan Interrupt EOSI0...
Page 689 Chapter 34 12-bit Cyclic Analog-to-Digital Converter (ADC) 34.4.11 ADC Ready Register (ADC_RDY) This register provides the current status of the ADC conversions. RDY[RDYx] bits are cleared by reading their corresponding result registers (RSLTx). Address: 4005_C000h base + 14h offset = 4005_C014h Read RDY[15:0] Write...
Page 690 Memory Map and Registers ADC_LOLIMSTAT field descriptions Field Description LLS[15:0] Low Limit Status Bits 34.4.13 ADC High Limit Status Register (ADC_HILIMSTAT) The high limit status register latches in the result of the comparison between the result of the sample and the respective high limit register, HILIM0-15. Here is an example: If the result for the channel programmed in CLIST1[SAMPLE0] is greater than the value programmed into the High Limit Register zero, then the LIMSTAT[HLS0] bit is set to one.
Page 691 Chapter 34 12-bit Cyclic Analog-to-Digital Converter (ADC) ADC_ZXSTAT field descriptions (continued) Field Description Either: • A sign change did not occur in a comparison between the current channelx result and the previous channelx result, or • Zero crossing control is disabled for channelx in the zero crossing control register, ZXCTRL In a comparison between the current channelx result and the previous channelx result, a sign change condition occurred as defined in the zero crossing control register (ZXCTRL) 34.4.15 ADC Result Registers with sign extension (ADC_RSLTn)
Page 692 Memory Map and Registers ADC_RSLTn field descriptions (continued) Field Description The interpretation of the numbers programmed into the limit and offset registers, LOLIM, HILIM, and OFFST should match your interpretation of the result register. Reserved This field is reserved. This read-only field is reserved and always has the value 0. 34.4.16 ADC Low Limit Registers (ADC_LOLIMn) Each ADC sample is compared against the values in the limit registers.
Page 693 Chapter 34 12-bit Cyclic Analog-to-Digital Converter (ADC) 34.4.17 ADC High Limit Registers (ADC_HILIMn) Each ADC sample is compared against the values in the limit registers. The comparison is based upon the raw conversion value with no offset correction applied. The limit register used corresponds to the result register the value will be written to.
Page 694 Memory Map and Registers ADC_OFFSTn field descriptions Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. 14–3 ADC Offset Bits OFFSET Reserved This field is reserved. This read-only field is reserved and always has the value 0. 34.4.19 ADC Power Control Register (ADC_PWR) This register controls the power management features of the ADC module.
Page 695 Chapter 34 12-bit Cyclic Analog-to-Digital Converter (ADC) Read PUDELAY Write Reset ADC_PWR field descriptions Field Description Auto Standby This bit selects auto-standby mode. PWR[ASB] is ignored if PWR[APD] is 1. When the ADC is idle, auto- standby mode selects the standby clock as the ADC clock source and puts the converters into standby current mode.
Page 696 Memory Map and Registers ADC_PWR field descriptions (continued) Field Description NOTE: PWR[PUDELAY] defaults to a value that is typically sufficient for any power mode. The latency of a scan can be reduced by reducing PWR[PUDELAY] to the lowest value for which accuracy is not degraded.
Page 697 Chapter 34 12-bit Cyclic Analog-to-Digital Converter (ADC) 34.4.20 ADC Calibration Register (ADC_CAL) The ADC provides for off-chip references that can be used for ADC conversions. Address: 4005_C000h base + 9Eh offset = 4005_C09Eh Read Write Reset ADC_CAL field descriptions Field Description Select V Source...
Page 698 Memory Map and Registers 34.4.21 Gain Control 1 Register (ADC_GC1) The gain control registers are used to control amplification of each of the 16 input channels. GAIN0-GAIN7 control the amplification of inputs ANA0-ANA7 while GAIN8-GAIN15 control the amplification of inputs ANB0-ANB7. Address: 4005_C000h base + A0h offset = 4005_C0A0h Read GAIN7...
Page 699 Chapter 34 12-bit Cyclic Analog-to-Digital Converter (ADC) ADC_GC1 field descriptions (continued) Field Description 7–6 Gain Control Bit 3 GAIN3 GAIN 3 controls ANA3 x1 amplification x2 amplification x4 amplification reserved 5–4 Gain Control Bit 2 GAIN2 GAIN 2 controls ANA2 x1 amplification x2 amplification x4 amplification...
Page 700 Memory Map and Registers ADC_GC2 field descriptions Field Description 15–14 Gain Control Bit 15 GAIN15 GAIN 15 controls ANB7 x1 amplification x2 amplification x4 amplification reserved 13–12 Gain Control Bit 14 GAIN14 GAIN 14 controls ANB6 x1 amplification x2 amplification x4 amplification reserved 11–10...
Page 701 Chapter 34 12-bit Cyclic Analog-to-Digital Converter (ADC) ADC_GC2 field descriptions (continued) Field Description x1 amplification x2 amplification x4 amplification reserved GAIN8 Gain Control Bit 8 GAIN 8 controls ANB0 x1 amplification x2 amplification x4 amplification reserved 34.4.23 ADC Scan Control Register (ADC_SCTRL) This register is an extension to the CLIST1-4 registers, providing the ability to pause and await a new sync while processing samples programmed in the CLIST*[SAMPLE0–...
Page 702 Memory Map and Registers ADC_SCTRL field descriptions (continued) Field Description Perform sample immediately after the completion of the current sample. Delay sample until a new sync input occurs. 34.4.24 ADC Power Control Register (ADC_PWR2) Address: 4005_C000h base + A6h offset = 4005_C0A6h Read DIV1 SPEEDB...
Page 703 Chapter 34 12-bit Cyclic Analog-to-Digital Converter (ADC) 34.4.25 ADC Control Register 3 (ADC_CTRL3) Address: 4005_C000h base + A8h offset = 4005_C0A8h Read Write Reset Read DMASRC SCNT1[2:0] SCNT0[2:0] Write Reset ADC_CTRL3 field descriptions Field Description 15–7 This field is reserved. Reserved This read-only field is reserved and always has the value 0.
Page 704: Functional Description
Functional Description 34.4.26 ADC Scan Interrupt Enable Register (ADC_SCHLTEN) This register is used with ready register (RDY) to select the samples that will generate a scan interrupt. Address: 4005_C000h base + AAh offset = 4005_C0AAh Read SCHLTEN[15:0] Write Reset ADC_SCHLTEN field descriptions Field Description SCHLTEN[15:0] Scan Interrupt Enable...
Page 705 Chapter 34 12-bit Cyclic Analog-to-Digital Converter (ADC) ANA0 ANA1 A/D 0 ANA2 ADRSLT0 ANA3 ADRSLT1 ANA4 ADRSLT2 ANA5 ADRSLT3 ANA6 ADRSLT4 ANA7 ADRSLT5 ADRSLT6 SAMPLEn[3:0] ADRSLT7 ADRSLT8 ADRSLT9 ANB0 ADRSLT10 ANB1 ADRSLT11 A/D 1 ANB2 ADRSLT12 ANB3 ADRSLT13 ANB4 ADRSLT14 ANB5 ADRSLT15 ANB6...
Page 706 Functional Description ANA0 SAMPLEn is from ADLST1 or ADLST2.SAMPLEm is from ADLST3 or ADLST4. ANA1 ANA2 ANA3 ADRSLT0 ANA4 ADRSLT1 ANA5 A/D 0 ADRSLT2 ANA6 ADRSLT3 ANA7 ADRSLT4 ADRSLT5 SAMPLEn[3:0] ADRSLT6 ADRSLT7 SAMPLEn Field FromADLST1 or ADLST2 Register ANB0 ANB1 ADRSLT8 ANB2 ADRSLT9...
Page 707 Chapter 34 12-bit Cyclic Analog-to-Digital Converter (ADC) independently. Each converter has its own start, stop, sync, end-of-scan interrupt enable controls, and interrupts. Scanning in either converter terminates only when that converter encounters a disabled sample. The ADC can be configured to perform a single scan and halt, perform a scan whenever triggered, or perform the scan sequence repeatedly until manually stopped.
Page 708 Functional Description VREFH ADCA.VREFH VREFL ADCA.VREFL Channel Select ANA0 ANA1 ANA2 To Interface Function ANA3 Converter A ANA4 ANA5 ANA6 ANA7 Single-Ended (Vrefh + Vrefl)/2 Differential VREFH ADCB.VREFH VREFL ADCB.VREFL Channel Select ANB0 ANB1 ANB2 To Interface ANB3 Function Converter B ANB4 ANB5 ANB6...
Page 709 Chapter 34 12-bit Cyclic Analog-to-Digital Converter (ADC) • Sequential, differential mode conversions — During any conversion cycle (sample), either member of a differential pair may be referenced, resulting in a differential measurement on that pair. • Parallel, single-ended mode conversions — During any conversion cycle (sample), any of ANA[0:7] can be directed to the converter A output and any of ANB[0:7] can be directed to the converter B output.
Page 710: Normal Mode Operation
Functional Description 34.5.2 ADC Sample Conversion Operating Modes The ADC consists of a cyclic, algorithmic architecture using two recursive sub-ranging sections (RSD 1 and RSD 2) as shown in the following figure. Each sub-ranging section resolves a single bit for each conversion clock, resulting in an overall conversion rate of 2 bits per clock cycle.
Page 711 Chapter 34 12-bit Cyclic Analog-to-Digital Converter (ADC) • Single-ended mode (CHNCFG bit=0). The input multiplex of the ADC selects one of the 8 analog inputs and directs it to the plus terminal of the A/D core. The minus terminal of the A/D core is connected to the V reference.
Page 712: Adc Data Processing
Functional Description =Applied voltage at the input pin and V =Voltage at the external reference pins on the device (typically V and V REFH REFL REFH REFL Note: The 12-bit result is rounded to the nearest LSB. Note: The ADC is a 12-bit function with 4096 possible states. However, the 12 bits have been left shifted three bits on the 16-bit data bus, so the magnitude of this function, as read from the data bus, is now 32760.
Page 713 Chapter 34 12-bit Cyclic Analog-to-Digital Converter (ADC) normal mode. For example, if the STOP bit is set to one and the processor writes to RSLT5, the data written to the RSLT5 is multiplexed to the ADC digital logic inputs, processed, and stored into RSLT5 as if the analog core had provided the data. This test data must be justified, as illustrated by the RSLT register definition and does not include the sign bit.
Page 714: Scan Sequencing
Functional Description CTRL1[DMAEN0] is set and CTRL3[DMASRC]=0 a DMA transfer of the result data is initiated. The CTRL1[START0] bit and SYNC0 input are ignored while a scan is in process. Scanning stops and cannot be initiated when the CTRL1 [STOP0] bit is set. Parallel scans differ in that converter A performs up to eight samples (SAMPLE[0:7]) in parallel with converter B (SAMPLE[8:15]).
Page 715: Low Power Modes
Chapter 34 12-bit Cyclic Analog-to-Digital Converter (ADC) • Triggered scan. Identical to the corresponding once scan modes except that resetting CTRL*[SYNC*] bits is not necessary. • Looping scan. Automatically restarts a scan, either parallel or sequential, as soon as the previous scan completes. In parallel looping scan modes, the A converter scan restarts as soon as the A converter scan completes and the B converter scan restarts as soon as the B converter scan completes.
Page 716 Functional Description Mode Description Auto-Powerdown At least one ADC converter is powered up (PWR[PD0 or PD1] is 0), PWR[APD] is 1, and the SIM_SCGC5[ADC] bit is 1. The conversion clock should be configured at or near 20 MHz to minimize conversion latency when active although PWR2[SPEEDn] can be used for reduced power consumption when lower conversion frequencies are acceptable.
Page 717 Chapter 34 12-bit Cyclic Analog-to-Digital Converter (ADC) Normal mode does not use PWR[PUDELAY] at start of scan, so no further delay is imposed. To start up in auto-standby, use the normal mode startup procedure first. Before starting scan operations, set PWR[PUDELAY] to the moderate standby recovery value, and set PWR[ASB].
Page 718 Reset 34.6 Reset At reset, all the registers return to the reset state. 34.7 Clocks The ADC has two external clock inputs to drive two clock domains within the ADC module. Table 34-96. Clock Summary Clock input Source Characteristics Maximun rate is 150 MHz from fast bus clock domain. When the device is IP Clock in low power mode, the IP clock is from MCGIRCLK.
Page 719 Chapter 34 12-bit Cyclic Analog-to-Digital Converter (ADC) Conversion Clock IP_CLK Divide By (DIV + 1) Clock Conversion Clock Source MCGIRCLK (4 MHz) Divide by (DIV + 1) Auto-Standby Clock STOP mode/VLPS mode and SIM_ADCOPT[ROSB]=1 Standby ASB=1 Current Mode APD=0 IDLE Figure 34-100.
Page 720 Interrupts 34.8 Interrupts The following table summarizes the ADC interrupts. Table 34-97. Interrupt Summary Interrupt Source Description STAT[[ZCI], ADC_ERR_INT_B STAT[LLMTI], Zero Crossing, low Limit, and high limit interrupt STAT[HLMTI] STAT[EOSI0] Conversion Complete and Scan Interrupt for any scan type except ADC_CC0_INT_B converter B scan in non-simultaneous parallel scan mode (see EOSI0) RDY[RDY[15:0]]...
Page 721: Timing Specifications
Chapter 34 12-bit Cyclic Analog-to-Digital Converter (ADC) 34.9 Timing Specifications The following figure shows a timing diagram for the ADC module. The ADC is assumed to be in Once or Triggered mode, so the ADC clock is shown in the OFF state prior to the SYNC pulse or START bit write.
Page 722 Timing Specifications Because the conversion is a pipeline process, after the last sample is in the S/H, the ADC cannot be restarted until the pipeline is emptied. However, the conversion cycle can be aborted by issuing a STOP command. The figure shown here illustrates the case in which PWR[APD and ASB] are not in use. When the PWR[APD or ASB] bit is set, the sync pulse or start powers up the ADC, waits for a number of ADC clocks (determined by the PWR[PUDELAY] bits) for the ADC circuitry to stabilize, and only then begins the conversion sequence.
Page 723: Chapter 35 Comparator (Cmp)
Chapter 35 Comparator (CMP) 35.1 Chip-specific CMP information 35.1.1 CMP Signal Assignments NOTE For more details see SIM_MISCTRL and SIM_SOPT7 registers Table 35-1. CMP Signal assignments Instance Signal Description Connected to Ext Pin Mux / SIM Pin No. Of CMP0 input channel input CMP0_IN0 pin...
Page 724 Chip-specific CMP information Table 35-1. CMP Signal assignments (continued) Instance Signal Description Connected to Ext Pin Mux / SIM Pin No. Of input channel input CMP1_IN1 pin PTC3 pin73 of 100 input channel input CMP1_IN2 pin ADC0_SE8 pin 36 of 144 input channel input CMP1_IN3 pin...
Page 725: Cmp External References
Chapter 35 Comparator (CMP) Table 35-1. CMP Signal assignments (continued) Instance Signal Description Connected to Ext Pin Mux / SIM Pin No. Of WindowIN — input PDB0 pulse out, — — PDB1 pulse out XBARA_OUT19 CMP3_OUT — output XBARA_IN15, — —...
Page 726: Cmp Features
Introduction 35.2.1 CMP features The CMP has the following features: • Operational over the entire supply range • Inputs may range from rail to rail • Programmable hysteresis control • Selectable interrupt on rising-edge, falling-edge, or both rising or falling edges of the comparator output •...
Page 727: Anmux Key Features
Chapter 35 Comparator (CMP) • Power Down mode to conserve power when not in use • Option to route the output to internal comparator input 35.2.3 ANMUX key features The ANMUX has the following features: • Two 8-to-1 channel mux •...
Page 728: Cmp Block Diagram
Introduction VRSEL VOSEL[5:0] DACEN DAC output PSEL[2:0] Reference Input 0 Reference Input 1 Reference Input 2 Reference Input 3 Reference Input 4 Sample input Reference Input 5 Reference Input 6 Window ANMUX and filter control CMPO MSEL[2:0] Figure 35-1. CMP, DAC and ANMUX block diagram 35.2.5 CMP block diagram The following figure shows the block diagram for the CMP module.
Page 729 Chapter 35 Comparator (CMP) Internal bus FILT_PER EN,PMODE,HYSCTRL[1:0] COUT IER/F CFR/F FILTER_CNT Window Interrupt Polarity Filter control select control block CMPO COUT To other SOC functions WINDOW/SAMPLE bus clock Clock COUTA CMPO to divided prescaler FILT_PER CGMUX clock Figure 35-2. Comparator module block diagram In the CMP block diagram: •...
Page 730 Memory map/register definitions • If enabled, the Filter block will incur up to one bus clock additional latency penalty on COUT due to the fact that COUT, which is crossing clock domain boundaries, must be resynchronized to the bus clock. •...
Page 731 Chapter 35 Comparator (CMP) 35.3.1 CMP Control Register 0 (CMPx_CR0) Address: Base address + 0h offset Read FILTER_CNT HYSTCTR Write Reset CMPx_CR0 field descriptions Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. 6–4 Filter Sample Count FILTER_CNT...
Page 732 Memory map/register definitions CMPx_CR1 field descriptions Field Description Sample Enable At any given time, either SE or WE can be set. It is mandatory request to not set SE and WE both at a given time. Sampling mode is not selected. Sampling mode is selected.
Page 733 Chapter 35 Comparator (CMP) CMPx_CR1 field descriptions (continued) Field Description The comparator output (CMPO) is driven out on the associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this bit has no effect. Comparator Module Enable Enables the Analog Comparator module.
Page 734 Memory map/register definitions CMPx_SCR field descriptions (continued) Field Description DMA Enable Control DMAEN Enables the DMA transfer triggered from the CMP module. When this field is set, a DMA request is asserted when CFR or CFF is set. DMA is disabled. DMA is enabled.
Page 735 Chapter 35 Comparator (CMP) CMPx_DACCR field descriptions Field Description DAC Enable DACEN Enables the DAC. When the DAC is disabled, it is powered down to conserve power. DAC is disabled. DAC is enabled. Supply Voltage Reference Source Select VRSEL is selected as resistor ladder network supply reference. is selected as resistor ladder network supply reference.
Page 736: Functional Description
Functional description CMPx_MUXCR field descriptions (continued) Field Description MSEL Minus Input Mux Control Determines which input is selected for the minus input of the comparator. For INx inputs, see CMP, DAC, and ANMUX block diagrams. NOTE: When an inappropriate operation selects the same input for both muxes, the comparator automatically shuts down to prevent itself from becoming a noise generator.
Page 737 Chapter 35 Comparator (CMP) The filter, CR0[FILTER_CNT], can be clocked from an internal or external clock source. The filter is programmable with respect to the number of samples that must agree before a change in the output is registered. In the simplest case, only one sample must agree. In this case, the filter acts as a simple sampler.
Page 738 Functional description Table 35-37. Comparator sample/filter controls (continued) CR0[FILTER_C Mode # CR1[EN] CR1[WE] CR1[SE] FPR[FILT_PER] Operation Comparator output is sampled on every rising bus clock edge when SAMPLE=1 to generate COUTA, which is then resampled and filtered to generate COUT. See the Windowed/Filtered mode (#7).
Page 739 Chapter 35 Comparator (CMP) Internal bus FILT_PER FILTER_CNT COUT IER/F CFR/F EN,PMODE,HYSTCTR[1:0] Window Filter Interrupt Polarity control block control select CMPO COUT To other system functions WINDOW/SAMPLE bus clock Clock COUTA CMPO to prescaler divided FILT_PER CGMUX clock Figure 35-33. Comparator operation in Continuous mode The analog comparator block is powered and active.
Page 740 Functional description Internal bus FILT_PER FILTER_CNT COUT IER/F CFR/F EN,PMODE,HYSTCTR[1:0] 0x01 Filter Polarity Window Interrupt block select control control CMPO COUT To other SOC functions WINDOW/SAMPLE bus clock Clock COUTA CMPO to prescaler divided FILT_PER CGMUX clock SE=1 Figure 35-34. Sampled, Non-Filtered (# 3A): sampling point externally driven In Sampled, Non-Filtered mode, the analog comparator block is powered and active.
Page 741 Chapter 35 Comparator (CMP) Internal bus FILT_PER EN,PMODE,HYSTCTR[1:0] FILTER_CNT COUT IER/F CFR/F 0x01 Polarity Window Filter Interrupt select control block control CMPO COUT To other SOC functions WINDOW/SAMPLE bus clock Clock COUTA CMPO to divided bus clock prescaler FILT_PER CGMUX SE=0 Figure 35-35.
Page 742 Functional description Internal bus FILT_PER EN, PMODE, HYSTCTR[1:0] FILTER_CNT IER/F COUT CFR/F > 0x01 Polarity Interrupt Window Filter select control control block CMPO COUT To other SOC functions WINDOW/SAMPLE bus clock Clock COUTA CMPO to prescaler divided FILT_PER CGMUX clock SE=1 Figure 35-36.
Page 743 Chapter 35 Comparator (CMP) Internal bus FILT_PER FILT_PER IER/F CFR/F COUT EN, PMODE, HYSTCTR[1:0 FILTER_CNT > 0x01 Filter Polarity Window Interrupt block select control control CMPO COUT To other SOC functions WINDOW/SAMPLE bus clock Clock COUTA CMPO to prescaler divided CGMUX clock SE=0...
Page 744 Functional description WINDOW Plus input Minus input CMPO COUTA Figure 35-38. Windowed mode operation Internal bus FILT_PER EN, PMODE,HYSCTR[1:0] COUT IER/F FILTER_CNT CFR/F 0x01 Interrupt Polarity Window Filter select control control block CMPO COUT To other SOC functions WINDOW/SAMPLE bus clock Clock COUTA CMPO to...
Page 745 Chapter 35 Comparator (CMP) When any windowed mode is active, COUTA is clocked by the bus clock whenever WINDOW = 1. The last latched value is held when WINDOW = 0. 35.4.1.6 Windowed/Resampled mode (# 6) The following figure uses the same input stimulus shown in Figure 35-38, and adds resampling of COUTA to generate COUT.
Page 746: Wait Mode Operation
Functional description 35.4.1.7 Windowed/Filtered mode (#7) This is the most complex mode of operation for the comparator block, as it uses both windowing and filtering features. It also has the highest latency of any of the modes. This can be approximated: up to 1 bus clock synchronization in the window function + ((CR0[FILTER_CNT] * FPR[FILT_PER]) + 1) * bus clock for the filter function.
Page 747: Stop Mode Operation
Chapter 35 Comparator (CMP) 35.4.2.2 Stop mode operation Depending on clock restrictions related to the MCU core or core peripherals, the MCU is brought out of stop when a compare event occurs and the corresponding interrupt is enabled. Similarly, if CR1[OPE] is enabled, the comparator output operates as in the normal operating mode and comparator output is placed onto the external pin.
Page 748: Low Pass Filter
Functional description 35.4.4 Low-pass filter The low-pass filter operates on the unfiltered and unsynchronized and optionally inverted comparator output COUTA and generates the filtered and synchronized output COUT. Both COUTA and COUT can be configured as module outputs and are used for different purposes within the system.
Page 749: Latency Issues
Chapter 35 Comparator (CMP) If CR1[SE]=1, the filter takes samples of COUTA on each positive transition of the sample input. The output state of the filter changes when all the consecutive CR0[FILTER_CNT] samples agree that the output value has changed. 35.4.4.2 Latency issues The value of FPR[FILT_PER] or SAMPLE period must be set such that the sampling period is just longer than the period of the expected noise.
Page 750: Cmp Interrupts
CMP interrupts 1. T represents the intrinsic delay of the analog component plus the polarity select logic. T is the clock period of the SAMPLE external sample clock. T is the period of the bus clock. 35.5 CMP interrupts The CMP module is capable of generating an interrupt on either the rising- or falling- edge of the comparator output, or both.
Page 751: Digital-To-Analog Converter
Chapter 35 Comparator (CMP) When DMA support is enabled by setting SCR[DMAEN] and the interrupt is enabled by setting SCR[IER], SCR[IEF], or both, the corresponding change on COUT forces a DMA transfer request to wake up the system from STOP modes. After the data transfer has finished, system will go back to STOP modes.
Page 752: Voltage Reference Source Select
DAC resets 35.9.1 Voltage reference source select • V connects to the primary voltage source as supply reference of 64 tap resistor ladder • V connects to an alternate voltage source 35.10 DAC resets This module has a single reset input, corresponding to the chip-wide peripheral reset. 35.11 DAC clocks This module has a single clock input, the bus clock.
Page 753: 12-Bit Dac Instantiation Information
Chapter 36 12-bit Digital-to-Analog Converter (DAC) 36.1 Chip-specific 12-bit DAC information 36.1.1 12-bit DAC Instantiation Information This device contains one 12-bit digital-to-analog converter (DAC) with programmable reference generator output. The DAC includes a 16 deep 12bit FIFO for DMA support. DAC0_OUT signal is connected to CMP3_IN3 and CMP1_IN3/PTE30.
Page 754: Block Diagram
Introduction 36.2 Introduction The 12-bit digital-to-analog converter (DAC) is a low-power, general-purpose DAC. The output of the DAC can be placed on an external pin or set as one of the inputs to the analog comparator, op-amps, or ADC. 36.3 Features The features of the DAC module include: •...
Page 755: Memory Map/Register Definition
Chapter 36 12-bit Digital-to-Analog Converter (DAC) DACREF_1 DACREF_2 DACRFS DACRFS AMP buffer DACEN LPEN DACDAT[11:0] Hardware trigger DACBFWMF & DACBWIEN DACSWTRG Data Buffer DACBFWM DACBFRPTF dac_interrupt & DACBFEN DACBTIEN DACBFUP DACBFRPBF DACBFRP & DACBBIEN DACBFMD DACTRGSE Figure 36-1. DAC block diagram 36.5 Memory map/register definition The DAC has registers to control analog comparator and programmable voltage divider to perform the digital-to-analog functions.
Page 756 Memory map/register definition DAC memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4003_F000 DAC Data Low Register (DAC_DAT0L) 36.5.1/757 4003_F001 DAC Data High Register (DAC_DAT0H) 36.5.2/757 4003_F002 DAC Data Low Register (DAC_DAT1L) 36.5.1/757 4003_F003 DAC Data High Register (DAC_DAT1H) 36.5.2/757...
Page 757 Chapter 36 12-bit Digital-to-Analog Converter (DAC) 36.5.1 DAC Data Low Register (DAC_DATnL) Address: 4003_F000h base + 0h offset + (2d × i), where i=0d to 15d Read DATA0 Write Reset DAC_DATnL field descriptions Field Description DATA0 DATA0 When the DAC buffer is not enabled, DATA[11:0] controls the output voltage based on the following formula: V * (1 + DACDAT0[11:0])/4096 When the DAC buffer is enabled, DATA is mapped to the 16-word buffer.
Page 758 Memory map/register definition 36.5.3 DAC Status Register (DAC_SR) If DMA is enabled, the flags can be cleared automatically by DMA when the DMA request is done. Writing 0 to a field clears it whereas writing 1 has no effect. After reset, DACBFRPTF is set and can be cleared by software, if needed.
Page 759 Chapter 36 12-bit Digital-to-Analog Converter (DAC) 36.5.4 DAC Control Register (DAC_C0) Address: 4003_F000h base + 21h offset = 4003_F021h Read DACTRGSE DACEN DACRFS LPEN DACBWIEN DACBTIEN DACBBIEN Write DACSWTRG Reset DAC_C0 field descriptions Field Description DAC Enable DACEN Starts the Programmable Reference Generator operation. The DAC system is disabled.
Page 760 Memory map/register definition DAC_C0 field descriptions (continued) Field Description The DAC buffer read pointer bottom flag interrupt is disabled. The DAC buffer read pointer bottom flag interrupt is enabled. 36.5.5 DAC Control Register 1 (DAC_C1) Address: 4003_F000h base + 22h offset = 4003_F022h Read DMAEN DACBFWM...
Page 761: Dac Data Buffer Operation
Chapter 36 12-bit Digital-to-Analog Converter (DAC) 36.5.6 DAC Control Register 2 (DAC_C2) Address: 4003_F000h base + 23h offset = 4003_F023h Read DACBFRP DACBFUP Write Reset DAC_C2 field descriptions Field Description 7–4 DAC Buffer Read Pointer DACBFRP In normal mode it keeps the current value of the buffer read pointer. FIFO mode, it is the FIFO read pointer.
Page 762: Dac Data Buffer Interrupts
Functional description The data buffer can be configured to operate in Normal mode, Swing mode, One-Time Scan mode or FIFO mode. When the buffer operation is switched from one mode to another, the read pointer does not change. The read pointer can be set to any value between 0 and C2[DACBFUP] by writing C2[DACBFRP].
Page 763: Dma Operation
Chapter 36 12-bit Digital-to-Analog Converter (DAC) Table 36-40. Modes of DAC data buffer operation Modes Description NOTE: A successful 32bit FIFO write will increase the write pointer by 2. Any write will cause the FIFO over-flow will be ignored, the cases includes: 1.FIFO is full, the write will be ignored.
Page 764 Functional description Table 36-41. Modes of operation Modes of operation Description Wait mode The DAC will operate normally, if enabled. In low-power stop modes, the DAC is fully Stop mode shut down. NOTE The assignment of module modes to core modes is chip- specific.
Page 765: Chapter 37 Pulse Width Modulator A (Pwma/Eflexpwm)
Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM) 37.1 Chip-specific eFlexPWM information 37.1.1 eFlexPWM Inputs For this chip the flexPWM has the following signal input connections. Input synchronisation to the four submodules of the flexPWM are fed from the XBARA module, which provides flexible triggering and fault inputs from other peripherals. PWMA signal Connected to PWMA0_EXTA...
Page 766 Introduction 37.1.2 eFlexPWM Outputs For this chip the PWMA has the following signal output connections. Output trigger events from the PWMA are used to trigger other peripherals to take action via the XBARA and XBARB and AOI module. Each of the four sub modules have two trigger outputs (TRIG0) and TRIG1).
Page 767: Modes Of Operation
Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM) 37.2.1 Features • 16 bits of resolution for center, edge-aligned, and asymmetrical PWMs • Fractional PWM clock generation for enhanced resolution of the PWM period and duty cycle • Dithering to simulate enhanced resolution when fine edge placement is not available •...
Page 768: Block Diagram
Introduction CAUTION Some applications require regular software updates for proper operation. Failure to provide regular software updates could result in destroying the hardware setup. To accommodate this situation, PWM outputs are placed in their inactive states in stop mode, and they can optionally be placed in inactive states in wait and debug (EOnCE) modes.
Page 769 Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM) EXT_SYNC PWMA0 EXT_FORCE PWMB0 Sub-Module 0 PWMX0 FAULT0-3 Fault Channel 0 PWMA1 PWMB1 Sub-Module 1 PWMX1 PWMA2 PWMB2 Sub-Module 2 PWMX2 PWMA3 PWMB3 Sub-Module 3 PWMX3 Figure 37-1. PWM Block Diagram KV4x Reference Manual, Rev. 2, 02/2015 Preliminary Freescale Semiconductor, Inc.
Page 770 Signal Descriptions 37.2.3.1 PWM Submodule Force Init LDOK Aux Clock (sub-module 0 only) Compare 0 value Mid-cycle reload 16 bit Master Reload Reload Prescaler Clock comparator 16 bit counter (sub-module 0 only) Logic Compare 1 value 16 bit Modulo counter value Master Sync comparator (sub-module 0 only)
Page 771: Control Signals
Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM) 37.3.2 PWM[n]_X - Auxiliary PWM Output signal These pins are the auxiliary output pins of the PWM channels. They can be independent PWM signals. When not needed as an output, they can be used as inputs to the input capture circuitry or used to detect the polarity of the current flowing through the complementary circuit at deadtime correction.
Page 772: Memory Map And Registers
Memory Map and Registers 37.3.8 EXT_CLK - External Clock Signal This signal allows a source external to the PWM (typically a timer or an off-chip source) to control the PWM clocking. In this manner, the PWM can be synchronized to the timer, or multiple chips can be synchronized to each other.
Page 773 Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM) PWMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4003_300E Value Register 1 (PWMA_SM0VAL1) 0000h 37.4.7/786 4003_3010 Fractional Value Register 2 (PWMA_SM0FRACVAL2) 0000h 37.4.8/787 4003_3012 Value Register 2 (PWMA_SM0VAL2) 0000h 37.4.9/788...
Page 774 Memory Map and Registers PWMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 37.4.30/ 4003_303E Capture Compare X Register (PWMA_SM0CAPTCOMPX) 0000h 37.4.31/ 4003_3040 Capture Value 0 Register (PWMA_SM0CVAL0) 0000h 37.4.32/ 4003_3042 Capture Value 0 Cycle Register (PWMA_SM0CVAL0CYC) 0000h 37.4.33/ 4003_3044...
Page 775 Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM) PWMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 37.4.14/ 4003_307C Fractional Value Register 5 (PWMA_SM1FRACVAL5) 0000h 37.4.15/ 4003_307E Value Register 5 (PWMA_SM1VAL5) 0000h 37.4.16/ 4003_3080 Fractional Control Register (PWMA_SM1FRCTRL) 0000h...
Page 776 Memory Map and Registers PWMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 37.4.36/ 4003_30AA Capture Value 2 Cycle Register (PWMA_SM1CVAL2CYC) 0000h 37.4.37/ 4003_30AC Capture Value 3 Register (PWMA_SM1CVAL3) 0000h 37.4.38/ 4003_30AE Capture Value 3 Cycle Register (PWMA_SM1CVAL3CYC) 0000h 37.4.39/ 4003_30B0...
Page 777 Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM) PWMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 37.4.20/ 4003_30E8 DMA Enable Register (PWMA_SM2DMAEN) 0000h 37.4.21/ 4003_30EA Output Trigger Control Register (PWMA_SM2TCTRL) 0000h 37.4.22/ 4003_30EC Fault Disable Mapping Register 0 (PWMA_SM2DISMAP0) FFFFh 37.4.23/...
Page 778 Memory Map and Registers PWMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 37.4.42/ 4003_3116 Capture Value 5 Cycle Register (PWMA_SM2CVAL5CYC) 0000h 4003_3120 Counter Register (PWMA_SM3CNT) 0000h 37.4.1/780 4003_3122 Initial Count Register (PWMA_SM3INIT) 0000h 37.4.2/780 4003_3124...
Page 779 Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM) PWMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 37.4.26/ 4003_3156 Capture Compare A Register (PWMA_SM3CAPTCOMPA) 0000h 37.4.27/ 4003_3158 Capture Control B Register (PWMA_SM3CAPTCTRLB) 0000h 37.4.28/ 4003_315A Capture Compare B Register (PWMA_SM3CAPTCOMPB)
Page 780 Memory Map and Registers PWMA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 37.4.49/ 4003_318A Master Control 2 Register (PWMA_MCTRL2) 0000h 37.4.50/ 4003_318C Fault Control Register (PWMA_FCTRL) 0000h 37.4.51/ 4003_318E Fault Status Register (PWMA_FSTS) 0000h 37.4.52/ 4003_3190...
Page 781 Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM) NOTE The INIT register is buffered. The value written does not take effect until MCTRL[LDOK] is set and the next PWM load cycle begins or CTRL[LDMOD] is set. This register cannot be written when MCTRL[LDOK] is set. Reading INIT reads the value in a buffer and not necessarily the value the PWM generator is currently using.
Page 782 Memory Map and Registers PWMA_SMnCTRL2 field descriptions (continued) Field Description WAIT Enable WAITEN When set to one, the PWM will continue to run while the chip is in WAIT mode. In this mode, the peripheral clock continues to run but the CPU clock does not. If the device enters WAIT mode and this bit is zero, then the PWM outputs will be disabled until WAIT mode is exited.
Page 783 Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM) PWMA_SMnCTRL2 field descriptions (continued) Field Description • The PWM_A and PWM_B output pins will assume values based on DTSRCSEL[SMxSEL23] and DTSRCSEL[SMxSEL45]. • If CTRL2[FRCEN] is set, the counter value will be initialized with the INIT register value. 5–3 This read/write bit determines the source of the FORCE OUTPUT signal for this submodule.
Page 784 Memory Map and Registers PWMA_SMnCTRL field descriptions Field Description 15–12 These buffered read/write bits select the PWM load frequency. Reset clears LDFQ, selecting loading LDFQ every PWM opportunity. A PWM opportunity is determined by HALF and FULL. NOTE: LDFQ takes effect when the current load cycle is complete, regardless of the state of MCTRL[LDOK].
Page 785 Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM) PWMA_SMnCTRL field descriptions (continued) Field Description NOTE: Reading CTRL[PRSC] reads the buffered values and not necessarily the values currently in effect. CTRL[PRSC] takes effect at the beginning of the next PWM cycle and only when the load okay bit, MCTRL[LDOK], is set or CTRL[LDMOD] is set.
Page 786 Memory Map and Registers PWMA_SMnVAL0 field descriptions Field Description VAL0 Value Register 0 The 16-bit signed value in this buffered, read/write register defines the mid-cycle reload point for the PWM in PWM clock periods. This value also defines when the PWM_X signal is set and the local sync signal is reset.
Page 787 Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM) PWMA_SMnVAL1 field descriptions Field Description VAL1 Value Register 1 The 16-bit signed value written to this buffered, read/write register defines the modulo count value (maximum count) for the submodule counter. Upon reaching this count value, the counter reloads itself with the contents of the INIT register and asserts the local sync signal while resetting PWM_X.
Page 788 Memory Map and Registers 37.4.9 Value Register 2 (PWMA_SMnVAL2) Address: 4003_3000h base + 12h offset + (96d × i), where i=0d to 3d Read VAL2 Write Reset PWMA_SMnVAL2 field descriptions Field Description VAL2 Value Register 2 The 16-bit signed value in this buffered, read/write register defines the count value to set PWM23 high. This register is not byte accessible.
Page 789 Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM) 37.4.11 Value Register 3 (PWMA_SMnVAL3) Address: 4003_3000h base + 16h offset + (96d × i), where i=0d to 3d Read VAL3 Write Reset PWMA_SMnVAL3 field descriptions Field Description VAL3 Value Register 3 The 16-bit signed value in this buffered, read/write register defines the count value to set PWM23 low. This register is not byte accessible.
Page 790 Memory Map and Registers 37.4.13 Value Register 4 (PWMA_SMnVAL4) Address: 4003_3000h base + 1Ah offset + (96d × i), where i=0d to 3d Read VAL4 Write Reset PWMA_SMnVAL4 field descriptions Field Description VAL4 Value Register 4 The 16-bit signed value in this buffered, read/write register defines the count value to set PWM45 high. This register is not byte accessible.
Page 791 Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM) 37.4.15 Value Register 5 (PWMA_SMnVAL5) Address: 4003_3000h base + 1Eh offset + (96d × i), where i=0d to 3d Read VAL5 Write Reset PWMA_SMnVAL5 field descriptions Field Description VAL5 Value Register 5 The 16-bit signed value in this buffered, read/write register defines the count value to set PWM45 low. This register is not byte accessible.
Page 792 Memory Map and Registers PWMA_SMnFRCTRL field descriptions (continued) Field Description down when the FRAC_PU bits in all submodules are 0. The fractional delay logic can only be used when the IPBus clock is running at 100 MHz. When turned off, fractional placement is disabled. Turn off fractional delay logic.
Page 793 Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM) 37.4.17 Output Control Register (PWMA_SMnOCTRL) Address: 4003_3000h base + 22h offset + (96d × i), where i=0d to 3d Read PWMA_IN PWMB_IN PWMX_IN POLA POLB POLX Write Reset Read PWMAFS PWMBFS PWMXFS Write Reset PWMA_SMnOCTRL field descriptions Field...
Page 794 Memory Map and Registers PWMA_SMnOCTRL field descriptions (continued) Field Description 5–4 PWM_A Fault State PWMAFS These bits determine the fault state for the PWM_A output during fault conditions and STOP mode. It may also define the output state during WAIT and DEBUG modes depending on the settings of CTRL2[WAITEN] and CTRL2[DBGEN].
Page 795 Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM) PWMA_SMnSTS field descriptions Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. Registers Updated Flag This read-only flag is set when one of the INIT, VALx,FRACVALx, or CTRL[PRSC] registers has been written, which indicates potentially non-coherent data in the set of double buffered registers.
Page 796 Memory Map and Registers PWMA_SMnSTS field descriptions (continued) Field Description Capture Flag X0 CFX0 This bit is set when a capture event occurs on the Capture X0 circuit. This bit is cleared by writing a one to this bit position if DMAEN[CX0DE] is clear (non-DMA mode) or by the DMA done signal if DMAEN[CX0DE] is set (DMA mode).
Page 797 Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM) PWMA_SMnINTEN field descriptions (continued) Field Description Interrupt request disabled for STS[CFA1]. Interrupt request enabled for STS[CFA1]. Capture A 0 Interrupt Enable CA0IE This bit allows the STS[CFA0] flag to create an interrupt request to the CPU. Do not set both this bit and DMAEN[CA0DE].
Page 798 Memory Map and Registers 37.4.20 DMA Enable Register (PWMA_SMnDMAEN) Address: 4003_3000h base + 28h offset + (96d × i), where i=0d to 3d Read VALDE FAND Write Reset Read CAPTDE CA1DE CA0DE CB1DE CB0DE CX1DE CX0DE Write Reset PWMA_SMnDMAEN field descriptions Field Description 15–10...
Page 799 Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM) PWMA_SMnDMAEN field descriptions (continued) Field Description This read/write bit enables DMA read requests for the Capture A0 FIFO data when STS[CFA0] is set. Reset clears this bit. Do not set both this bit and INTEN[CA0IE]. Capture B1 FIFO DMA Enable CB1DE This read/write bit enables DMA read requests for the Capture B1 FIFO data when STS[CFB1] is set.
Page 800 Memory Map and Registers PWMA_SMnTCTRL field descriptions (continued) Field Description This bit selects which signal to bring out on the PWM's PWM_OUT_TRIG1 port. The output trigger port is often connected to routing logic on the chip. This control bit allows the PWMB output signal to be driven onto the output trigger port so it can be sent to the chip routing logic.
Page 801 Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM) PWMA_SMnDISMAP0 field descriptions (continued) Field Description Each of the four bits of this read/write field is one-to-one associated with the four FAULTx inputs of fault channel 0. The PWM_B output is turned off if there is a logic 1 on a FAULTx input and a 1 in the corresponding bit of this field.
Page 802 Memory Map and Registers 37.4.24 Deadtime Count Register 1 (PWMA_SMnDTCNT1) Deadtime operation applies only to complementary channel operation. The values written to the DTCNTx registers are in terms of IPBus clock cycles regardless of the setting of CTRL[PRSC] and/or CTRL2[CLK_SEL]. Reset sets the deadtime count registers to a default value of 0x07FF, selecting a deadtime of 2047 IPBus clock cycles.
Page 803 Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM) PWMA_SMnCAPTCTRLA field descriptions (continued) Field Description This field reflects the number of words in the Capture A1 FIFO. (FIFO depth is 1) 12–10 Capture A0 FIFO Word Count CA0CNT This field reflects the number of words in the Capture A0 FIFO. (FIFO depth is 1) 9–8 Capture A FIFOs Water Mark CFAWM...
Page 804 Memory Map and Registers PWMA_SMnCAPTCTRLA field descriptions (continued) Field Description If only one of the capture circuits is enabled, then captures continue indefinitely on the enabled capture circuit. One shot mode is selected. If both capture circuits are enabled, then capture circuit 0 is armed first after CAPTCTRLA[ARMA] is set.
Page 805 Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM) 37.4.27 Capture Control B Register (PWMA_SMnCAPTCTRLB) Address: 4003_3000h base + 38h offset + (96d × i), where i=0d to 3d Read CB1CNT CB0CNT CFBWM Write Reset Read EDGCNTB_ INP_SELB EDGB1 EDGB0 ONESHOTB ARMB Write Reset PWMA_SMnCAPTCTRLB field descriptions...
Page 806 Memory Map and Registers PWMA_SMnCAPTCTRLB field descriptions (continued) Field Description Capture falling edges Capture rising edges Capture any edge 3–2 Edge B 0 EDGB0 These bits control the input capture 0 circuitry by determining which input edges cause a capture event. Disabled Capture falling edges Capture rising edges...
Page 807 Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM) PWMA_SMnCAPTCOMPB field descriptions Field Description 15–8 Edge Counter B EDGCNTB This read-only field contains the edge counter value for the PWM_B input capture circuitry. EDGCMPB Edge Compare B This read/write field is the compare value associated with the edge counter for the PWM_B input capture circuitry.
Page 808 Memory Map and Registers PWMA_SMnCAPTCTRLX field descriptions (continued) Field Description Raw PWM_X input signal selected as source. Output of edge counter/compare selected as source. NOTE: When this bitfield is set to 1, the internal edge counter is enabled and the rising and/or falling edges specified by the CAPTCTRLX[EDGX0] and CAPTCTRLX[EDGX1] fields are ignored.
Page 809 Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM) 37.4.30 Capture Compare X Register (PWMA_SMnCAPTCOMPX) Address: 4003_3000h base + 3Eh offset + (96d × i), where i=0d to 3d Read EDGCNTX EDGCMPX Write Reset PWMA_SMnCAPTCOMPX field descriptions Field Description 15–8 Edge Counter X EDGCNTX This read-only field contains the edge counter value for the PWM_X input capture circuitry.
Page 810 Memory Map and Registers PWMA_SMnCVAL0CYC field descriptions Field Description 15–4 This field is reserved. Reserved This read-only field is reserved and always has the value 0. CVAL0CYC This read-only register stores the cycle number corresponding to the value captured in CVAL0. This register is incremented each time the counter is loaded with the INIT value at the end of a PWM modulo cycle.
Page 811 Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM) 37.4.35 Capture Value 2 Register (PWMA_SMnCVAL2) Address: 4003_3000h base + 48h offset + (96d × i), where i=0d to 3d Read CAPTVAL2 Write Reset PWMA_SMnCVAL2 field descriptions Field Description CAPTVAL2 This read-only register stores the value captured from the submodule counter. Exactly when this capture occurs is defined by CAPTCTRLA[EDGA0].
Page 812 Memory Map and Registers PWMA_SMnCVAL3 field descriptions Field Description CAPTVAL3 This read-only register stores the value captured from the submodule counter. Exactly when this capture occurs is defined by CAPTCTRLA[EDGA1]. Each capture increases the value of CAPTCTRLA[CA1CNT] by 1 until the maximum value is reached. Each read of this register decreases the value of CAPTCTRLA[CA1CNT] by 1 until 0 is reached.
Page 813 Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM) 37.4.40 Capture Value 4 Cycle Register (PWMA_SMnCVAL4CYC) Address: 4003_3000h base + 52h offset + (96d × i), where i=0d to 3d Read CVAL4CYC Write Reset PWMA_SMnCVAL4CYC field descriptions Field Description 15–4 This field is reserved. Reserved This read-only field is reserved and always has the value 0.
Page 814 Memory Map and Registers PWMA_SMnCVAL5CYC field descriptions Field Description 15–4 This field is reserved. Reserved This read-only field is reserved and always has the value 0. CVAL5CYC This read-only register stores the cycle number corresponding to the value captured in CVAL5. This register is incremented each time the counter is loaded with the INIT value at the end of a PWM modulo cycle.
Page 815 Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM) 37.4.45 Mask Register (PWMA_MASK) MASK is double buffered and does not take effect until a FORCE_OUT event occurs within the appropriate submodule. Reading MASK reads the buffered values and not necessarily the values currently in effect. This double buffering can be overridden by setting the UPDATE_MASK bits.
Page 816 Memory Map and Registers 37.4.46 Software Controlled Output Register (PWMA_SWCOUT) These bits are double buffered and do not take effect until a FORCE_OUT event occurs within the appropriate submodule. Reading these bits reads the buffered value and not necessarily the value currently in effect. Address: 4003_3000h base + 184h offset = 4003_3184h Read Write...
Page 817 Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM) PWMA_SWCOUT field descriptions (continued) Field Description Submodule 1 Software Controlled Output 23 SM1OUT23 This bit is only used when DTSRCSEL[SM1SEL23] is set to b10. It allows software control of which signal is supplied to the deadtime generator of that submodule. A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23.
Page 818 Memory Map and Registers PWMA_DTSRCSEL field descriptions (continued) Field Description Generated SM3PWM23 signal is used by the deadtime logic. Inverted generated SM3PWM23 signal is used by the deadtime logic. SWCOUT[SM3OUT23] is used by the deadtime logic. PWM3_EXTA signal is used by the deadtime logic. 13–12 Submodule 3 PWM45 Control Select SM3SEL45...
Page 819 Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM) PWMA_DTSRCSEL field descriptions (continued) Field Description 3–2 Submodule 0 PWM23 Control Select SM0SEL23 This field selects possible over-rides to the generated SM0PWM23 signal that will be passed to the deadtime logic upon the occurrence of a FORCE_OUT event in that submodule. Generated SM0PWM23 signal is used by the deadtime logic.
Page 820 Memory Map and Registers PWMA_MCTRL field descriptions (continued) Field Description 11–8 The four read/write bits of this field enable the clocks to the PWM generator of submodules 3-0, respectively. The corresponding MCTRL[RUN] bit must be set for each submodule that is using its input capture functions or is using the local reload as its reload source.
Page 821 Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM) PWMA_MCTRL2 field descriptions Field Description 15–2 This field is reserved. Reserved This read-only field is reserved and always has the value 0. MONPLL Monitor PLL State These bits are used to control disabling of the fractional delay block when the chip PLL is unlocked and/or missing its input reference.
Page 822 Memory Map and Registers PWMA_FCTRL field descriptions (continued) Field Description 11–8 Automatic Fault Clearing FAUTO The four read/write bits of this field select automatic or manual clearing of faults 3-0, respectively. A reset clears this field. Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the start of a half cycle or full cycle depending the state of FSTS[FFULL].
Page 823 Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM) PWMA_FSTS field descriptions (continued) Field Description These read/write bits are used to control the timing for re-enabling the PWM outputs after a fault condition. These bits apply to both automatic and manual clearing of a fault condition. NOTE: Both FHALF and FFULL can be set so that the fault recovery occurs at the start of a full cycle and at the start of a half cycle (as defined by VAL0).
Page 824 Memory Map and Registers FILT_PER x IPBus clock period). Note that even when the filter is enabled, there is a combinational path to disable the PWM outputs. This is to ensure rapid response to fault conditions and also to ensure fault response if the PWM module loses its clock. The latency induced by the filter will be seen in the time to set FSTS[FFLAG] and FSTS[FFPIN].
Page 825 Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM) 37.4.53 Fault Test Register (PWMA_FTST) Address: 4003_3000h base + 192h offset = 4003_3192h Read Write Reset Read FTEST Write Reset PWMA_FTST field descriptions Field Description 15–1 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Fault Test FTEST This read/write bit is used to simulate a fault condition.
Page 826: Functional Description
Functional Description PWMA_FCTRL2 field descriptions (continued) Field Description Setting these bits removes the combinational path and uses the filterred and latched fault signals as the fault source to disable the PWM outputs. This eliminates fault glitches from creating PWM output glitches but also increases the latency to respond to a real fault.
Page 827 Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM) VAL1 ($0100) VAL3 VAL5 VAL0 ($0000) VAL4 VAL2 INIT ($FF00) PWM_A PWM_B Figure 37-224. Center Aligned Example The submodule timers only count in the up direction and then reset to the INIT value. Instead of having a single value that determines pulse width, there are two values that must be specified: the turn on edge and the turn off edge.
Page 828: Edge Aligned Pwms
Functional Description alignment between the signals is not restricted to symmetry around the zero count value, as any other number would also work. However, centering on zero provides the greatest range in signed mode and also simplifies the calculations. 37.5.1.2 Edge Aligned PWMs When the turn on edge for each pulse is specified to be the INIT value, then edge aligned operation results, as the following figure shows.
Page 829 Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM) 37.5.1.3 Phase Shifted PWMs In the previous sections, the benefits of signed mode of operation were discussed in the context of simplifying the required software calculations by eliminating the requirement to bias up signed variables before applying them to the module. However, if numerical biases are applied to the turn on and turn off edges of different PWM signal, the signals will be phase shifted with respect to each other, as the following figure shows.
Page 830 Functional Description requirements of the transistors. Notice that the square wave on the right side of the H- Bridge is phase shifted compared to the left side of the H-Bridge. As a result, the transformer primary sees the bottom waveform across its terminals. The RMS value of this waveform is directly controlled by the amount of phase shift of the square waves.
Page 831: Double Switching Pwms
Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM) 37.5.1.4 Double Switching PWMs Double switching PWM output is supported to aid in single shunt current measurement and three phase reconstruction. This method support two independent rising edges and two independent falling edges per PWM cycle. The VAL2 and VAL3 registers are used to generate the even channel (labelled as PWM_A in the figure) while VAL4 and VAL5 are used to generate the odd channel.
Page 832 Functional Description complementary mode of operation, only two edge comparators are required to generate the output PWM signals for a given submodule. This means that the other comparators are free to perform other functions. In this example, the software does not need to quickly respond after the first conversion to set up other conversions that must occur in the same PWM cycle.
Page 833 Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM) Submodule0 counter (PWM generation) Submodule1 counter VAL5 VAL4 VAL3 VAL2 VAL1 VAL0 Output Triggers Figure 37-230. Multiple Output Triggers Over Several PWM Cycles 37.5.1.6 Enhanced Capture Capabilities (E-Capture) When a PWM pin is not being used for PWM generation, it can be used to perform input captures.
Page 834 Functional Description Figure 37-231. Capture Capabilities of the E-Capture Circuit When a submodule is being used for PWM generation, its timer counts up to the modulus value used to specify the PWM frequency and then is re-initialized. Therefore, using this timer for input captures on one of the other pins (for example, PWM_X) has limited utility since it does not count through all of the numbers and the timer reset represents a discontinuity in the 16 bit number range.
Page 835: Synchronous Switching Of Multiple Outputs
Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM) During deadtime, load inductance drives voltage with polarity that keeps inductive current flowing through diodes. PWM_A PWM_B to PWMX input Actual load voltage pulse width is measured Actual load voltage (for i+) Actual load voltage (for i-) Figure 37-232.
Page 836: Functional Details
Functional Description 37.5.2 Functional Details This section describes the implementation of various sections of the PWM in greater detail. The following figure is a high-level block diagram of output PWM generation. PWM_EXT_SYNC Clock Sources Clocking Counter Synchroni- zation Register Reload Logic PWM_EXTAn PWM_FAULTn...
Page 837: Register Reload Logic
Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM) To permit lower PWM frequencies, the prescaler produces the PWM clock frequency by dividing the IPBus clock frequency by 1-128. The prescaler bits, CTRL[PRSC], select the prescaler divisor. This prescaler is buffered and will not be used by the PWM generator until MCTRL[LDOK] is set and a new PWM reload cycle begins or CTRL[LDMOD] is set.
Page 838 Functional Description VAL1 INIT 16 bit Mod Compare comparator Submodule Clock 16 bit counter FORCE_OUT FRCEN Local Sync Processing Logic Master Reload Init Master Sync Master Sync (from submod0 only) PWM_EXT_SYNC INIT_SEL Figure 37-236. Submodule Timer Synchronization The Master Sync signal originates as the Local Sync from submodule0. If configured to do so, the timer period of any submodule can be locked to the period of the timer in submodule0.
Page 839: Pwm Generation
Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM) 37.5.2.4 PWM Generation Figure 37-237 illustrates how PWM generation is accomplished in each submodule. In each case, two comparators and associated VALx registers are utilized for each PWM output signal. One comparator and VALx register are used to control the turn-on edge, while a second comparator and VALx register control the turn-off edge.
Page 840: Output Compare Capabilities
Functional Description counter initialization, they can be used to modulate the duty cycle of the Local Sync signal, effectively turning it into an auxiliary PWM signal (PWM_X) assuming that the PWM_X pin is not being used for another function such as input capture or deadtime distortion correction.
Page 841: Force Out Logic
Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM) 37.5.2.6 Force Out Logic For each submodule, software can select between eight signal sources for the FORCE_OUT signal: local CTRL2[FORCE], the Master Force signal from submodule0, the local Reload signal, the Master Reload signal from submodule0, the Local Sync signal, the Master Sync signal from submodule0, the EXT_SYNC signal from on- or off- chip, or the EXT_FORCE signal from on- or off-chip depending on the chip architecture.
Page 842: Independent Or Complementary Channel Operation
Functional Description The local CTRL2[FORCE] signal of submodule0 can be broadcast as the Master Force signal to other submodules. This feature allows the CTRL2[FORCE] of submodule0 to synchronously update all of the submodule outputs at the same time. The EXT_FORCE signal originates from outside the PWM module from a source such as a timer or digital comparators in the Analog-to-Digital Converter.
Page 843 Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM) DTCNT0 PWM23 from Force Out logic rising start down edge counter PWM23 zero detect DBLPWM to Output DBLEN logic zero falling start down PWM45 edge counter detect IPOL PWM45 DTCNT1 INDEP Figure 37-240. Deadtime Insertion Logic While in the complementary mode, a PWM pair can be used to drive top/bottom transistors, as shown in the figure.
Page 844: Top/Bottom Correction
Functional Description When deadtime is inserted in complementary PWM signals connected to an inverter driving an inductive load, the PWM waveform on the inverter output will have a different duty cycle than what appears on the output pins of the PWM module. This results in a distortion in the voltage applied to the load.
Page 845 Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM) DESIRED LOAD VOLTAGE DEADTIME PWM TO TOP TRANSISTOR POSITIVE POSITIVE CURRENT CURRENT NEGATIVE CURRENT PWM TO BOTTOM TRANSISTOR POSITIVE CURRENT LOAD VOLTAGE NEGATIVE CURRENT LOAD VOLTAGE Figure 37-242. Deadtime Distortion During deadtime, load inductance distorts output voltage by keeping current flowing through the diodes.
Page 846: Manual Correction
Functional Description To correct deadtime distortion, software can decrease or increase the value in the appropriate VALx register. • In edge-aligned operation, decreasing or increasing the PWM value by a correction value equal to the deadtime typically compensates for deadtime distortion. •...
Page 847 Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM) DEADTIME PWM TO TOP TRANSISTOR POSITIVE CURRENT NEGATIVE CURRENT PWM TO BOTTOM TRANSISTOR LOAD VOLTAGE WITH HIGH POSITIVE CURRENT LOAD VOLTAGE WITH LOW POSITIVE CURRENT LOAD VOLTAGE WITH HIGH NEGATIVE CURRENT LOAD VOLTAGE WITH LOW NEGATIVE CURRENT T = DEADTIME INTERVAL BEFORE ASSERTION OF TOP PWM B = DEADTIME INTERVAL BEFORE ASSERTION OF BOTTOM PWM...
Page 848: Output Logic
Functional Description 37.5.2.9.1 Fractional Delay Logic with Micro-Edge Placement Block Using the micro-edge placer block requires that the IPBus clock to the PWM be set at a defined frequency. The micro-edge placer is powered up by setting FRCTRL[FRAC_PU]. Enable fine edge control on the various PWM edges by setting FRCTRL[FRACx_EN].
Page 849 Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM) OCTRL[POLA] and OCTRL[POLB] before enabling the output pins. A fault condition can result in the PWM output being tristated, forced to a logic 1, or forced to a logic 0 depending on the values programmed into the OCTRL[PWMxFS] fields. PWMAFS[1] Disable PWM_A...
Page 850 Functional Description dividing down high frequency signals for capture processing so that capture interrupts don't overwhelm the CPU. Also, this feature can be used to simply generate an interrupt after "n" events have been counted. CIE0 INP_SEL Pin Input Circuit 0 Capture reset 8 bit...
Page 851: Fault Protection
Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM) 37.5.2.12 Fault Protection Fault protection can control any combination of PWM output pins. Faults are generated by a logic one on any of the FAULTx pins. This polarity can be changed via FCTRL[FLVL]. Each FAULTx pin can be mapped arbitrarily to any of the PWM outputs.
Page 852 Functional Description NOCOMB0 DISA0 FAULT0 FILT NOCOMB1 DISA1 FAULT1 FILT NOCOMB2 DISA2 FAULT2 FILT NOCOMB3 DISA3 FAULT3 FILT DISABLE Wait Mode PWM_A WAITEN Debug Mode DBGEN Stop Mode Figure 37-247. Fault Decoder for PWM_A Table 37-224. Fault Mapping PWM Pin Controlling Register Bits PWM_A DISMAP0[DIS0A]...
Page 853: Fault Pin Filter
Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM) 37.5.2.12.1 Fault Pin Filter Each fault pin has a programmable filter that can be bypassed. The sampling period of the filter can be adjusted with FFILT[FILT_PER]. The number of consecutive samples that must agree before an input transition is recognized can be adjusted using FFILT[FILT_CNT].
Page 854 Functional Description Half Cycle COUNT FFPINx BIT OUTPUTS ENABLED DISABLED ENABL DISABLE ENABLED Figure 37-248. Automatic Fault Clearing 37.5.2.12.3 Manual Fault Clearing Clearing the automatic clearing mode bit, FCTRL[FAUTOx], configures faults from the FAULTx pin for manual clearing: • If the fault safety mode bits, FCTRL[FSAFEx], are clear, then PWM pins disabled by the FAULTx pins are enabled when: •...
Page 855: Pwm Generator Loading
Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM) COUNT FFPINx BIT ENABLED OUTPUTS ENABLED DISABLED FFLAGx CLEARED Figure 37-249. Manual Fault Clearing (FCTRL[FSAFE]=0) COUNT FFPINx BIT ENABLED OUTPUTS ENABLED DISABLED FFLAGx CLEARED Figure 37-250. Manual Fault Clearing (FCTRL[FSAFE]=1) Note Fault protection also applies during software output control when the SEL23 and SEL45 fields are set to select OUT23 and OUT45 bits or PWM_EXTA and PWM_EXTB.
Page 856: Load Enable
Functional Description 37.5.3.1 Load Enable MCTRL[LDOK] enables loading of the following PWM generator parameters: • The prescaler divisor—from CTRL[PRSC] • The PWM period and pulse width—from the INIT and VALx registers MCTRL[LDOK] allows software to finish calculating all of these PWM parameters so they can be synchronously updated.
Page 857: Reload Flag
Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM) Counter Reload Change to every to every four Reload Every two opportunity opportunities Frequency opportunities Figure 37-252. Half Cycle Reload Frequency Change Counter Reload Change Every two to every four to every to every two Reload opportunities opportunities...
Page 858 Resets 37.5.3.4 Reload Errors Whenever one of the VALx, FRACVALx, or CTRL[PRSC] registers is updated, the STS[RUF] flag is set to indicate that the data is not coherent. STS[RUF] will be cleared by a successful reload which consists of the reload signal while MCTRL[LDOK] is set. If STS[RUF] is set and MCTRL[LDOK] is clear when the reload signal occurs, a reload error has taken place and STS[REF] is set.
Page 859 Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM) 37.7 Interrupts Each of the submodules within the eFlexPWM module can generate an interrupt from several sources. The fault logic can also generate interrupts. The interrupt service routine (ISR) must check the related interrupt enables and interrupt flags to determine the actual cause of the interrupt.
Page 860 Table 37-225. Interrupt Summary (continued) Core Interrupt Interrupt Flag Interrupt Enable Name Description SM3STS[CFA1], SM3INTEN[CFA1IE], SM3STS[CFA0], SM3INTEN[CFA0IE], SM3STS[CFB1], SM3INTEN[CFB1IE], Submodule 3 input Input capture event has PWM_CAP3 capture interrupt occurred SM3STS[CFB0], SM3INTEN[CFB0IE], SM3STS[CFX1], SM3INTEN[CFX1IE], SM3STS[CFX0] SM3INTEN[CFX0IE Submodule 3 reload Reload event has PWM_RELOAD3 SM3STS[RF] SM3INTEN[RIE]...
Page 861 Chapter 37 Pulse Width Modulator A (PWMA/eFlexPWM) Table 37-226. DMA Summary (continued) DMA Request DMA Enable Name Description Submodule 0 SM0DMAEN[VALDE] SM0VALx write request SM0VALx registers need to be updated write request SM1 Capture FIFO X0 SM1DMAEN[CX0DE] SM1CVAL0 contains a value to be read read request SM1 Capture FIFO X! SM1DMAEN[CX1DE]...
Page 862 Table 37-226. DMA Summary (continued) DMA Request DMA Enable Name Description SM3 Capture FIFO B1 SM3DMAEN[CB1DE] SM3CVAL5 contains a value to be read read request SM3 Capture FIFO SM3DMAEN[CAPTDE] read request source Selects source of submodule3 read DMA request select Submodule 3 SM3DMAEN[VALDE] SM3VALx write request...
Page 863: Chapter 38 Programmable Delay Block (Pdb)
Chapter 38 Programmable Delay Block (PDB) 38.1 Chip-specific PDB information 38.1.1 PDB Instantiation This chip has two PDBs that primarily provide delayed triggering from the FTMs to the ADCs. Each PDB has one trigger output with four pre-trigger channels, four pulse output and one DAC trigger.
Page 864 Chip-specific PDB information Table 38-2. PDB0 Input Trigger Options (continued) PDB Trigger PDB Input 0001 CMP0_out 0010 CMP1_out 0011 CMP2_out 0100 PIT Ch 0 Output 0101 PIT Ch 1 Output 0110 PIT Ch 2 Output 0111 PIT Ch 3 Output 1000 FTM0 initialization trigger and channel triggers, as programmed in the FTM external trigger register (EXTTRIG)
Page 865 Chapter 38 Programmable Delay Block (PDB) Table 38-4. PDB1 Input Trigger Options (continued) PDB Trigger PDB Input 0010 CMP1_out 0011 CMP2_out 0100 PIT Ch 0 Output 0101 PIT Ch 1 Output 0110 PIT Ch 2 Output 0111 PIT Ch 3 Output 1000 FTM0 initialization trigger and channel triggers, as programmed in the FTM external trigger register (EXTTRIG)
Page 866: Pulse-Out Enable Register Implementation
Introduction 38.1.4 Pulse-Out Enable Register Implementation The following table shows the comparison of pulse-out enable register at the module and chip level. Table 38-5. PDB pulse-out enable register Register Module implementation Chip implementation POnEN 7:0 - POEN 0 - POEN[0] for CMP0 31:8 - Reserved 1 - POEN[1] for CMP1 2 - POEN[2] for CMP2...
Page 867 Chapter 38 Programmable Delay Block (PDB) 38.2.1 Features • Up to 15 trigger input sources and one software trigger source • Up to 8 configurable PDB channels for ADC hardware trigger • One PDB channel is associated with one ADC •...
Page 868: Back-To-Back Acknowledgment Connections
Introduction 38.2.2 Implementation In this section, the following letters refer to the number of output triggers: • N—Total available number of PDB channels. • n—PDB channel number, valid from 0 to N-1. • M—Total available pre-trigger per PDB channel. • m—Pre-trigger number, valid from 0 to M-1. •...
Page 869 Chapter 38 Programmable Delay Block (PDB) Ack 0 PDBCHnDLY0 Pre-trigger 0 BB[0], TOS[0] EN[0] Ch n pre-trigger 0 Ack m PDBCHnDLYm Pre-trigger m BB[m], TOS[m] EN[m] Ch n pre-trigger m Sequence Error Detection ERR[M - 1:0] Ch n trigger PDBMOD Control DACINTx DAC interval...
Page 870: Modes Of Operation
PDB signal descriptions 38.2.6 Modes of operation PDB ADC trigger operates in the following modes: • Disabled—Counter is off, all pre-trigger and trigger outputs are low if PDB is not in back-to-back operation of Bypass mode. • Debug—Counter is paused when processor is in Debug mode, and the counter for the DAC trigger is also paused in Debug mode.
Page 871 Chapter 38 Programmable Delay Block (PDB) PDB memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4003_1000 Status and Control register (PDB1_SC) 0000_0000h 38.4.1/872 4003_1004 Modulus register (PDB1_MOD) 0000_FFFFh 38.4.2/875 4003_1008 Counter register (PDB1_CNT) 0000_0000h 38.4.3/875 4003_100C Interrupt Delay register (PDB1_IDLY)
Page 872 Memory map and register definition PDB memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 38.4.13/ 4003_6190 Pulse-Out n Enable register (PDB0_POEN) 0000_0000h 38.4.14/ 4003_6194 Pulse-Out n Delay register (PDB0_PO0DLY) 0000_0000h 38.4.14/ 4003_6198 Pulse-Out n Delay register (PDB0_PO1DLY) 0000_0000h 38.4.14/...
Page 873 Chapter 38 Programmable Delay Block (PDB) PDBx_SC field descriptions (continued) Field Description 19–18 Load Mode Select LDMOD Selects the mode to load the MOD, IDLY, CHnDLYm, INTx, and POyDLY registers, after 1 is written to LDOK. The internal registers are loaded with the values from their buffers immediately after 1 is written to LDOK.
Page 874 Memory map and register definition PDBx_SC field descriptions (continued) Field Description 0000 Trigger-In 0 is selected. 0001 Trigger-In 1 is selected. 0010 Trigger-In 2 is selected. 0011 Trigger-In 3 is selected. 0100 Trigger-In 4 is selected. 0101 Trigger-In 5 is selected. 0110 Trigger-In 6 is selected.
Page 875 Chapter 38 Programmable Delay Block (PDB) PDBx_SC field descriptions (continued) Field Description Writing 1 to this bit updates the internal registers of MOD, IDLY, CHnDLYm, DACINTx,and POyDLY with the values written to their buffers. The MOD, IDLY, CHnDLYm, DACINTx, and POyDLY will take effect according to the LDMOD.
Page 876 Memory map and register definition PDBx_CNT field descriptions (continued) Field Description Contains the current value of the counter. 38.4.4 Interrupt Delay register (PDBx_IDLY) Address: Base address + Ch offset IDLY Reset PDBx_IDLY field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0.
Page 877 Chapter 38 Programmable Delay Block (PDB) PDBx_CHnC1 field descriptions (continued) Field Description set of configuration and results registers. Application code must enable only the back-to-back operation of the PDB pre-triggers at the leading of the back-to-back connection chain. PDB channel's corresponding pre-trigger back-to-back operation disabled. PDB channel's corresponding pre-trigger back-to-back operation enabled.
Page 878 Memory map and register definition PDBx_CHnS field descriptions (continued) Field Description one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 0’s to clear the sequence error flags.
Page 879 Chapter 38 Programmable Delay Block (PDB) 38.4.9 Channel n Delay 2 register (PDBx_CHnDLY2) Address: Base address + 20h offset + (40d × i), where i=0d to 0d Reset PDBx_CHnDLY2 field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. PDB Channel Delay These bits specify the delay value for the channel's corresponding pre-trigger.
Page 880 Memory map and register definition 38.4.11 DAC Interval Trigger n Control register (PDBx_DACINTCn) Address: Base address + 150h offset + (8d × i), where i=0d to 0d Reset Reset PDBx_DACINTCn field descriptions Field Description 31–2 This field is reserved. Reserved This read-only field is reserved and always has the value 0.
Page 881 Chapter 38 Programmable Delay Block (PDB) PDBx_DACINTn field descriptions (continued) Field Description These bits specify the interval value for DAC interval trigger. DAC interval trigger triggers DAC[1:0] update when the DAC interval counter is equal to the DACINT. Reading these bits returns the value of internal register that is effective for the current PDB cycle.
Page 882: Functional Description
Functional description 38.5 Functional description 38.5.1 PDB pre-trigger and trigger outputs The PDB contains a counter whose output is compared to several different digital values. If the PDB is enabled, then a trigger input event will reset the counter and make it start to count.
Page 883 Chapter 38 Programmable Delay Block (PDB) Trigger input event Ch n pre-trigger 0 Ch n pre-trigger 1 .... Ch n pre-trigger M Ch n trigger Figure 38-80. Pre-trigger and trigger outputs The delay in CHnDLYm register can be optionally bypassed, if CHnC1[TOS[m]] is cleared.
Page 884: Pdb Trigger Input Source Selection
Functional description When the PDB counter reaches the value set in IDLY register, the SC[PDBIF] flag is set. A PDB interrupt can be generated if SC[PDBIE] is set and SC[DMAEN] is cleared. If SC[DMAEN] is set, then the PDB requests a DMA transfer when the SC[PDBIF] flag is set.
Page 885: Updating The Delay Registers
Chapter 38 Programmable Delay Block (PDB) MOD, IDLY CHnDLY1 CHnDLY0 DACINTx x3 DACINTx x2 DACINTx counter Trigger input event .... DAC internal trigger x Ch n pre-trigger 0 Ch n pre-trigger 1 Ch n trigger PDB interrupt Figure 38-81.
Page 886 Functional description • PDB Modulus register (MOD) • PDB Interrupt Delay register (IDLY) • PDB Channel n Delay m register (CHnDLYm) • DAC Interval x register (DACINTx) • PDB Pulse-Out y Delay register (POyDLY) The internal registers of them are buffered and any values written to them are written first to their buffers.
Page 887: Application Information
Chapter 38 Programmable Delay Block (PDB) CHnDLY1 CHnDLY0 PDB counter SC[LDOK] Ch n pre-trigger 0 Ch n pre-trigger 1 Figure 38-83. Registers update with SC[LDMOD] = x1 38.5.6 Interrupts PDB can generate two interrupts: PDB interrupt and PDB sequence error interrupt. The following table summarizes the interrupts.
Page 888 Application information values of total peripheral clocks that can be detected are even values; if prescaler is set to 4 then the only values of total peripheral clocks that can be decoded as detected are mod(4) and so forth. If the applications need a really long delay value and use a prescaler set to 128, then the resolution would be limited to 128 peripheral clock cycles.
Page 889: Chapter 39 Flextimer Module (Ftm)
Chapter 39 FlexTimer Module (FTM) 39.1 Chip-specific FTM information 39.1.1 Instantiation Information This device contains three FlexTimer modules. The following table shows how these modules are configured. This adheres to Kinetis K series FTM instantiations. Table 39-1. FTM Instantiations FTM instance Number of channels Features/usage FTM0...
Page 890: Fixed Frequency Clock
Chip-specific FTM information • FTM_CLKIN0 can provide an external input clock to all or either of FTM0,FTM1 and FTM3 • FTM_CLKIN1 can provide an external input clock to all or either of FTM0,FTM1 and FTM3 • FTM_CLKIN2 can provide an external input clock to all or either of FTM0,FTM1 and FTM3 39.1.3 Fixed frequency clock The fixed frequency clock for each FTM is MCGFFCLK.
Page 891: Ftm Hardware Triggers
Chapter 39 FlexTimer Module (FTM) 39.1.6 FTM Hardware Triggers The FTM input synchronization hardware triggers are connected in the chip as follows: • FTM0 hardware trigger 0 = FTM0_SYNCBIT of SIM_OPTx register, CMP0 Output or FTM1 Match output. • FTM0 hardware trigger 1 = PDB0 channel 1 trigger Output or FTM1 Match output •...
Page 892: Ftm Global Time Base
Chip-specific FTM information FTM0_CH2 event output to DMAMUX source 26 FTM0_CH3 event output to DMAMUX source 27 FTM0_CH4 event output to DMAMUX source 28 FTM0_CH5 event output to DMAMUX source 29 FTM0_CH6 event output to DMAMUX source 30 FTM0_CH7 event output to DMAMUX source 31 FTM1 has 2 channels of trigger capability which are ORed together to force an output trigger.
Page 893: Ftm Bdm And Debug Halt Mode
Chapter 39 FlexTimer Module (FTM) FTM1 CONF Register GTBEOUT = 0 FTM0 FTM Counter GTBEEN = 1 CONF Register gtb_in gtb_in GTBEOUT = 1 FTM Counter GTBEEN = 1 FTM3 gtb_out CONF Register GTBEOUT = 0 FTM Counter GTBEEN = 1 gtb_in Figure 39-1.
Page 894 Introduction Several key enhancements are made: • Signed up counter • Deadtime insertion hardware • Fault control inputs • Enhanced triggering functionality • Initialization and polarity control All of the features common with the TPM have fully backwards compatible register assignments.
Page 895 Chapter 39 FlexTimer Module (FTM) • It can be a free-running counter or a counter with initial and final value • The counting can be up or up-down • Each channel can be configured for input capture, output compare, or edge-aligned PWM mode •...
Page 896: Modes Of Operation
Introduction • Dual edge capture for pulse and period width measurement • Quadrature decoder with input filters, relative position counting, and interrupt on position count or capture of position count on external event 39.2.3 Modes of operation When the MCU is in an active BDM mode, the FTM temporarily suspends all counting until the MCU returns to normal user operating mode.
Page 897 Chapter 39 FlexTimer Module (FTM) CLKS FTMEN QUADEN no clock selected (FTM counter disable) system clock fixed frequency clock prescaler external clock synchronizer (1, 2, 4, 8, 16, 32, 64 or 128) phase A Quadrature decoder phase B QUADEN CPWMS CAPTEST INITTRIGEN initialization...
Page 898: Ftm Signal Descriptions
FTM signal descriptions 39.3 FTM signal descriptions Table 39-2 shows the user-accessible signals for the FTM. Table 39-2. FTM signal descriptions Signal Description Function EXTCLK External clock. FTM external The external clock input signal is used as the FTM counter clock can be selected to drive clock if selected by CLKS[1:0] bits in the SC register.
Page 899 Chapter 39 FlexTimer Module (FTM) Note Do not write in the region from the CNTIN register through the PWMLOAD register when FTMEN = 0. NOTE The number of channels supported can vary for each instance of the FTM module on a chip. See the chip-specific FTM information to see how many channels are supported for each module instance.
Page 900 Memory map and register definition FTM memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4002_6050 Capture And Compare Status (FTM3_STATUS) 0000_0000h 39.4.9/911 39.4.10/ 4002_6054 Features Mode Selection (FTM3_MODE) 0000_0004h 39.4.11/ 4002_6058 Synchronization (FTM3_SYNC) 0000_0000h 39.4.12/ 4002_605C Initial State For Channels Output (FTM3_OUTINIT)
Page 901 Chapter 39 FlexTimer Module (FTM) FTM memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4003_8018 Channel (n) Value (FTM0_C1V) 0000_0000h 39.4.7/910 4003_801C Channel (n) Status And Control (FTM0_C2SC) 0000_0000h 39.4.6/907 4003_8020 Channel (n) Value (FTM0_C2V) 0000_0000h 39.4.7/910 4003_8024...
Page 902 Memory map and register definition FTM memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 39.4.23/ 4003_8088 FTM Fault Input Polarity (FTM0_FLTPOL) 0000_0000h 39.4.24/ 4003_808C Synchronization Configuration (FTM0_SYNCONF) 0000_0000h 39.4.25/ 4003_8090 FTM Inverting Control (FTM0_INVCTRL) 0000_0000h 39.4.26/ 4003_8094...
Page 903 Chapter 39 FlexTimer Module (FTM) FTM memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 39.4.15/ 4003_9068 Deadtime Insertion Control (FTM1_DEADTIME) 0000_0000h 39.4.16/ 4003_906C FTM External Trigger (FTM1_EXTTRIG) 0000_0000h 39.4.17/ 4003_9070 Channels Polarity (FTM1_POL) 0000_0000h 39.4.18/ 4003_9074...
Page 904 Memory map and register definition 39.4.3 Status And Control (FTMx_SC) SC contains the overflow status flag and control bits used to configure the interrupt enable, FTM configuration, clock source, and prescaler factor. These controls relate to all channels within this module. Address: Base address + 0h offset Reset TOIE...
Page 905 Chapter 39 FlexTimer Module (FTM) FTMx_SC field descriptions (continued) Field Description Timer Overflow Interrupt Enable TOIE Enables FTM overflow interrupts. Disable TOF interrupts. Use software polling. Enable TOF interrupts. An interrupt is generated when TOF equals one. Center-Aligned PWM Select CPWMS Selects CPWM mode.
Page 906 Memory map and register definition Address: Base address + 4h offset COUNT Reset FTMx_CNT field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. COUNT Counter Value 39.4.5 Modulo (FTMx_MOD) The Modulo register contains the modulo value for the FTM counter.
Page 907 Chapter 39 FlexTimer Module (FTM) 39.4.6 Channel (n) Status And Control (FTMx_CnSC) CnSC contains the channel-interrupt-status flag and control bits used to configure the interrupt enable, channel configuration, and pin function. Table 39-71. Mode, edge, and level selection DECAPEN COMBINE CPWMS MSnB:MSnA ELSnB:ELSnA...
Page 908 Memory map and register definition Table 39-71. Mode, edge, and level selection (continued) DECAPEN COMBINE CPWMS MSnB:MSnA ELSnB:ELSnA Mode Configuration See the Dual Edge One-Shot following table Capture Capture mode (Table 39-9). Continuous Capture mode Table 39-72. Dual Edge Capture mode — edge polarity selection ELSnB ELSnA Channel Port Enable...
Page 909 Chapter 39 FlexTimer Module (FTM) FTMx_CnSC field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Channel Flag Set by hardware when an event occurs on the channel. CHF is cleared by reading the CSC register while CHnF is set and then writing a 0 to the CHF bit.
Page 910 Memory map and register definition 39.4.7 Channel (n) Value (FTMx_CnV) These registers contain the captured FTM counter value for the input modes or the match value for the output modes. In Input Capture, Capture Test, and Dual Edge Capture modes, any write to a CnV register is ignored.
Page 911 Chapter 39 FlexTimer Module (FTM) Address: Base address + 4Ch offset Reserved INIT Reset FTMx_CNTIN field descriptions Field Description 31–16 This field is reserved. Reserved INIT Initial Value Of The FTM Counter 39.4.9 Capture And Compare Status (FTMx_STATUS) The STATUS register contains a copy of the status flag CHnF bit in CnSC for each FTM channel for software convenience.
Page 912 Memory map and register definition Reset FTMx_STATUS field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Channel 7 Flag CH7F See the register description. No channel event has occurred. A channel event has occurred.
Page 913 Chapter 39 FlexTimer Module (FTM) FTMx_STATUS field descriptions (continued) Field Description No channel event has occurred. A channel event has occurred. Channel 1 Flag CH1F See the register description. No channel event has occurred. A channel event has occurred. Channel 0 Flag CH0F See the register description.
Page 914 Memory map and register definition FTMx_MODE field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Fault Interrupt Enable FAULTIE Enables the generation of an interrupt when a fault is detected by FTM and the FTM fault control is enabled.
Page 915 Chapter 39 FlexTimer Module (FTM) FTMx_MODE field descriptions (continued) Field Description TPM compatibility. Free running counter and synchronization compatible with TPM. Free running counter and synchronization are different from TPM behavior. 39.4.11 Synchronization (FTMx_SYNC) This register configures the PWM synchronization. A synchronization event can perform the synchronized update of MOD, CV, and OUTMASK registers with the value of their write buffer and the FTM counter initialization.
Page 916 Memory map and register definition Reset FTMx_SYNC field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. PWM Synchronization Software Trigger SWSYNC Selects the software trigger as the PWM synchronization trigger. The software trigger happens when a 1 is written to SWSYNC bit.
Page 917 Chapter 39 FlexTimer Module (FTM) FTMx_SYNC field descriptions (continued) Field Description Maximum Loading Point Enable CNTMAX Selects the maximum loading point to PWM synchronization. See Boundary cycle and loading points. If CNTMAX is 1, the selected loading point is when the FTM counter reaches its maximum value (MOD register).
Page 918 Memory map and register definition FTMx_OUTINIT field descriptions (continued) Field Description Selects the value that is forced into the channel output when the initialization occurs. The initialization value is 0. The initialization value is 1. Channel 5 Output Initialization Value CH5OI Selects the value that is forced into the channel output when the initialization occurs.
Page 919 Chapter 39 FlexTimer Module (FTM) Any write to the OUTMASK register, stores the value in its write buffer. The register is updated with the value of its write buffer according to synchronization. Address: Base address + 60h offset Reset Reset FTMx_OUTMASK field descriptions Field Description...
Page 920 Memory map and register definition FTMx_OUTMASK field descriptions (continued) Field Description Channel output is not masked. It continues to operate normally. Channel output is masked. It is forced to its inactive state. Channel 2 Output Mask CH2OM Defines if the channel output is masked or unmasked. Channel output is not masked.
Page 921 Chapter 39 FlexTimer Module (FTM) FTMx_COMBINE field descriptions Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. Fault Control Enable For n = 6 FAULTEN3 Enables the fault control in channels (n) and (n+1). This field is write protected.
Page 922 Memory map and register definition FTMx_COMBINE field descriptions (continued) Field Description Combine Channels For n = 6 COMBINE3 Enables the combine feature for channels (n) and (n+1). This field is write protected. It can be written only when MODE[WPDIS] = 1. Channels (n) and (n+1) are independent.
Page 923 Chapter 39 FlexTimer Module (FTM) FTMx_COMBINE field descriptions (continued) Field Description Enables Complementary mode for the combined channels. In Complementary mode the channel (n+1) output is the inverse of the channel (n) output. This field is write protected. It can be written only when MODE[WPDIS] = 1. The channel (n+1) output is the same as the channel (n) output.
Page 924 Memory map and register definition FTMx_COMBINE field descriptions (continued) Field Description This field is write protected. It can be written only when MODE[WPDIS] = 1. The Dual Edge Capture mode in this pair of channels is disabled. The Dual Edge Capture mode in this pair of channels is enabled. Complement Of Channel (n) For n = 2 COMP1 Enables Complementary mode for the combined channels.
Page 925 Chapter 39 FlexTimer Module (FTM) FTMx_COMBINE field descriptions (continued) Field Description Dual Edge Capture Mode Enable For n = 0 DECAPEN0 Enables the Dual Edge Capture mode in the channels (n) and (n+1). This bit reconfigures the function of MSnA, ELSnB:ELSnA and ELS(n+1)B:ELS(n+1)A bits in Dual Edge Capture mode according to Table 39-8.
Page 926 Memory map and register definition FTMx_DEADTIME field descriptions (continued) Field Description Divide the system clock by 4. Divide the system clock by 16. DTVAL Deadtime Value Selects the deadtime insertion value for the deadtime counter. The deadtime counter is clocked by a scaled version of the system clock.
Page 927 Chapter 39 FlexTimer Module (FTM) Reserved Reset FTMx_EXTTRIG field descriptions Field Description 31–8 This field is reserved. Reserved Channel Trigger Flag TRIGF Set by hardware when a channel trigger is generated. Clear TRIGF by reading EXTTRIG while TRIGF is set and then writing a 0 to TRIGF. Writing a 1 to TRIGF has no effect. If another channel trigger is generated before the clearing sequence is completed, the sequence is reset so TRIGF remains set after the clear sequence is completed for the earlier TRIGF.
Page 928 Memory map and register definition FTMx_EXTTRIG field descriptions (continued) Field Description Enables the generation of the channel trigger when the FTM counter is equal to the CnV register. The generation of the channel trigger is disabled. The generation of the channel trigger is enabled. Channel 4 Trigger Enable CH4TRIG Enables the generation of the channel trigger when the FTM counter is equal to the CnV register.
Page 929 Chapter 39 FlexTimer Module (FTM) FTMx_POL field descriptions Field Description 31–8 This field is reserved. Reserved Channel 7 Polarity POL7 Defines the polarity of the channel output. This field is write protected. It can be written only when MODE[WPDIS] = 1. The channel polarity is active high.
Page 930 Memory map and register definition FTMx_POL field descriptions (continued) Field Description The channel polarity is active high. The channel polarity is active low. Channel 0 Polarity POL0 Defines the polarity of the channel output. This field is write protected. It can be written only when MODE[WPDIS] = 1. The channel polarity is active high.
Page 931 Chapter 39 FlexTimer Module (FTM) FTMx_FMS field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Fault Detection Flag FAULTF Represents the logic OR of the individual FAULTFj bits where j = 3, 2, 1, 0. Clear FAULTF by reading the FMS register while FAULTF is set and then writing a 0 to FAULTF while there is no existing fault condition at the enabled fault inputs.
Page 932 Memory map and register definition FTMx_FMS field descriptions (continued) Field Description If another fault condition is detected at the corresponding fault input before the clearing sequence is completed, the sequence is reset so FAULTF2 remains set after the clearing sequence is completed for the earlier fault condition.
Page 933 Chapter 39 FlexTimer Module (FTM) Address: Base address + 78h offset Reserved CH3FVAL CH2FVAL CH1FVAL CH0FVAL Reset FTMx_FILTER field descriptions Field Description 31–16 This field is reserved. Reserved 15–12 Channel 3 Input Filter CH3FVAL Selects the filter value for the channel input. The filter is disabled when the value is zero.
Page 934 Memory map and register definition FTMx_FLTCTRL field descriptions Field Description 31–12 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 11–8 Fault Input Filter FFVAL Selects the filter value for the fault inputs. The fault filter is disabled when the value is zero.
Page 935 Chapter 39 FlexTimer Module (FTM) FTMx_FLTCTRL field descriptions (continued) Field Description Fault Input 1 Enable FAULT1EN Enables the fault input. This field is write protected. It can be written only when MODE[WPDIS] = 1. Fault input is disabled. Fault input is enabled. Fault Input 0 Enable FAULT0EN Enables the fault input.
Page 936 Memory map and register definition 39.4.21 Quadrature Decoder Control And Status (FTMx_QDCTRL) This register has the control and status bits for the Quadrature Decoder mode. Address: Base address + 80h offset Reset Reset FTMx_QDCTRL field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0.
Page 937 Chapter 39 FlexTimer Module (FTM) FTMx_QDCTRL field descriptions (continued) Field Description Phase B Input Filter Enable PHBFLTREN Enables the filter for the quadrature decoder phase B input. The filter value for the phase B input is defined by the CH1FVAL field of FILTER. The phase B filter is also disabled when CH1FVAL is zero. Phase B input filter is disabled.
Page 938 Memory map and register definition 39.4.22 Configuration (FTMx_CONF) This register selects the number of times that the FTM counter overflow should occur before the TOF bit to be set, the FTM behavior in BDM modes, the use of an external global time base, and the global time base signal generation.
Page 939 Chapter 39 FlexTimer Module (FTM) FTMx_CONF field descriptions (continued) Field Description Selects the ratio between the number of counter overflows to the number of times the TOF bit is set. NUMTOF = 0: The TOF bit is set for each counter overflow. NUMTOF = 1: The TOF bit is set for the first counter overflow but not for the next overflow.
Page 940 Memory map and register definition FTMx_FLTPOL field descriptions (continued) Field Description The fault input polarity is active high. A 1 at the fault input indicates a fault. The fault input polarity is active low. A 0 at the fault input indicates a fault. Fault Input 1 Polarity FLT1POL Defines the polarity of the fault input.
Page 941 Chapter 39 FlexTimer Module (FTM) FTMx_SYNCONF field descriptions (continued) Field Description Software output control synchronization is activated by a hardware trigger. HWSOC A hardware trigger does not activate the SWOCTRL register synchronization. A hardware trigger activates the SWOCTRL register synchronization. Inverting control synchronization is activated by a hardware trigger.
Page 942 Memory map and register definition FTMx_SYNCONF field descriptions (continued) Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. SWOCTRL Register Synchronization SWOC SWOCTRL register is updated with its buffer value at all rising edges of system clock. SWOCTRL register is updated with its buffer value by the PWM synchronization.
Page 943 Chapter 39 FlexTimer Module (FTM) Reset FTMx_INVCTRL field descriptions Field Description 31–4 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Pair Channels 3 Inverting Enable INV3EN Inverting is disabled. Inverting is enabled. Pair Channels 2 Inverting Enable INV2EN Inverting is disabled.
Page 944 Memory map and register definition Address: Base address + 94h offset Reset Reset FTMx_SWOCTRL field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Channel 7 Software Output Control Value CH7OCV The software output control forces 0 to the channel output.
Page 945 Chapter 39 FlexTimer Module (FTM) FTMx_SWOCTRL field descriptions (continued) Field Description The software output control forces 0 to the channel output. The software output control forces 1 to the channel output. Channel 7 Software Output Control Enable CH7OC The channel output is not affected by software output control. The channel output is affected by software output control.
Page 946 Memory map and register definition 39.4.27 FTM PWM Load (FTMx_PWMLOAD) Enables the loading of the MOD, CNTIN, C(n)V, and C(n+1)V registers with the values of their write buffers when the FTM counter changes from the MOD register value to its next value or when a channel (j) match occurs.
Page 947: Functional Description
Chapter 39 FlexTimer Module (FTM) FTMx_PWMLOAD field descriptions (continued) Field Description Channel 4 Select CH4SEL Do not include the channel in the matching process. Include the channel in the matching process. Channel 3 Select CH3SEL Do not include the channel in the matching process. Include the channel in the matching process.
Page 948: Counter Clock Source
Functional description FTM counting is up. Channel (n) is in high-true EPWM mode. PS[2:0] = 001 CNTIN = 0x0000 MOD = 0x0004 CnV = 0x0002 prescaler counter FTM counter channel (n) output counter channel (n) channel (n) counter counter channel (n) overflow match match...
Page 949 Chapter 39 FlexTimer Module (FTM) 39.5.2 Prescaler The selected counter clock source passes through a prescaler that is a 7-bit counter. The value of the prescaler is selected by the PS[2:0] bits. The following figure shows an example of the prescaler counter and FTM counter. FTM counting is up.
Page 950 Functional description The FTM period when using up counting is (MOD – CNTIN + 0x0001) × period of the FTM counter clock. The TOF bit is set when the FTM counter changes from MOD to CNTIN. FTM counting is up. CNTIN = 0xFFFC (in two's complement is equal to -4) MOD = 0x0004 -4 -3 -2 -1...
Page 951 Chapter 39 FlexTimer Module (FTM) FTM counting is up CNTIN = 0x0000 MOD = 0x0004 FTM counter TOF bit set TOF bit set TOF bit set TOF bit period of FTM counter clock period of counting = (MOD - CNTIN + 0x0001) x period of FTM counter clock = (MOD + 0x0001) x period of FTM counter clock Figure 39-170.
Page 952: Up-Down Counting
Functional description FTM counting is up MOD = 0x0005 CNTIN = 0x0015 load of CNTIN load of CNTIN FTM counter 0xFFFE 0xFFFF 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0015 0x0016 0x0005 0x0015 0x0016 TOF bit set TOF bit set TOF bit Figure 39-171.
Page 953: Free Running Counter
Chapter 39 FlexTimer Module (FTM) FTM counting is up-down CNTIN = 0x0000 MOD = 0x0004 FTM counter TOF bit set TOF bit set TOF bit period of FTM counter clock period of counting = 2 x (MOD - CNTIN) x period of FTM counter clock = 2 x MOD x period of FTM counter clock Figure 39-172.
Page 954: Counter Reset
Functional description • FTMEN = 1 • QUADEN = 0 • CPWMS = 0 • CNTIN = 0x0000, and • MOD = 0xFFFF 39.5.3.4 Counter reset Any one of the following cases resets the FTM counter to the value in the CNTIN register and the channels output to its initial value, except for channels in Output Compare mode.
Page 955: Input Capture Mode
Chapter 39 FlexTimer Module (FTM) FTM counter NUMTOF[4:0] 0x00 TOF counter 0x00 set TOF bit Figure 39-175. Periodic TOF when NUMTOF = 0x00 39.5.4 Input Capture mode The Input Capture mode is selected when: • DECAPEN = 0 • COMBINE = 0 •...
Page 956: Filter For Input Capture Mode
Functional description was rising edge selected? is filter enabled? channel (n) interrupt CHnIE CHnF synchronizer rising edge channel (n) input edge detector Filter* system clock falling edge was falling edge selected? * Filtering function is only available in the inputs of channel 0, 1, 2, and 3 FTM counter Figure 39-176.
Page 957: Ftm Counter Reset In Input Capture Mode
Chapter 39 FlexTimer Module (FTM) If the opposite edge appears on the input signal before it can be validated, the counter is reset. At the next input transition, the counter starts counting again. Any pulse that is shorter than the minimum value selected by CHnFVAL[3:0] (× 4 system clocks) is regarded as a glitch and is not passed on to the edge detector.
Page 958: Output Compare Mode
Functional description system clock 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x00 0x01 0x02 0x03 channel (n) input CHnF bit 0x27 C(n)V selected channel (n) input event: rising edge NOTE Channel (n) input after its synchronizer and filter MOD = 0xFFFF CNTIN = 0x0000 PS[2:0] = 3'b000 ICRST = 1'b1...
Page 959: Edge-Aligned Pwm (Epwm) Mode
Chapter 39 FlexTimer Module (FTM) MOD = 0x0005 CnV = 0x0003 channel (n) counter channel (n) counter counter overflow match overflow match overflow previous value channel (n) output CHnF bit previous value TOF bit Figure 39-180. Example of the Output Compare mode when the match toggles the channel output MOD = 0x0005 CnV = 0x0003...
Page 960 Functional description • DECAPEN = 0 • COMBINE = 0 • CPWMS = 0, and • MSnB = 1 The EPWM period is determined by (MOD − CNTIN + 0x0001) and the pulse width (duty cycle) is determined by (CnV − CNTIN). The CHnF bit is set and the channel (n) interrupt is generated if CHnIE = 1 at the channel (n) match (FTM counter = CnV), that is, at the end of the pulse width.
Page 961: Center-Aligned Pwm (Cpwm) Mode
Chapter 39 FlexTimer Module (FTM) MOD = 0x0008 CnV = 0x0005 counter channel (n) counter overflow match overflow channel (n) output previous value CHnF bit TOF bit Figure 39-185. EPWM signal with ELSnB:ELSnA = X:1 If (CnV = 0x0000), then the channel (n) output is a 0% duty cycle EPWM signal and CHnF bit is not set even when there is the channel (n) match.
Page 962 Functional description The CHnF bit is set and channel (n) interrupt is generated (if CHnIE = 1) at the channel (n) match (FTM counter = CnV) when the FTM counting is down (at the begin of the pulse width) and when the FTM counting is up (at the end of the pulse width). This type of PWM signal is called center-aligned because the pulse width centers for all channels are aligned with the value of CNTIN.
Page 963: Combine Mode
Chapter 39 FlexTimer Module (FTM) counter counter MOD = 0x0008 overflow overflow CnV = 0x0005 channel (n) match in channel (n) match in channel (n) match in down counting up counting down counting channel (n) output CHnF bit previous value TOF bit Figure 39-188.
Page 964 Functional description If (ELSnB:ELSnA = 1:0), then the channel (n) output is forced low at the beginning of the period (FTM counter = CNTIN) and at the channel (n+1) match (FTM counter = C(n +1)V). It is forced high at the channel (n) match (FTM counter = C(n)V). See the following figure.
Page 965 Chapter 39 FlexTimer Module (FTM) FTM counter MOD = C(n+1)V C(n)V CNTIN channel (n) output with ELSnB:ELSnA = 1:0 channel (n) output with ELSnB:ELSnA = X:1 Figure 39-191. Channel (n) output if (CNTIN < C(n)V < MOD) and (C(n+1)V = MOD) FTM counter C(n+1)V C(n)V = CNTIN...
Page 966 Functional description FTM counter C(n+1)V C(n)V = CNTIN not fully 100% duty cycle channel (n) output with ELSnB:ELSnA = 1:0 channel (n) output not fully 0% duty cycle with ELSnB:ELSnA = X:1 Figure 39-194. Channel (n) output if (C(n)V = CNTIN) and (CNTIN < C(n+1)V < MOD) and (C(n+1)V is Almost Equal to MOD) FTM counter C(n+1)V...
Page 967 Chapter 39 FlexTimer Module (FTM) FTM counter C(n+1)V = C(n)V CNTIN channel (n) output 0% duty cycle with ELSnB:ELSnA = 1:0 channel (n) output 100% duty cycle with ELSnB:ELSnA = X:1 Figure 39-196. Channel (n) output if (CNTIN < C(n)V < MOD) and (CNTIN < C(n+1)V < MOD) and (C(n)V = C(n+1)V) FTM counter C(n)V =...
Page 968 Functional description FTM counter C(n)V C(n+1)V CNTIN channel (n) match is ignored channel (n) output 0% duty cycle with ELSnB:ELSnA = 1:0 channel (n) output 100% duty cycle with ELSnB:ELSnA = X:1 Figure 39-199. Channel (n) output if (CNTIN < C(n)V < MOD) and (CNTIN < C(n+1)V < MOD) and (C(n)V >...
Page 969 Chapter 39 FlexTimer Module (FTM) FTM counter C(n)V CNTIN C(n+1)V channel (n) output with ELSnB:ELSnA = 1:0 channel (n) output with ELSnB:ELSnA = X:1 Figure 39-201. Channel (n) output if (C(n+1)V < CNTIN) and (CNTIN < C(n)V < MOD) FTM counter C(n)V C(n+1)V CNTIN...
Page 970: Asymmetrical Pwm
Functional description FTM counter C(n+1)V C(n)V CNTIN channel (n) output with ELSnB:ELSnA = 1:0 channel (n) output with ELSnB:ELSnA = X:1 Figure 39-203. Channel (n) output if (C(n+1)V > MOD) and (CNTIN < C(n)V < MOD) FTM counter C(n+1)V MOD = C(n)V CNTIN channel (n) output not fully 0% duty cycle...
Page 971: Registers Updated From Write Buffers
Chapter 39 FlexTimer Module (FTM) • QUADEN = 0 • DECAPEN = 0 • COMP = 1 In Complementary mode, the channel (n+1) output is the inverse of the channel (n) output. So, the channel (n+1) output is the same as the channel (n) output when: •...
Page 972: Cntin Register Update
Functional description 39.5.10.1 CNTIN register update The following table describes when CNTIN register is updated: Table 39-244. CNTIN register update When Then CNTIN register is updated CLKS[1:0] = 0:0 When CNTIN register is written, independent of FTMEN bit. • FTMEN = 0, or At the next system clock after CNTIN was written.
Page 973: Pwm Synchronization
Chapter 39 FlexTimer Module (FTM) Table 39-246. CnV register update (continued) When Then CnV register is updated • If the selected mode is Output Compare, then CnV register is updated on the next FTM counter change, end of the prescaler counting, after CnV register was written.
Page 974: Software Trigger
Functional description In this case, if two or more hardware triggers are enabled (for example, TRIG0 and TRIG1 = 1) and only trigger 1 event occurs, then only TRIG1 bit is cleared. If a trigger n event occurs together with a write setting TRIGn bit, then the synchronization is initiated, but TRIGn bit remains set due to the write operation.
Page 975: Boundary Cycle And Loading Points
Chapter 39 FlexTimer Module (FTM) If SYNCMODE = 1 then the SWSYNC bit is also cleared by FTM according to the SWRSTCNT bit. If SWRSTCNT = 0 then SWSYNC bit is cleared at the next selected loading point after that the software trigger event occurred; see the following figure. If SWRSTCNT = 1 then SWSYNC bit is cleared when the software trigger event occurs.
Page 976: Mod Register Synchronization
Functional description loading points if CNTMAX = 1 or CNTMIN = 1 CNT = MOD -> CNTIN up counting mode loading points if CNTMAX = 1 CNT = (MOD - 0x0001) -> MOD up-down counting mode CNT = (CNTIN + 0x0001) -> CNTIN loading points if CNTMIN = 1 Figure 39-209.
Page 977 Chapter 39 FlexTimer Module (FTM) begin legacy SYNCMODE PWM synchronization bit ? enhanced PWM synchronization MOD register is MOD register is updated by software trigger updated by hardware trigger SWWRBUF HWWRBUF bit ? bit ? hardware software trigger trigger TRIGn SWSYNC bit ? bit ?
Page 978 Functional description loading point. If the trigger event was a hardware trigger, then the trigger enable bit (TRIGn) is cleared according to Hardware trigger. Examples with software and hardware triggers follow. system clock write 1 to SWSYNC bit SWSYNC bit software trigger event selected loading point MOD register is updated...
Page 979 Chapter 39 FlexTimer Module (FTM) system clock write 1 to SWSYNC bit SWSYNC bit software trigger event MOD register is updated Figure 39-213. MOD synchronization with (SYNCMODE = 0), (PWMSYNC = 0), (REINIT = 1), and software trigger was used system clock write 1 to TRIG0 bit TRIG0 bit...
Page 980: Cntin Register Synchronization
Functional description 39.5.11.5 CNTIN register synchronization The CNTIN register synchronization updates the CNTIN register with its buffer value. This synchronization is enabled if (FTMEN = 1), (SYNCMODE = 1), and (CNTINC = 1). The CNTIN register synchronization can be done only by the enhanced PWM synchronization (SYNCMODE = 1).
Page 981 Chapter 39 FlexTimer Module (FTM) begin update OUTMASK register at update OUTMASK register by each rising edge of system clock PWM synchronization SYNCHOM bit ? SYNCMODE rising edge no = bit ? of system clock ? legacy = yes PWM synchronization update OUTMASK with its buffer value enhanced PWM synchronization...
Page 982 Functional description If (SYNCMODE = 0), (SYNCHOM = 1), and (PWMSYNC = 0), then this synchronization is done on the next enabled trigger event. If the trigger event was a software trigger, then the SWSYNC bit is cleared on the next selected loading point. If the trigger event was a hardware trigger, then the TRIGn bit is cleared according to Hardware trigger.
Page 983: Invctrl Register Synchronization
Chapter 39 FlexTimer Module (FTM) system clock write 1 to TRIG0 bit TRIG0 bit trigger 0 event OUTMASK register is updated and TRIG0 bit is cleared Figure 39-219. OUTMASK synchronization with (SYNCMODE = 0), (HWTRIGMODE = 0), (SYNCHOM = 1), (PWMSYNC = 1), and a hardware trigger was used 39.5.11.8 INVCTRL register synchronization The INVCTRL register synchronization updates the INVCTRL register with its buffer value.
Page 984: Swoctrl Register Synchronization
Functional description begin update INVCTRL register at update INVCTRL register by each rising edge of system clock PWM synchronization INVC bit ? SYNCMODE bit ? rising edge no = of system clock ? = yes update INVCTRL with its buffer value enhanced PWM synchronization INVCTRL is updated INVCTRL is updated...
Page 985 Chapter 39 FlexTimer Module (FTM) The SWOCTRL register can be updated at each rising edge of system clock (SWOC = 0) or by the enhanced PWM synchronization (SWOC = 1 and SYNCMODE = 1) according to the following flowchart. In the case of enhanced PWM synchronization, the SWOCTRL register synchronization depends on SWSOC and HWSOC bits.
Page 986: Ftm Counter Synchronization
Functional description 39.5.11.10 FTM counter synchronization The FTM counter synchronization is a mechanism that allows the FTM to restart the PWM generation at a certain point in the PWM period. The channels outputs are forced to their initial value, except for channels in Output Compare mode, and the FTM counter is forced to its initial counting value defined by CNTIN register.
Page 987 Chapter 39 FlexTimer Module (FTM) begin legacy SYNCMODE PWM synchronization bit ? enhanced PWM synchronization FTM counter is reset by FTM counter is reset by software trigger hardware trigger SWRSTCNT HWRSTCNT bit ? bit ? hardware TRIGn software SWSYNC trigger bit ? trigger bit ?
Page 988 Functional description system clock write 1 to SWSYNC bit SWSYNC bit software trigger event FTM counter is updated with the CNTIN register value and channel outputs are forced to their initial value Figure 39-224. FTM counter synchronization with (SYNCMODE = 0), (REINIT = 1), (PWMSYNC = 0), and software trigger was used system clock write 1 to TRIG0 bit...
Page 989 Chapter 39 FlexTimer Module (FTM) 39.5.12 Inverting The invert functionality swaps the signals between channel (n) and channel (n+1) outputs. The inverting operation is selected when: • QUADEN = 0 • DECAPEN = 0 • COMP = 1, and • INVm = 1 (where m represents a channel pair) The INVm bit in INVCTRL register is updated with its buffer value according to INVCTRL register synchronization In High-True (ELSnB:ELSnA = 1:0) Combine mode, the channel (n) output is forced low...
Page 990: Software Output Control
Functional description Note that the ELSnB:ELSnA bits value should be considered because they define the active state of the channels outputs. In Low-True (ELSnB:ELSnA = X:1) Combine mode, the channel (n) output is forced high at the beginning of the period, forced low at the channel (n) match and forced high at the channel (n+1) match.
Page 991 Chapter 39 FlexTimer Module (FTM) The CHnOC bit enables the software output control for a specific channel output and the CHnOCV selects the value that is forced to this channel output. Both CHnOC and CHnOCV bits in SWOCTRL register are buffered and updated with their buffer value according to SWOCTRL register synchronization.
Page 992: Deadtime Insertion
Functional description Table 39-248. Software ouput control behavior when (COMP = 1) CH(n)OC CH(n+1)OC CH(n)OCV CH(n+1)OCV Channel (n) Output Channel (n+1) Output is not modified by SWOC is not modified by SWOC is forced to zero is forced to zero is forced to zero is forced to one is forced to one...
Page 993 Chapter 39 FlexTimer Module (FTM) when the channel (n+1) match (FTM counter = C(n+1)V) occurs, the channel (n+1) output remains at the high value until the end of the deadtime delay when the channel (n +1) output is cleared. channel (n+1) match FTM counter channel (n) match channel (n) output...
Page 994: Deadtime Insertion Corner Cases
Functional description 39.5.14.1 Deadtime insertion corner cases If (PS[2:0] is cleared), (DTPS[1:0] = 0:0 or DTPS[1:0] = 0:1): • and the deadtime delay is greater than or equal to the channel (n) duty cycle ((C(n +1)V – C(n)V) × system clock), then the channel (n) output is always the inactive value (POL(n) bit value).
Page 995: Output Mask
Chapter 39 FlexTimer Module (FTM) channel (n+1) match FTM counter channel (n) match channel (n) output (before deadtime insertion) channel (n+1) output (before deadtime insertion) channel (n) output (after deadtime insertion) channel (n+1) output (after deadtime insertion) Figure 39-233. Example of the deadtime insertion (ELSnB:ELSnA = 1:0, POL(n) = 0, and POL(n+1) = 0) when the deadtime delay is comparable to channels (n) and (n+1) duty cycle 39.5.15 Output mask...
Page 996: Fault Control
Functional description the beginning of new PWM cycles FTM counter channel (n) output (before output mask) CHnOM bit channel (n) output (after output mask) channel (n) output is disabled configured PWM signal starts to be available in the channel (n) output Figure 39-234.
Page 997 Chapter 39 FlexTimer Module (FTM) counter continues to increment. If the 5-bit counter overflows, that is, the counter exceeds the value of the FFVAL[3:0] bits, the new fault input n value is validated. It is then transmitted as a pulse edge to the edge detector. If the opposite edge appears on the fault input n signal before validation (counter overflow), the counter is reset.
Page 998 Functional description If the fault control is enabled (FAULTM[1:0] ≠ 0:0), a fault condition has occurred and (FAULTEN = 1), then outputs are forced to their safe values: • Channel (n) output takes the value of POL(n) • Channel (n+1) takes the value of POL(n+1) The fault interrupt is generated when (FAULTF = 1) and (FAULTIE = 1).
Page 999: Fault Inputs Polarity Control
Chapter 39 FlexTimer Module (FTM) 39.5.16.2 Manual fault clearing If the manual fault clearing is selected (FAULTM[1:0] = 0:1 or 1:0), then the channels output disabled by fault control is again enabled when the FAULTF bit is cleared and a new PWM cycle begins.
Page 1000: Features Priority
Functional description • If POLn = 0, the channel (n) output polarity is high, so the logical one is the active state and the logical zero is the inactive state. • If POLn = 1, the channel (n) output polarity is low, so the logical zero is the active state and the logical one is the inactive state.

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NXP Semiconductors freescale KV4 Series Reference Manual

Chapter 1 About this Document

Chapter 2 Introduction

Chapter 3 Core Overview

Chapter 4 Memories and Memory Interfaces

Chapter 5 Memory Map

Chapter 6 Clock Distribution

Chapter 7 Power Management

Chapter 8 Security

Chapter 9 Debug

Chapter 10 Reset and Boot

Chapter 11 Signal Multiplexing

Chapter 12 Port Control and Interrupts (PORT)

Chapter 13 System Integration Module (SIM)

Chapter 14 Kinetis Flashloader

Chapter 15 Reset Control Module (RCM)

Chapter 16 System Mode Controller (SMC)

Chapter 17 Miscellaneous Control Module (MCM)

Chapter 18 Power Management Controller (PMC)

Chapter 19 Low-Leakage Wakeup Unit (LLWU)

Chapter 20 Crossbar Switch Lite (AXBS-Lite)

Chapter 21 Peripheral Bridge (AIPS-Lite)

Chapter 22 Direct Memory Access Multiplexer (DMAMUX)

Chapter 23 Direct Memory Access Controller (Edma)

Chapter 24 External Watchdog Monitor (EWM)

Chapter 25 Watchdog Timer (WDOG)

Chapter 26 Inter-Peripheral Crossbar Switch a (XBARA)

Chapter 27 Inter-Peripheral Crossbar Switch B (XBARB)

Chapter 29 Oscillator (OSC)

Chapter 30 Multipurpose Clock Generator (MCG)

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