Llwu Pin Enable 2 Register (Llwu_Pe2) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Field
00 External input pin disabled as wakeup input
01 External input pin enabled with rising edge detection
10 External input pin enabled with falling edge detection
11 External input pin enabled with any change detection
3–2 Wakeup Pin Enable For LLWU_P1
WUPE1
Enables and configures the edge detection for the wakeup pin.
00 External input pin disabled as wakeup input
01 External input pin enabled with rising edge detection
10 External input pin enabled with falling edge detection
11 External input pin enabled with any change detection
WUPE0 Wakeup Pin Enable For LLWU_P0
Enables and configures the edge detection for the wakeup pin.
00 External input pin disabled as wakeup input
01 External input pin enabled with rising edge detection
10 External input pin enabled with falling edge detection
11 External input pin enabled with any change detection

18.4.2 LLWU Pin Enable 2 register (LLWU_PE2)

LLWU_PE2 contains the field to enable and select the edge detect type for the external
wakeup input pins LLWU_P7–LLWU_P4.
This register is reset on Chip Reset not VLLS and by reset
types that trigger Chip Reset not VLLS. It is unaffected by reset
types that do not trigger Chip Reset not VLLS. See the
Introduction
Address: 4007_C000h base + 1h offset = 4007_C001h
Bit 7
Read
WUPE7
Write
Reset 0
Field
7–6 Wakeup Pin Enable For LLWU_P7
WUPE7
Enables and configures the edge detection for the wakeup pin.
00 External input pin disabled as wakeup input
01 External input pin enabled with rising edge detection
Freescale Semiconductor, Inc.
LLWU_PE1 field descriptions (continued)
NOTE
details for more information.
6 5
WUPE6
0 0
LLWU_PE2 field descriptions
Table continues on the next page...
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Chapter 18 Low-Leakage Wakeup Unit (LLWU)
Description
4 3
WUPE5
0 0
Description
2 1
WUPE4
0 0
0
0
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