Functional Description; Lptmr Power And Reset; Lptmr Clocking - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Table of Contents

Functional description

Counter Value

The CNR returns the value of the LPTMR counter at the time this register was last written. Writing the

CNR will latch the current value of the LPTMR for subsequent reading, the value written is ignored.

31.5 Functional description

The LPTMR remains powered in all power modes, including low-leakage modes. If the

LPTMR is not required to remain operating during a low-power mode, then it must be

disabled before entering the mode.

The LPTMR is reset only on global Power On Reset (POR) or Low Voltage Detect

(LVD). When configuring the LPTMR registers, the CSR must be initially written with

the timer disabled, before configuring the PSR and CMR. Then, CSR[TIE] must be set as

the last step in the initialization. This ensures the LPTMR is configured correctly and the

LPTMR counter is reset to zero following a warm reset.

The LPTMR prescaler/glitch filter can be clocked by one of the four clocks. The clock

source must be enabled before the LPTMR is enabled.

The clock source selected need to be configured to remain

enabled in low-power modes, otherwise the LPTMR will not

operate during low-power modes.

In Pulse Counter mode with the prescaler/glitch filter bypassed, the selected input source

directly clocks the CNR and no other clock source is required. To minimize power in this

case, configure the prescaler clock source for a clock that is not toggling.

The clock source or pulse input source selected for the LPTMR

should not exceed the frequency f

LPTMRx_CNR field descriptions (continued)

KL27 Sub-Family Reference Manual , Rev. 5, 01/2016

defined in the device

Freescale Semiconductor, Inc.