External Signal Description - NXP Semiconductors MKL27Z128VFM4 Reference Manual

External signal description

SPE
ENABLE
SPI SYSTEM
SHIFT
OUT
8 OR 16
SPIMODE
BIT MODE
FIFOMODE
LSBFE SHIFT
DIRECTION
BUS RATE
SPI BR
CLOCK
CLOCK GENERATOR
MASTER/SLAVE
MSTR
MODE SELECT
RX DMA DONE
RX BUFFER
RX DMA REQ
NOT EMPTY
TX DMA DONE
TX BUFFER
TX DMA REQ
NOT FULL
RNFULLF
RNFULLIEN
TNEAREF
TNEARIEN
35.3 External signal description
The SPI optionally shares four port pins. The function of these pins depends on the
settings of SPI control bits. When the SPI is disabled (SPE = 0), these four pins revert to
other functions that are not controlled by the SPI (based on chip configuration).
572
Tx FIFO (64 bits deep)
Tx BUFFER (WRITE DH:DL)
SPI SHIFT REGISTER
Rx BUFFER (READ DH:DL)
Rx FIFO (64 bits deep)
SHIFT Rx BUFFER
CLOCK FULL
CLOCK
LOGIC
MODE FAULT
DETECTION
SPRF
RXDMAE
TXDMAE
MODF
Figure 35-3. SPI Module Block Diagram with FIFO
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
SHIFT
IN
SPC0
BIDIROE
Tx BUFFER
EMPTY
MASTER CLOCK
SLAVE CLOCK
MODFEN
SSOE
16-BIT COMPARATOR
MH:ML
16-BIT LATCH
SPTEF
SPTIE
SPIE
PIN CONTROL
M
MOSI
S
(MOMI)
M
MISO
(SISO)
S
M
SPSCK
S
MASTER/
SLAVE
SS
SPMF
SPMIE
SPI
INTERRUPT
REQUEST
Freescale Semiconductor, Inc.