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Field
0
Short sample time.
1
Long sample time.
3–2
Conversion mode selection
MODE
Selects the ADC resolution mode.
00
When DIFF=0:It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with
2's complement output.
01
When DIFF=0:It is single-ended 12-bit conversion ; when DIFF=1, it is differential 13-bit conversion
with 2's complement output.
10
When DIFF=0:It is single-ended 10-bit conversion. ; when DIFF=1, it is differential 11-bit conversion
with 2's complement output
11
When DIFF=0:It is single-ended 16-bit conversion..; when DIFF=1, it is differential 16-bit conversion
with 2's complement output
ADICLK
Input Clock Select
Selects the input clock source to generate the internal clock, ADCK. Note that when the ADACK clock
source is selected, it is not required to be active prior to conversion start. When it is selected and it is not
active prior to a conversion start, when CFG2[ADACKEN]=0, the asynchronous clock is activated at the
start of a conversion and deactivated when conversions are terminated. In this case, there is an
associated clock startup delay each time the clock source is re-activated.
00
Bus clock
01
Bus clock divided by 2(BUSCLK/2)
10
Alternate clock (ALTCLK)
11
Asynchronous clock (ADACK)
23.4.3 ADC Configuration Register 2 (ADCx_CFG2)
Configuration Register 2 (CFG2) selects the special high-speed configuration for very
high speed conversions and selects the long sample time duration during long sample
mode.
Address: 4003_B000h base + Ch offset = 4003_B00Ch
Bit
31
30
29
R
W
Reset
0
0
0
15
14
13
Bit
R
W
Reset
0
0
0
Freescale Semiconductor, Inc.
ADCx_CFG1 field descriptions (continued)
28
27
26
25
0
0
0
0
12
11
10
9
0
0
0
0
0
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Chapter 23 Analog-to-Digital Converter (ADC)
Description
24
23
22
21
0
0
0
0
0
8
7
6
5
0
0
0
0
0
20
19
18
17
0
0
0
0
4
3
2
1
ADLSTS
0
0
0
0
16
0
0
0
347
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