Functional Description; Shifter Operation - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Table of Contents

trigger input, the compare register is used to set the number of bits in each word equal to (CMP[15:0] +

39.4 Functional description

Shifters are responsible for buffering and shifting data into or out of the FlexIO. The

timing of shift, load and store events are controlled by the Timer assigned to the Shifter

via the SHIFTCTL[TIMSEL] register. The Shifters are designed to support either DMA,

interrupt or polled operation. The following block diagram provides a detailed view of

the Shifter microarchitecture.

timer_load_data/start/stop

39.4.1.1 Transmit Mode

When configured for Transmit mode (SHIFTCTL[SMOD]=Transmit), the shifter will

load data from the SHIFTBUF register and shift data out when a load event is signalled

by the assigned Timer. An optional start/stop bit can also be automatically loaded before/

after SHIFTBUF data by configuring the SHIFTCFG[SSTART], TIMCFG[TSTART] or

SHIFTCFG[SSTOP], TIMCFG[TSTOP] registers in the Shifter and Timer. Note that the

shifter will immediately load a stop bit when the Shifter is initially configured for

Transmit mode if a stop bit is enabled.

Freescale Semiconductor, Inc.

FLEXIO_TIMCMPn field descriptions (continued)

S = synchronizer

Figure 39-2. Shifter Microarchitecture

KL27 Sub-Family Reference Manual , Rev. 5, 01/2016

timer_store_data

timer_shift_pos

timer_shift_neg

Chapter 39 FlexIO