Peripheral Access Control Register (Aips_Pacrn) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Memory map/register definition
Field
0 This master is not trusted for write accesses.
1 This master is trusted for write accesses.
20 Master 2 Privilege Level
MPL2
Specifies how the privilege level of the master is determined.
0 Accesses from this master are forced to user-mode.
1 Accesses from this master are not forced to user-mode.
19 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
18 Master 3 Trusted For Read
MTR3
Determines whether the master is trusted for read accesses.
0 This master is not trusted for read accesses.
1 This master is trusted for read accesses.
17 Master 3 Trusted For Writes
MTW3
Determines whether the master is trusted for write accesses.
0 This master is not trusted for write accesses.
1 This master is trusted for write accesses.
16 Master 3 Privilege Level
MPL3
Specifies how the privilege level of the master is determined.
0 Accesses from this master are forced to user-mode.
1 Accesses from this master are not forced to user-mode.

19.3.2 Peripheral Access Control Register (AIPS_PACRn)

The following table shows the location of each peripheral slot's PACR field in the PACR
registers.
Offset Register
0x20 PACRA PACR0
0x24 PACRB PACR8
0x28 PACRC PACR16
0x2C PACRD PACR24
Address: 0h base + 20h offset + (4d × i), where i=0d to 3d
Bit 31 30 29
0
R
SP0 WP0
W
Reset
0* 0* 0*
286
AIPS_MPRA field descriptions (continued)
[31:28] [27:24] [23:20]
PACR1 PACR2
PACR9 PACR10
PACR17 PACR18
PACR25 PACR26
28 27 26 25
0
TP0 SP1 WP1
0* 0* 0* 0*
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Description
[19:16] [15:12]
PACR3 PACR4
PACR11 PACR12
PACR19 PACR20
PACR27 PACR28
24 23 22 21
0
TP1 SP2 WP2
0* 0* 0* 0*
[11:8] [7:4]
PACR5 PACR6 PACR7
PACR13 PACR14 PACR15
PACR21 PACR22 PACR23
PACR29 PACR30 PACR31
20 19 18 17
0
TP2 SP3 WP3
0* 0* 0* 0*
Freescale Semiconductor, Inc.
[3:0]
16
TP3
0*