Dac Resets; Dac Clocks; Dac Interrupts; Cmp Trigger Mode - NXP Semiconductors MKL27Z128VFM4 Reference Manual

DAC resets

24.9.1 Voltage reference source select
• V connects to the primary voltage source as supply reference of 64 tap resistor
in1
ladder
• V connects to an alternate voltage source
in2
24.10 DAC resets
This module has a single reset input, corresponding to the chip-wide peripheral reset.

24.11 DAC clocks

This module has a single clock input, the bus clock.

24.12 DAC interrupts

This module has no interrupts.

24.13 CMP Trigger Mode

CMP and DAC are configured to CMP Trigger mode when CMP_CR1[TRIGM] is set to
1.
In addition, the CMP must be enabled. If the DAC is to be used as a reference to the
CMP, it must also be enabled.
CMP Trigger mode depends on an external timer resource to periodically enable the
CMP and 6-bit DAC in order to generate a triggered compare.
Upon setting TRIGM, the CMP and DAC are placed in a standby state until an external
timer resource trigger is received.
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KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Freescale Semiconductor, Inc.