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Memory map and register definition
Field
4–2
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
1
FIFO Warning DMA Enable
FWDE
Enables/disables DMA requests.
0
Disables the DMA request.
1
Enables the DMA request.
0
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
40.4.9 SAI Receive Configuration 2 Register (I2Sx_RCR2)
This register must not be altered when RCSR[RE] is set.
Address: 4002_F000h base + 88h offset = 4002_F088h
Bit
31
30
29
R
SYNC
BCS
W
Reset
0
0
0
15
14
13
Bit
R
W
Reset
0
0
0
Field
31–30
Synchronous Mode
SYNC
Configures between asynchronous and synchronous modes of operation. When configured for a
synchronous mode of operation, the transmitter must be configured for asynchronous operation.
00
Asynchronous mode.
01
Synchronous with transmitter.
10
Synchronous with another SAI receiver.
11
Synchronous with another SAI transmitter.
29
Bit Clock Swap
BCS
This field swaps the bit clock used by the receiver. When the receiver is configured in asynchronous mode
and this bit is set, the receiver is clocked by the transmitter bit clock (SAI_TX_BCLK). This allows the
transmitter and receiver to share the same bit clock, but the receiver continues to use the receiver frame
sync (SAI_RX_SYNC).
When the receiver is configured in synchronous mode, the transmitter BCS field and receiver BCS field
must be set to the same value. When both are set, the transmitter and receiver are both clocked by the
receiver bit clock (SAI_RX_BCLK) but use the transmitter frame sync (SAI_TX_SYNC).
804
I2Sx_RCSR field descriptions (continued)
28
27
26
25
BCI
MSEL
BCP
0
0
0
0
12
11
10
9
0
0
0
0
0
I2Sx_RCR2 field descriptions
Table continues on the next page...
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Description
24
23
22
21
BCD
0
0
0
0
8
7
6
5
0
0
0
0
Description
20
19
18
17
0
0
0
0
0
4
3
2
1
DIV
0
0
0
0
Freescale Semiconductor, Inc.
16
0
0
0
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