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Memory Map and Registers
39.3.16 Shifter Buffer N Bit Byte Swapped Register
(FLEXIO_SHIFTBUFBBSn)
.
Address: 4005_F000h base + 380h offset + (4d × i), where i=0d to 3d
Bit
31
30
29
28
27
26
R
W
0
0
0
0
0
0
Reset
Field
SHIFTBUFBBS Shift Buffer
Alias to SHIFTBUF register, except reads/writes to this register are bit swapped within each byte. Reads
return { SHIFTBUF[24:31], SHIFTBUF[16:23], SHIFTBUF[8:15], SHIFTBUF[0:7] }.
39.3.17 Timer Control N Register (FLEXIO_TIMCTLn)
.
Address: 4005_F000h base + 400h offset + (4d × i), where i=0d to 3d
Bit
31
30
29
0
R
W
Reset
0
0
0
Bit
15
14
13
0
R
W
Reset
0
0
0
Field
31–28
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
27–24
Trigger Select
TRGSEL
The valid values for TRGSEL will depend on the FLEXIO_PARAM register.
762
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
FLEXIO_SHIFTBUFBBSn field descriptions
28
27
26
25
TRGSEL
0
0
0
0
12
11
10
9
PINSEL
0
0
0
0
FLEXIO_TIMCTLn field descriptions
Table continues on the next page...
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
17
16
15
14
13
12
11
10
SHIFTBUFBBS
0
0
0
0
0
0
0
Description
24
23
22
21
0
0
0
0
8
7
6
5
0
0
0
0
Description
9
8
7
6
5
4
3
0
0
0
0
0
0
0
0
20
19
18
0
0
0
0
4
3
2
0
0
0
0
Freescale Semiconductor, Inc.
2
1
0
0
0
0
17
16
PINCFG
0
0
1
0
TIMOD
0
0
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