Mcg Control Register 1 (Mcg_C1) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Absolute
address
(hex)
4006_4000

MCG Control Register 1 (MCG_C1)

4006_4001 MCG Control Register 2 (MCG_C2)
4006_4006 MCG Status Register (MCG_S)
4006_4008 MCG Status and Control Register (MCG_SC)
4006_4018 MCG Miscellaneous Control Register (MCG_MC)
27.2.1 MCG Control Register 1 (MCG_C1)
Address: 4006_4000h base + 0h offset = 4006_4000h
Bit 7
Read
CLKS
Write
Reset 0
Field
7–6 Clock Source Select
CLKS
Selects the clock source for MCGOUTCLK.
00 Selects HIRC clock as the main clock source. This is HIRC mode.
01 Selects LIRC clock as the main clock source. This is LIRC2M or LIRC8M mode.
10 Selects external clock as the main clock source. This is EXT mode.
11 Reserved. Writing 11 takes no effect.
5–2 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
1 Internal Reference Clock Enable
IRCLKEN
Enables the IRC source.
0 LIRC is disabled.
1 LIRC is enabled.
0 Internal Reference Stop Enable
IREFSTEN
Controls whether the IRC source remains enabled when the MCG_Lite enters Stop mode.
0 LIRC is disabled in Stop mode.
1 LIRC is enabled in Stop mode, if IRCLKEN is set.
Freescale Semiconductor, Inc.
MCG memory map
Register name
6 5
1 0
MCG_C1 field descriptions
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Chapter 27 Multipurpose Clock Generator Lite (MCG_Lite)
Width
Access
(in bits)
8 R/W
8 R/W
8
8 R/W
8 R/W
4 3
0
0 0
Description
Section/
Reset value
page
40h 27.2.1/435
01h 27.2.2/436
R 04h 27.2.3/437
00h 27.2.4/437
00h 27.2.5/438
2 1
IRCLKEN IREFSTEN
0 0
0
0
435