Entering And Exiting Power Modes - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Chip mode Description
• All SRAM is operating (content retained and I/O states held).
VLLS3 (Very • Most peripherals are disabled (with clocks stopped), but OSC,
Low-Leakage LLWU, LPTMR, RTC, CMP can be used.
Stop3) • NVIC is disabled; LLWU is used to wake up.
• SRAM_U and SRAM_L remain powered on (content retained
and I/O states held).
VLLS1 (Very • Most peripherals are disabled (with clocks stopped), but OSC,
Low-Leakage LLWU, LPTMR, RTC, CMP can be used.
Stop1) • NVIC is disabled; LLWU is used to wake up.
• All of SRAM_U and SRAM_L are powered off.
• The 32-byte system register file remains powered for customer-
critical data
VLLS0 (Very • Most peripherals are disabled (with clocks stopped), but LLWU,
Low-Leakage LPTMR, RTC can be used.
Stop 0) • NVIC is disabled; LLWU is used to wake up.
• All of SRAM_U and SRAM_L are powered off.
• The 32-byte system register file remains powered for customer-
critical data
• LPO disabled, optional POR brown-out detection
1. Resumes Normal Run mode operation by executing the LLWU interrupt service routine.
2. Follows the reset flow with the LLWU interrupt flag set for the NVIC.

7.4 Entering and exiting power modes

The WFI instruction invokes wait and stop modes for the chip. The processor exits the
low-power mode via an interrupt.
For LLS and VLLS modes, the wake-up sources are limited to LLWU generated wake-
ups,NMI_b pin, or RESET_b pin assertions. When the NMI_b pin or RESET_b pin have
been disabled through associated FTFA_FOPT settings, then these pins are ignored as
wakeup sources. The wake-up flow from VLLSx is always through reset.
The WFE instruction can have the side effect of entering a low-
power mode, but that is not its intended usage. See ARM
documentation for more on the WFE instruction.
On VLLS recoveries, the I/O pins continue to be held in a static state after code execution
begins, allowing software to reconfigure the system before unlocking the I/O. RAM is
retained in VLLS3 only.
Freescale Semiconductor, Inc.
Table 7-1. Chip power modes (continued)
NOTE:
The LLWU interrupt must not be masked by
the interrupt controller to avoid a scenario
where the system does not fully exit stop
mode on an LLS recovery
NOTE
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Chapter 7 Power Management
Core mode Normal
recovery
method
Sleep Deep Wake-up Reset
Sleep Deep Wake-up Reset
Sleep Deep Wake-up Reset
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