Clock Gating; Module Clocks - NXP Semiconductors MKL27Z128VFM4 Reference Manual

5.6 Clock gating

The clock to each module can be individually gated on and off using bits of the SCGCx
registers of the SIM module. These bits are cleared after any reset, which disables the
clock to the corresponding module to conserve power. Prior to initializing a module, set
the corresponding bit in the SCGCx register to enable the clock. Before turning off the
clock, make sure to disable the module.
Any bus access to a peripheral that has its clock disabled generates an error termination.

5.7 Module clocks

The following table summarizes the clocks associated with each module.
Module
ARM Cortex-M0+ core
NVIC
DAP
DMA
DMA Mux
Port control
Crossbar Switch
Peripheral bridges
LLWU, PMC, SIM, RCM
Mode controller
MCM
COP watchdog
MCG_Lite
OSC
Flash Controller
Flash memory
Freescale Semiconductor, Inc.
Table 5-2. Module clocks
Bus interface clock
Core modules
Platform clock
Platform clock
Platform clock
System modules
System clock
Bus clock
Bus clock
Platform clock
System clock
Bus clock
Bus clock
Platform clock
Bus clock
Clocks
Bus clock
Bus clock
Memory and memory interfaces
Platform clock
Flash clock
Analog
Table continues on the next page...
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Internal clocks
Core clock
—
—
—
—
—
—
Bus clock
LPO
—
—
LPO, Bus Clock, MCGIRCLK,
OSCERCLK
MCGOUTCLK, MCGPCLK,
MCGIRCLK, OSCERCLK,
ERCLK32K
OSCERCLK
Flash clock
—
Chapter 5 Clock Distribution
I/O interface clocks
—
—
SWD_CLK
—
—
—
—
—
—
—
—
—
—
—
—
—
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