Spi Baud Rate Generation; Special Features - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Table of Contents

Functional description

When C1[CPHA] = 0, the slave begins to drive its MISO output with the first data bit

value (MSB or LSB depending on LSBFE) when SS goes to active low. The first SPSCK

edge causes both the master and the slave to sample the data bit values on their MISO

and MOSI inputs, respectively. At the second SPSCK edge, the SPI shifter shifts one bit

position which shifts in the bit value that was just sampled and shifts the second data bit

value out the other end of the shifter to the MOSI and MISO outputs of the master and

slave, respectively. When C1[CPHA] = 0, the slave's SS input must go to its inactive high

level between transfers.

35.5.8 SPI baud rate generation

As shown in the following figure, the clock source for the SPI baud rate generator is the

SPI module clock. The prescale bits (SPPR2:SPPR1:SPPR0) choose a prescale divisor of

1, 2, 3, 4, 5, 6, 7, or 8. The rate-select bits (SPR3:SPR2:SPR1:SPR0) divide the output of

the prescaler stage by 2, 4, 8, 16, 32, 64, 128, 256, or 512 to get the internal SPI master

mode bit-rate clock.

The baud rate generator is activated only when the SPI is in the master mode and a serial

transfer is taking place. In the other cases, the divider is disabled to decrease I

The baud rate divisor equation is as follows (except those reserved combinations in the

SPI Baud Rate Divisor table).

BaudRateDivisor = (SPPR + 1) × 2

The baud rate can be calculated with the following equation:

BaudRate = SPI Module Clock / BaudRateDivisor

The following section describes the special features of SPI module.

1, 2, 3, 4, 5, 6, 7, or 8

SPPR2:SPPR1:SPPR0

Figure 35-9. SPI baud rate generation

KL27 Sub-Family Reference Manual , Rev. 5, 01/2016

BAUD RATE DIVIDER

2, 4, 8, 16, 32, 64, 128,

SPR3:SPR2:SPR1:SPR0

Freescale Semiconductor, Inc.