Application Information; Uart Transmit - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Table of Contents

Application Information

When configuring a pin as an input (this includes a timer trigger configured as a pin

input), the input signal is first synchronized to the FlexIO clock before the signal is used

by a timer or shifter. This introduces a small latency of between 0.5 to 1.5 FlexIO clock

cycles when using an external pin input to generate an output or control a shifter. This

sets the maximum setup time at 1.5 FlexIO clock cycles.

If an input is used by more than one timer or shifter then the synchronization occurs once

to ensure any edge is seen on the same cycle by all timers and shifters using that input.

Note that FlexIO pins are also connected internally, configuring a FlexIO shifter or timer

to output data on an unused pin will make an internal connection that allows other

shifters and timer to use this pin as an input. This allows a shifter output to be used to

trigger a timer or a timer output to be shifted into a shifter. This path is also synchronized

to the FlexIO clock and therefore incurs a 1 cycle latency.

So when using a Pin input as a Timer Trigger, Timer Clock or Shifter Data Input, the

following synchronization delays occur:

1. 0.5 – 1.5 FlexIO clock cycles for external pin

2. 1 FlexIO clock cycle for an internally driven pin

For timing considerations such as output valid time and input setup time for specific

applications (SPI Master, SPI Slave, I2C Master, I2S Master, I2S Slave) please refer to

the FlexIO Application Information Section.

39.5 Application Information

This section provides examples for a variety of FlexIO module applications.

UART transmit can be supported using one Timer, one Shifter and one Pin (two Pins if

supporting CTS). The start and stop bit insertion is handled automatically and multiple

transfers can be supported using DMA controller. The timer status flag can be used to

indicate when the stop bit of each word is transmitted.

Break and idle characters require software intervention, before transmitting a break or

idle character the SSTART and SSTOP fields should be altered to transmit the required

state and the data to transmit must equal 0xFF or 0x00. Supporting a second stop bit

requires the stop bit to be inserted into the data stream using software (and increasing the

KL27 Sub-Family Reference Manual , Rev. 5, 01/2016

Freescale Semiconductor, Inc.