Mcg Miscellaneous Control Register (Mcg_Mc) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Memory map and register definition
Field
3–1 Low-frequency Internal Reference Clock Divider
FCRDIV
Selects the factor value to divide the LIRC source.
000 Division factor is 1.
001 Division factor is 2.
010 Division factor is 4.
011 Division factor is 8.
100 Division factor is 16.
101 Division factor is 32.
110 Division factor is 64.
111 Division factor is 128.
0 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.

27.2.5 MCG Miscellaneous Control Register (MCG_MC)

Address: 4006_4000h base + 18h offset = 4006_4018h
Bit 7
Read
HIRCEN
Write
Reset 0
Field
7 High-frequency IRC Enable
HIRCEN
Enables the HIRC, even when MCG_Lite is not working at HIRC mode.
0 HIRC source is not enabled.
1 HIRC source is enabled.
6–3 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
LIRC_DIV2 Second Low-frequency Internal Reference Clock Divider
Selects the factor value to further divide the LIRC source.
000 Division factor is 1.
001 Division factor is 2.
010 Division factor is 4.
011 Division factor is 8.
100 Division factor is 16.
101 Division factor is 32.
110 Division factor is 64.
111 Division factor is 128.
438
MCG_SC field descriptions (continued)
6 5
0
0 0
MCG_MC field descriptions
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Description
4 3
0 0
Description
2 1
LIRC_DIV2
0 0
Freescale Semiconductor, Inc.
0
0