Adc Offset Correction Register (Adcx_Ofs) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Table of Contents

Advertisement

Memory map and register definitions
Field
5–4
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
3
Continuous Conversion Enable
ADCO
Enables continuous conversions.
0
One conversion or one set of conversions if the hardware average function is enabled, that is,
AVGE=1, after initiating a conversion.
1
Continuous conversions or sets of conversions if the hardware average function is enabled, that is,
AVGE=1, after initiating a conversion.
2
Hardware Average Enable
AVGE
Enables the hardware average function of the ADC.
0
Hardware average function disabled.
1
Hardware average function enabled.
AVGS
Hardware Average Select
Determines how many ADC conversions will be averaged to create the ADC average result.
00
4 samples averaged.
01
8 samples averaged.
10
16 samples averaged.
11
32 samples averaged.

23.4.8 ADC Offset Correction Register (ADCx_OFS)

The ADC Offset Correction Register (OFS) contains the user-selected or calibration-
generated offset error correction value. This register is a 2's complement, left-justified,
16-bit value . The value in OFS is subtracted from the conversion and the result is
transferred into the result registers, Rn. If the result is greater than the maximum or less
than the minimum result value, it is forced to the appropriate limit for the current mode of
operation.
For more information regarding the calibration procedure, please refer to the
function
section.
Address: 4003_B000h base + 28h offset = 4003_B028h
Bit
31
30
29
28
27
26
R
W
0
0
0
0
0
0
Reset
354
ADCx_SC3 field descriptions (continued)
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
0
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Description
17
16
15
14
13
12
11
10
0
0
0
0
0
0
0
0
Calibration
9
8
7
6
5
4
3
2
OFS
0
0
0
0
0
0
0
1
Freescale Semiconductor, Inc.
1
0
0
0

Advertisement

Table of Contents
loading

Table of Contents