Spi Control Register 2 (Spix_C2) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Table of Contents

This 4-bit field selects one of nine divisors for the SPI baud rate divider. The input to this divider comes

from the SPI baud rate prescaler. Refer to the description of "SPI Baud Rate Generation" for details.

35.4.3 SPI Control Register 2 (SPIx_C2)

This read/write register is used to control optional features of the SPI system.

Address: Base address + 2h offset

SPI Match Interrupt Enable

This is the interrupt enable bit for the SPI receive data buffer hardware match (SPMF) function.

Interrupts from SPMF inhibited (use polling)

When SPMF is 1, requests a hardware interrupt

SPI 8-bit or 16-bit mode

This bit allows the user to select either an 8-bit or 16-bit SPI data transmission length. In master mode, a

change of this bit aborts a transmission in progress, forces the SPI system into an idle state, and resets all

status bits in the S register. Refer to the description of "Data Transmission Length" for details.

8-bit SPI shift register, match register, and buffers

16-bit SPI shift register, match register, and buffers

Transmit DMA enable

This bit enables a transmit DMA request. When this bit is set to 1, a transmit DMA request is asserted

when both SPTEF and SPE are set, and the interrupt from SPTEF is disabled.

Freescale Semiconductor, Inc.

SPIx_BR field descriptions (continued)

Baud rate divisor is 2.

Baud rate divisor is 4.

Baud rate divisor is 8.

Baud rate divisor is 16.

Baud rate divisor is 32.

Baud rate divisor is 64.

Baud rate divisor is 128.

Baud rate divisor is 256.

Baud rate divisor is 512.

SPIx_C2 field descriptions

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KL27 Sub-Family Reference Manual , Rev. 5, 01/2016

Chapter 35 Serial Peripheral Interface (SPI)