Source Address Register (Dma_Sarn) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Table of Contents

Source Address Register (DMA_SAR0)

Destination Address Register (DMA_DAR0)

DMA Status Register / Byte Count Register

(DMA_DSR_BCR0)

4000_810C DMA Control Register (DMA_DCR0)

Source Address Register (DMA_SAR1)

Destination Address Register (DMA_DAR1)

DMA Status Register / Byte Count Register

(DMA_DSR_BCR1)

4000_811C DMA Control Register (DMA_DCR1)

Source Address Register (DMA_SAR2)

Destination Address Register (DMA_DAR2)

DMA Status Register / Byte Count Register

(DMA_DSR_BCR2)

4000_812C DMA Control Register (DMA_DCR2)

Source Address Register (DMA_SAR3)

Destination Address Register (DMA_DAR3)

DMA Status Register / Byte Count Register

(DMA_DSR_BCR3)

4000_813C DMA Control Register (DMA_DCR3)

21.3.1 Source Address Register (DMA_SARn)

For this register:

• Only 32-bit writes are allowed. 16-bit and 8-bit writes

result in a bus error.

• Only several values are allowed to be written to bits 31-20

of this register, see the value list in the field description. A

write of any other value to these bits causes a configuration

error when the channel starts to execute. For more

information about the configuration error, see the

description of the

Address: 4000_8000h base + 100h offset + (16d × i), where i=0d to 3d

Freescale Semiconductor, Inc.

DMA memory map

field of DSR.

KL27 Sub-Family Reference Manual , Rev. 5, 01/2016

Chapter 21 DMA Controller Module