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Chapter 19
Peripheral Bridge (AIPS-Lite)
19.1 Chip-specific AIPS-Lite information
19.1.1 Number of peripheral bridges
This device contains one peripheral bridge.
19.1.2 Memory maps
The peripheral bridges are used to access the registers of most of the modules on this
device. See
AIPS0 Memory Map
for the memory slot assignment for each module.
19.2 Introduction
The peripheral bridge converts the crossbar switch interface to an interface that can
access most of the slave peripherals on this chip.
The peripheral bridge occupies 64 MB of the address space, which is divided into
peripheral slots of 4 KB. (It might be possible that all the peripheral slots are not used.
See the memory map chapter for details on slot assignments.) The bridge includes
separate clock enable inputs for each of the slots to accommodate slower peripherals.
19.2.1 Features
Key features of the peripheral bridge are:
• Supports peripheral slots with 8-, 16-, and 32-bit datapath width
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Freescale Semiconductor, Inc.
283
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