NXP Semiconductors MKL04Z8VFK4 Reference Manual

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KL04 Sub-Family Reference Manual

Supports: MKL04Z8VFK4, MKL04Z16VFK4, MKL04Z32VFK4,

MKL04Z8VLC4, MKL04Z16VLC4, MKL04Z32VLC4, MKL04Z8VFM4,

MKL04Z16VFM4, MKL04Z32VFM4, MKL04Z16VLF4, and

MKL04Z32VLF4

Document Number: KL04P48M48SF1RM

Rev. 3.1, November 2012

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Page 1 KL04 Sub-Family Reference Manual Supports: MKL04Z8VFK4, MKL04Z16VFK4, MKL04Z32VFK4, MKL04Z8VLC4, MKL04Z16VLC4, MKL04Z32VLC4, MKL04Z8VFM4, MKL04Z16VFM4, MKL04Z32VFM4, MKL04Z16VLF4, and MKL04Z32VLF4 Document Number: KL04P48M48SF1RM Rev. 3.1, November 2012...
Page 2 KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc.
Page 3: Table Of Contents
Contents Section number Title Page Chapter 1 About This Document Overview..................................29 1.1.1 Purpose.................................29 1.1.2 Audience..............................29 Conventions..................................29 1.2.1 Numbering systems............................29 1.2.2 Typographic notation...........................30 1.2.3 Special terms..............................30 Chapter 2 Introduction Overview..................................31 Kinetis L Series................................31 KL04 Sub-Family Introduction.............................34 Module functional categories............................35 2.4.1 ARM® Cortex™-M0+ Core Modules......................35 2.4.2 System Modules............................36 2.4.3...
Page 4 Section number Title Page Module to Module Interconnects..........................41 3.2.1 Module to Module Interconnects.........................41 3.2.2 Analog reference options..........................43 Core Modules................................44 3.3.1 ARM Cortex-M0+ Core Configuration.......................44 3.3.2 Nested Vectored Interrupt Controller (NVIC) Configuration..............46 3.3.3 Asynchronous wake-up interrupt controller (AWIC) configuration............50 System Modules................................51 3.4.1 SIM Configuration............................51 3.4.2...
Page 5 Section number Title Page 3.6.3 SRAM Configuration...........................69 Analog...................................71 3.7.1 12-bit SAR ADC Configuration........................71 3.7.2 CMP Configuration............................75 Timers...................................77 3.8.1 Timer/PWM Module Configuration......................77 3.8.2 PIT Configuration............................79 3.8.3 Low-power timer configuration........................81 3.8.4 RTC configuration............................82 Communication interfaces............................84 3.9.1 SPI configuration............................84 3.9.2 I2C Configuration............................85 3.9.3 UART Configuration...........................85 3.10 Human-machine interfaces (HMI)..........................87...
Page 6 Section number Title Page Chapter 5 Clock Distribution Introduction...................................101 Programming model..............................101 High-Level device clocking diagram..........................101 Clock definitions................................102 5.4.1 Device clock summary..........................103 Internal clocking requirements.............................105 5.5.1 Clock divider values after reset........................105 5.5.2 VLPR mode clocking...........................106 Clock Gating.................................106 Module clocks................................106 5.7.1 PMC 1-kHz LPO clock..........................107 5.7.2 COP clocking...............................108 5.7.3...
Page 7 Section number Title Page 6.3.2 FOPT boot options............................118 6.3.3 Boot sequence..............................119 Chapter 7 Power Management Introduction...................................121 Clocking Modes................................121 7.2.1 Partial Stop..............................121 7.2.2 DMA Wakeup..............................122 7.2.3 Compute Operation............................123 7.2.4 Peripheral Doze............................124 7.2.5 Clock Gating..............................125 Power modes.................................125 Entering and exiting power modes..........................127 Module Operation in Low Power Modes........................127 Chapter 8 Security...
Page 8 Section number Title Page Debug & Security.................................139 Chapter 10 Signal Multiplexing and Signal Descriptions 10.1 Introduction...................................141 10.2 Signal Multiplexing Integration............................141 10.2.1 Port control and interrupt module features....................142 10.2.2 Clock gating..............................143 10.2.3 Signal multiplexing constraints........................143 10.3 Pinout....................................143 10.3.1 KL04 signal multiplexing and pin assignments...................143 10.3.2 KL04 Pinouts...............................145 10.4...
Page 9 Section number Title Page 11.5 Memory map and register definition..........................155 11.5.1 Pin Control Register n (PORTx_PCRn).......................158 11.5.2 Global Pin Control Low Register (PORTx_GPCLR)..................160 11.5.3 Global Pin Control High Register (PORTx_GPCHR).................161 11.5.4 Interrupt Status Flag Register (PORTx_ISFR)....................161 11.6 Functional description..............................162 11.6.1 Pin control..............................162 11.6.2 Global pin control............................163...
Page 10 Section number Title Page 12.2.16 Unique Identification Register Mid Low (SIM_UIDML)................185 12.2.17 Unique Identification Register Low (SIM_UIDL)..................186 12.2.18 COP Control Register (SIM_COPC)......................186 12.2.19 Service COP Register (SIM_SRVCOP)......................187 12.3 Functional description..............................188 Chapter 13 System Mode Controller (SMC) 13.1 Introduction...................................189 13.2 Modes of operation...............................189 13.3 Memory map and register descriptions.........................191 13.3.1...
Page 11 Section number Title Page 14.4 I/O retention..................................211 14.5 Memory map and register descriptions.........................211 14.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1)............212 14.5.2 Low Voltage Detect Status And Control 2 register (PMC_LVDSC2)............213 14.5.3 Regulator Status And Control register (PMC_REGSC)................214 Chapter 15 Low-Leakage Wakeup Unit (LLWU) 15.1...
Page 12 Section number Title Page 16.2.2 System Reset Status Register 1 (RCM_SRS1)....................235 16.2.3 Reset Pin Filter Control register (RCM_RPFC)..................236 16.2.4 Reset Pin Filter Width register (RCM_RPFW)...................237 Chapter 17 Bit Manipulation Engine (BME) 17.1 Introduction...................................239 17.1.1 Overview..............................240 17.1.2 Features................................240 17.1.3 Modes of Operation.............................241 17.2 External Signal Description............................241 17.3...
Page 13 Section number Title Page 19.1.3 Modes of Operation.............................271 19.2 External Signal Description............................271 19.3 Memory Map and Register Definition..........................272 19.3.1 MTB_RAM Memory Map...........................272 19.3.2 MTB_DWT Memory Map...........................285 19.3.3 System ROM Memory Map.........................295 Chapter 20 Crossbar Switch Lite (AXBS-Lite) 20.1 Introduction...................................301 20.1.1 Features................................301 20.2 Memory Map / Register Definition..........................301...
Page 14 Section number Title Page 22.3 Memory map/register definition...........................309 22.3.1 Channel Configuration register (DMAMUXx_CHCFGn)................309 22.4 Functional description..............................310 22.4.1 DMA channels with periodic triggering capability..................311 22.4.2 DMA channels with no triggering capability....................313 22.4.3 Always-enabled DMA sources........................313 22.5 Initialization/application information...........................314 22.5.1 Reset................................314 22.5.2 Enabling and configuring sources........................314 Chapter 23 DMA Controller Module...
Page 15 Section number Title Page Chapter 24 Multipurpose Clock Generator (MCG) 24.1 Introduction...................................337 24.1.1 Features................................337 24.1.2 Modes of Operation.............................339 24.2 External Signal Description............................340 24.3 Memory Map/Register Definition..........................340 24.3.1 MCG Control 1 Register (MCG_C1)......................340 24.3.2 MCG Control 2 Register (MCG_C2)......................342 24.3.3 MCG Control 3 Register (MCG_C3)......................343 24.3.4 MCG Control 4 Register (MCG_C4)......................343 24.3.5...
Page 16 Section number Title Page 24.5.3 MCG mode switching..........................358 Chapter 25 Oscillator (OSC) 25.1 Introduction...................................365 25.2 Features and Modes..............................365 25.3 Block Diagram................................366 25.4 OSC Signal Descriptions..............................366 25.5 External Crystal / Resonator Connections........................367 25.6 External Clock Connections............................368 25.7 Memory Map/Register Definitions..........................369 25.7.1 OSC Memory Map/Register Definition.......................369 25.8 Functional Description..............................370...
Page 17 Section number Title Page Chapter 27 Flash Memory Module (FTFA) 27.1 Introduction...................................379 27.1.1 Features................................380 27.1.2 Block Diagram.............................380 27.1.3 Glossary...............................381 27.2 External Signal Description............................382 27.3 Memory Map and Registers............................382 27.3.1 Flash Configuration Field Description......................382 27.3.2 Program Flash IFR Map..........................383 27.3.3 Register Descriptions...........................384 27.4 Functional Description..............................392 27.4.1...
Page 18 Section number Title Page 28.2 ADC Signal Descriptions..............................419 28.2.1 Analog Power (VDDA)..........................420 28.2.2 Analog Ground (VSSA)..........................420 28.2.3 Voltage Reference Select..........................420 28.2.4 Analog Channel Inputs (ADx)........................421 28.3 Register definition.................................421 28.3.1 ADC Status and Control Registers 1 (ADCx_SC1n)...................422 28.3.2 ADC Configuration Register 1 (ADCx_CFG1)...................425 28.3.3 ADC Configuration Register 2 (ADCx_CFG2)...................427 28.3.4...
Page 19 Section number Title Page 28.4.7 User-defined offset function........................450 28.4.8 Temperature sensor............................451 28.4.9 MCU wait mode operation...........................452 28.4.10 MCU Normal Stop mode operation......................452 28.4.11 MCU Low-Power Stop mode operation......................453 28.5 Initialization information..............................454 28.5.1 ADC module initialization example......................454 28.6 Application information..............................456 28.6.1 External pins and routing..........................456 28.6.2 Sources of error............................458...
Page 20 Section number Title Page 29.8.4 Low-pass filter.............................484 29.9 CMP interrupts................................487 29.10 DMA support................................487 29.11 CMP Asyncrhonous DMA support..........................487 29.12 Digital-to-analog converter............................488 29.13 DAC functional description............................488 29.13.1 Voltage reference source select........................488 29.14 DAC resets..................................489 29.15 DAC clocks...................................489 29.16 DAC interrupts................................489 29.17 CMP Trigger Mode...............................489 Chapter 30 Timer/PWM Module (TPM) 30.1...
Page 21 Section number Title Page 30.4 Functional Description..............................505 30.4.1 Clock Domains.............................505 30.4.2 Prescaler...............................506 30.4.3 Counter.................................506 30.4.4 Input Capture Mode.............................508 30.4.5 Output Compare Mode..........................509 30.4.6 Edge-Aligned PWM (EPWM) Mode......................510 30.4.7 Center-Aligned PWM (CPWM) Mode......................512 30.4.8 Registers Updated from Write Buffers......................514 30.4.9 DMA................................514 30.4.10 Reset Overview............................515 30.4.11...
Page 22 Section number Title Page 31.4.3 Chained timers.............................526 31.5 Initialization and application information........................526 31.6 Example configuration for chained timers........................527 31.7 Example configuration for the lifetime timer.......................528 Chapter 32 Low-Power Timer (LPTMR) 32.1 Introduction...................................531 32.1.1 Features................................531 32.1.2 Modes of operation............................531 32.2 LPTMR signal descriptions............................532 32.2.1 Detailed signal descriptions.........................532 32.3...
Page 23 Section number Title Page 33.1.3 RTC Signal Descriptions..........................541 33.2 Register definition.................................542 33.2.1 RTC Time Seconds Register (RTC_TSR)....................543 33.2.2 RTC Time Prescaler Register (RTC_TPR)....................543 33.2.3 RTC Time Alarm Register (RTC_TAR).....................544 33.2.4 RTC Time Compensation Register (RTC_TCR)..................544 33.2.5 RTC Control Register (RTC_CR)........................545 33.2.6 RTC Status Register (RTC_SR)........................547 33.2.7...
Page 24 Section number Title Page 34.3 Memory Map and Register Descriptions........................561 34.3.1 SPI control register 1 (SPIx_C1)........................561 34.3.2 SPI control register 2 (SPIx_C2)........................563 34.3.3 SPI baud rate register (SPIx_BR).........................564 34.3.4 SPI status register (SPIx_S).........................565 34.3.5 SPI data register (SPIx_D)...........................566 34.3.6 SPI match register (SPIx_M)........................567 34.4 Functional Description..............................568 34.4.1...
Page 25 Section number Title Page 35.3 Memory map and register descriptions.........................589 35.3.1 I2C Address Register 1 (I2Cx_A1)......................590 35.3.2 I2C Frequency Divider register (I2Cx_F)....................591 35.3.3 I2C Control Register 1 (I2Cx_C1).......................592 35.3.4 I2C Status register (I2Cx_S)........................593 35.3.5 I2C Data I/O register (I2Cx_D)........................595 35.3.6 I2C Control Register 2 (I2Cx_C2).......................596 35.3.7 I2C Programmable Input Glitch Filter register (I2Cx_FLT)...............597...
Page 26 Section number Title Page 36.1.2 Modes of operation............................620 36.1.3 Block diagram..............................620 36.2 Register definition.................................622 36.2.1 UART Baud Rate Register High (UARTx_BDH)..................623 36.2.2 UART Baud Rate Register Low (UARTx_BDL)..................624 36.2.3 UART Control Register 1 (UARTx_C1).....................624 36.2.4 UART Control Register 2 (UARTx_C2).....................626 36.2.5 UART Status Register 1 (UARTx_S1)......................627 36.2.6...
Page 27 Section number Title Page 37.2.2 Port Set Output Register (GPIOx_PSOR)....................649 37.2.3 Port Clear Output Register (GPIOx_PCOR)....................649 37.2.4 Port Toggle Output Register (GPIOx_PTOR).....................650 37.2.5 Port Data Input Register (GPIOx_PDIR).....................650 37.2.6 Port Data Direction Register (GPIOx_PDDR).....................651 37.3 FGPIO memory map and register definition........................651 37.3.1 Port Data Output Register (FGPIOx_PDOR)....................652 37.3.2...
Page 28 KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc.
Page 29: About This Document
Chapter 1 About This Document Overview 1.1.1 Purpose This document describes the features, architecture, and programming model of the Freescale KL04 microcontroller. 1.1.2 Audience This document is primarily for system architects and software application developers who are using or considering using the KL04KL02 microcontroller in a system. Conventions 1.2.1 Numbering systems The following suffixes identify different numbering systems:...
Page 30: Typographic Notation
Conventions 1.2.2 Typographic notation The following typographic notation is used throughout this document: Example Description placeholder, x Items in italics are placeholders for information that you provide. Italicized text is also used for the titles of publications and for emphasis. Plain lowercase letters are also used as placeholders for single letters and numbers.
Page 31: Introduction
Chapter 2 Introduction 2.1 Overview This chapter provides an overview of the Kinetis L series of ARM® Cortex™-M0+ MCUs and KL04 product family. It also presents high-level descriptions of the modules available on the devices covered by this document. 2.2 Kinetis L Series The Kinetis L series is the most scalable portfolio of ultra low-power, mixed-signal ARM Cortex-M0+ MCUs in the industry.
Page 32 Kinetis L Series Kinetis L series MCU families combine the latest low-power innovations with precision mixed-signal capability and a broad range of communication, connectivity, and human- machine interface peripherals. Each MCU family is supported by a market-leading enablement bundle from Freescale and numerous ARM 3rd party ecosystem partners. The KL0x family is the entry-point to the Kinetis L series and is pin compatible with the 8-bit S08PT family.
Page 33 Chapter 2 Introduction • Optimized access to program memory: Accesses on alternate cycles reduces power consumption • 100 percent compatible with ARM Cortex-M0 and a subset ARM Cortex- M3/M4: Reuse existing compilers and debug tools • Simplified architecture: 56 instructions and 17 registers enables easy programming and efficient packaging of 8/16/32-bit data in memory •...
Page 34: Kl04 Sub-Family Introduction
KL04 Sub-Family Introduction • Connectivity and Communications: • Up to three UARTs, all UARTs support DMA transfers, and can trigger when data on bus is detected, UART0 supports 4x to 32x over sampling ratio. Asynchronous transmit and receive operation for operating in STOP/VLPS modes.
Page 35: Module Functional Categories
Chapter 2 Introduction 2.4 Module functional categories The modules on this device are grouped into functional categories. The following sections describe the modules assigned to each category in more detail. Table 2-1. Module functional categories Module category Description ® ARM Cortex-M0+ core •...
Page 36: System Modules
Module functional categories Table 2-2. Core modules Module Description ARM® Cortex™-M0+ The ARM® Cortex™-M0+ is the newest member of the Cortex M Series of processors targeting microcontroller applications focused on very cost sensitive, deterministic, interrupt driven environments. The Cortex M0+ processor is based on the ARMv6 Architecture and Thumb®-2 ISA and is 100% instruction set compatible with its predecessor, the Cortex-M0 core, and upward compatible to Cortex-M3 and M4 cores.
Page 37: Memories And Memory Interfaces
Chapter 2 Introduction Table 2-3. System modules (continued) Module Description Peripheral bridge The peripheral bridge converts the crossbar switch interface to an interface to access a majority of peripherals on the device. DMA multiplexer (DMAMUX) The DMA multiplexer selects from many DMA requests down to 4 for the DMA controller.
Page 38: Analog Modules
Module functional categories Table 2-6. Security and integrity modules Module Description Watchdog Timer (WDOG) Watchdog Timer keeps a watch on the system functioning and resets it in case of its failure. 2.4.6 Analog modules The following analog modules are available on this device: Table 2-7.
Page 39: Communication Interfaces
Chapter 2 Introduction Table 2-8. Timer modules (continued) Module Description Low power timer (LPTMR) • 16-bit time counter or pulse counter with compare • Configurable clock source for prescaler/glitch filter • Configurable input source for pulse counter Real-time counter (RTC) •...
Page 40 Orderable part numbers Table 2-11. Orderable part numbers summary Freescale part number Pin count Package Total flash Temperature range frequency memory MKL04Z8VFK4 48 MHz 8 KB 1 KB -40 to 105 °C MKL04Z16VFK4 48 MHz 16 KB 2 KB -40 to 105 °C...
Page 41: Chip Configuration
Chapter 3 Chip Configuration 3.1 Introduction This chapter provides details on the individual modules of the microcontroller. It includes: • Module block diagrams showing immediate connections within the device • Specific module-to-module interactions not necessarily discussed in the individual module chapters •...
Page 42: Kl04 Sub-Family Reference Manual, Rev. 3.1, November
Module to Module Interconnects Table 3-1. Module to Module Interconnects (continued) Peripheral Signal — to Peripheral Use Case Control Comment LPTMR Hardware trigger ADC (Trigger) ADC Triggering SOPT7_ADC0T — (A or B) RGSEL (4 bit field), ADC0PRETRG SEL to select A or B TPMx ADC (Trigger)
Page 43: Analog Reference Options
Chapter 3 Chip Configuration Table 3-1. Module to Module Interconnects (continued) Peripheral Signal — to Peripheral Use Case Control Comment TPM1 Timebase TPMx TPM Global TPMx_CONF[G — timebase input TBEEN] PIT CHx TIF0, TIF1 TPMx TPM Trigger TPMx_CONF[T If PIT is input RGSEL] (4 bit triggering the...
Page 44: Core Modules
Core Modules Core Modules 3.3.1 ARM Cortex-M0+ Core Configuration This section summarizes how the module has been configured in the chip. Full documentation for this module is provided by ARM and can be found at www.arm.com. Debug Interrupts ARM Cortex-M0+ Crossbar switch Core...
Page 45 Chapter 3 Chip Configuration Table 3-4. ARM Cortex-M0+ parameter settings Parameter Verilog Name Value Description Arch Clock Gating 1 = Present Implements architectural clock gating DAP Slave Port Support AHBSLV Support any AHB debug access port (like the CM4 DAP) DAP ROM Table Base BASEADDR 0xF000_2003...
Page 46: Nested Vectored Interrupt Controller (Nvic) Configuration
Core Modules 3.3.1.3 System Tick Timer The CLKSOURCE bit in SysTick Control and Status register selects either the core clock (when CLKSOURCE = 1) or a divide-by-16 of the core clock (when CLKSOURCE = 0). Because the timing reference is a variable frequency, the TENMS bit in the SysTick Calibration Value Register is always zero.
Page 47 Chapter 3 Chip Configuration Table 3-5. Reference links to related information (continued) Topic Related module Reference Power management Power management Private Peripheral Bus ARM Cortex-M0+ core ARM Cortex-M0+ core (PPB) 3.3.2.1 Interrupt priority levels This device supports 4 priority levels for interrupts. Therefore, in the NVIC each source in the IPR registers contains 2 bits.
Page 48 Core Modules Table 3-7. Interrupt vector assignments (continued) Address Vector NVIC Source module Source description register number 0x0000_0008 — — ARM core Non-maskable Interrupt (NMI) 0x0000_000C — — ARM core Hard Fault 0x0000_0010 — — — — 0x0000_0014 — — —...
Page 49 Chapter 3 Chip Configuration Table 3-7. Interrupt vector assignments (continued) Address Vector NVIC Source module Source description register number 0x0000_0098 Single interrupt vector for all channels 0x0000_009C — — 0x0000_00A0 — 0x0000_00A4 — 0x0000_00A8 — 0x0000_00AC 0x0000_00B0 LPTMR0 0x0000_00B4 — 0x0000_00B8 Port control module Pin detect (Port A)
Page 50: Asynchronous Wake-Up Interrupt Controller (Awic) Configuration
Core Modules 3.3.3 Asynchronous wake-up interrupt controller (AWIC) configuration This section summarizes how the module has been configured in the chip. Full documentation for this module is provided by ARM and can be found at www.arm.com. Clock logic Wake-up requests Asynchronous Module Wake-up Interrupt...
Page 51: System Modules
Chapter 3 Chip Configuration Table 3-10. AWIC stop wake-up sources (continued) Wake-up source Description Address match wakeup UART0 Any interrupt provided clock remains enabled Alarm or seconds interrupt NMI pin TPMx Any interrupt provided clock remains enabled LPTMR Any interrupt provided clock remains enabled Slave mode interrupt System Modules 3.4.1 SIM Configuration...
Page 52: System Mode Controller (Smc) Configuration
System Modules 3.4.2 System Mode Controller (SMC) Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Peripheral bridge Register access System Mode Resets Controller (SMC) Figure 3-5.
Page 53: Low-Leakage Wake-Up Unit (Llwu) Configuration
Chapter 3 Chip Configuration Peripheral bridge Register access Module Module signals signals Power Management Controller (PMC) Figure 3-6. PMC configuration Table 3-13. Reference links to related information Topic Related module Reference Full description System memory map System memory map Power management Power management Full description System Mode...
Page 54 System Modules Peripheral bridge 0 Register access Wake-up requests Low-Leakage Wake-up Module Unit (LLWU) Module Figure 3-7. Low-Leakage Wake-up Unit configuration Table 3-14. Reference links to related information Topic Related module Reference Full description LLWU LLWU System memory map System memory map Clocking Clock distribution Power management...
Page 55: Mcm Configuration
Chapter 3 Chip Configuration Table 3-15. LLWU Wakeup Sources Module source or pin name LLWU_P0 PTA4 LLWU_P1 PTA5 LLWU_P2 PTA6 LLWU_P3 PTA7 LLWU_P4 PTB0 LLWU_P5 PTB2 LLWU_P6 PTB4 LLWU_P7 PTA0 LLWU_M0IF LPTMR0 LLWU_M1IF CMP0 LLWU_M2IF Reserved LLWU_M3IF Reserved LLWU_M4IF TSI0 LLWU_M5IF RTC Alarm LLWU_M6IF...
Page 56: Crossbar-Light Switch Configuration
System Modules Table 3-16. Reference links to related information (continued) Topic Related module Reference Transfer Flash memory Flash memory controller controller 3.4.6 Crossbar-Light Switch Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. GPIO controller Crossbar Switch...
Page 57: Peripheral Bridge Configuration
Chapter 3 Chip Configuration 3.4.6.1 Crossbar-Light Switch Master Assignments The masters connected to the crossbar switch are assigned as follows: Master module Master port number ARM core unified bus 3.4.6.2 Crossbar Switch Slave Assignments This device contains 3 slaves connected to the crossbar switch. The slave assignment is as follows: Slave module Slave port number...
Page 58: Dma Request Multiplexer Configuration
System Modules 3.4.7.1 Number of peripheral bridges This device contains one peripheral bridge. 3.4.7.2 Memory maps The peripheral bridges are used to access the registers of most of the modules on this device. See AIPS0 Memory Map for the memory slot assignment for each module. 3.4.8 DMA request multiplexer configuration This section summarizes how the module has been configured in the chip.
Page 59 Chapter 3 Chip Configuration 3.4.8.1 DMA MUX Request Sources This device includes a DMA request mux that allows up to 63 DMA request signals to be mapped to any of the 4 DMA channels. Because of the mux there is no hard correlation between any of the DMA request sources and a specific DMA channel.
Page 60 System Modules Table 3-20. DMA request sources - MUX 0 (continued) Source Source module Source description Async DMA number capable Reserved — TPM1 Channel 0 TPM1 Channel 1 Reserved — Reserved — Reserved — Reserved — Reserved — Reserved — ADC0 —...
Page 61: Dma Controller Configuration
Chapter 3 Chip Configuration 3.4.8.2 DMA transfers via PIT trigger The PIT module can trigger a DMA transfer on the first two DMA channels. The assignments are detailed at PIT/DMA Periodic Trigger Assignments 3.4.9 DMA Controller Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter.
Page 62 System Modules Peripheral bridge 0 Register access WDOG Figure 3-13. COP watchdog configuration Table 3-22. Reference links to related information Topic Related module Reference Clocking Clock distribution Power management Power management Programming model System Integration Module (SIM) 3.4.10.1 COP clocks The two clock inputs for the COP are the 1 kHz clock and the bus clock.
Page 63 Chapter 3 Chip Configuration The SIM's COPCTRL[COPCLKS] field selects the clock source used for the COP timer. The clock source options are either the bus clock or an internal 1 kHz clock source. With each clock source, there are three associated timeouts controlled by COPCTRL[COPT]. The following table summarizes the control functions of the COPCLKS and COPT bits.
Page 64: Clock Modules
Clock Modules Regardless of the clock selected, the COP is disabled when the chip enters a VLLSx mode. Upon a reset that wakes the chip from the VLLSx mode, the COP is re-initialized and enabled as for any reset. 3.4.10.3 Clock Gating This family of devices includes clock gating control for each peripheral, that is, the clock to each peripheral can explicitly be gated on or off, using clock-gate control bits in the SIM module.
Page 65: Osc Configuration
Chapter 3 Chip Configuration 3.5.1.1 MCG FLL modes On L-series devices the MCGFLLCLK frequency is limited to 48 MHz max. The DCO is limited to the two lowest range settings (MCG_C4[DRST_DRS] must be set to either 0b00 or 0b01). 3.5.2 OSC Configuration This section summarizes how the module has been configured in the chip.
Page 66: Memories And Memory Interfaces
Memories and Memory Interfaces The RTC_CR[OSCE] bit has overriding control over the MCG and OSC_CR enable functions. When RTC_CR[OSCE] is set, the OSC is configured for low frequency, low power and the RTC_CR[SCxP] bits override the OSC_CR[SCxP] bits to control the internal capacitance configuration.
Page 67 Chapter 3 Chip Configuration Table 3-27. KL04 flash memory size Device Program flash (KB) Block 0 (P-Flash) address range MKL04Z8VFK4 0x0000_0000 – 0x0000_1FFF MKL04Z16VFK4 0x0000_0000 – 0x0000_3FFF MKL04Z32VFK4 0x0000_0000 – 0x0000_7FFF MKL04Z8VLC4 0x0000_0000 – 0x0000_1FFF MKL04Z16VLC4 0x0000_0000 – 0x0000_3FFF MKL04Z32VLC4 0x0000_0000 –...
Page 68: Flash Memory Controller Configuration
Memories and Memory Interfaces 3.6.1.3 Flash Security How flash security is implemented on this device is described in Chip Security. 3.6.1.4 Flash Modes The flash memory chapter defines two modes of operation - NVM normal and NVM special modes. On this device, The flash memory only operates in NVM normal mode. All references to NVM special mode should be ignored.
Page 69: Sram Configuration
Chapter 3 Chip Configuration Transfers Transfers Flash memory controller Figure 3-18. Flash memory controller configuration Table 3-28. Reference links to related information Topic Related module Reference Full description Flash memory Flash memory controller controller System memory map System memory map Clocking Clock Distribution Transfers...
Page 70 This device contains SRAM which could be accessed by bus masters through the cross- bar switch. The amount of SRAM for the devices covered in this document is shown in the following table. Table 3-30. KL04 SRAM memory size Device SRAM (KB) MKL04Z8VFK4 MKL04Z16VFK4 MKL04Z32VFK4 MKL04Z8VLC4 MKL04Z16VLC4 MKL04Z32VLC4...
Page 71: Analog
Chapter 3 Chip Configuration 0x2000_0000 – SRAM_size/4 SRAM_L 0x1FFF_FFFF 0x2000_0000 SRAM_U 0x2000_0000 + SRAM_size(3/4) - 1 Figure 3-20. SRAM blocks memory map For example, for a device containing 16 KB of SRAM the ranges are: • SRAM_L: 0x1FFF_F000 – 0x1FFF_FFFF •...
Page 72 The number of ADC channels present on the device is determined by the pinout of the specific device package and is shown in the following table. Table 3-32. Number of KL04 ADC channels Device Number of ADC channels MKL04Z8VFK4 MKL04Z16VFK4 MKL04Z32VFK4 MKL04Z8VLC4 MKL04Z16VLC4...
Page 73 Chapter 3 Chip Configuration Table 3-32. Number of KL04 ADC channels (continued) Device Number of ADC channels MKL04Z32VLF4 3.7.1.2 DMA Support on ADC Applications may require continuous sampling of the ADC that may have considerable load on the CPU. The ADC supports DMA request functionality for higher performance when the ADC is sampled at a very high rate.
Page 74 Analog ADC Channel Channel Input signal Input signal (SC1n[ADCH]) (SC1n[DIFF]= 1) (SC1n[DIFF]= 0) 10101 AD21 Reserved Reserved 10110 AD22 Reserved Reserved 10111 AD23 Reserved Reserved 11000 AD24 Reserved Reserved 11001 AD25 Reserved Reserved 11010 AD26 Temperature Sensor (Diff) Temperature Sensor (S.E) 11011 AD27 Bandgap (Diff)
Page 75: Cmp Configuration
Chapter 3 Chip Configuration 3.7.2 CMP Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Peripheral bridge 0 Register access Module signals Other peripherals Figure 3-22.
Page 76 Analog The CMP does not support window compare function and CMP_CR1[WE] must always be written to 0. The sample function has limited functionality since the SAMPLE input to the block is not connected to a valid input. Usage of sample operation is limited to a divided version of the bus clock (CMP_CR1[SE] = 0).
Page 77: Timers
Chapter 3 Chip Configuration is provided from the LPTMR. The LPTMR triggering output is always enabled when the LPTMR is enabled. The first signal is supplied to enable the CMP and DAC and is asserted at the same time as the TCF flag is set. The delay to the second signal that triggers the CMP to capture the result of the compare operation is dependent on the LPTMR configuration.
Page 78 Timers 3.8.1.1 TPM Instantiation Information This device contains two Low Power TPM modules (TPM). All TPM modules in the device only are configured as basic TPM function, and no quadrature decoder function and all can be functional in Stop/VLPS mode. The clock source is either external or internal in Stop/VLPS mode.
Page 79: Pit Configuration
Chapter 3 Chip Configuration Table 3-37. TPM trigger options (continued) TPMx_CONF[TRGSEL] Selected source 0001 CMP0 output 0010 Reserved 0011 Reserved 0100 PIT trigger 0 0101 PIT trigger 1 0110 Reserved 0111 Reserved 1000 TPM0 overflow 1001 TPM1 overflow 1010 Reserved 1011 Reserved 1100...
Page 80 Timers Peripheral bridge Register access Periodic interrupt timer Figure 3-24. PIT configuration Table 3-38. Reference links to related information Topic Related module Reference Full description System memory map System memory map Clocking Clock Distribution Power management Power management 3.8.2.1 PIT/DMA Periodic Trigger Assignments The PIT generates periodic trigger events to the DMA channel mux as shown in the table below.
Page 81: Low-Power Timer Configuration
Chapter 3 Chip Configuration 3.8.2.4 PIT/DAC Triggers PIT Channel 0 is configured as the DAC hardware trigger source. For more details, refer to DAC chapter. 3.8.3 Low-power timer configuration Peripheral bridge Register access Module signals Low-power timer Figure 3-25. LPT configuration Table 3-40.
Page 82: Rtc Configuration
Timers 3.8.3.2 LPTMR pulse counter input options The LPTMR_CSR[TPS] bitfield configures the input source used in pulse counter mode. The following table shows the chip-specific input assignments for this bitfield. LPTMR_CSR[TPS] Pulse counter input number Chip input CMP0 output LPTMR_ALT1 pin LPTMR_ALT2 pin LPTMR_ALT3 pin 3.8.3.3 LPTMR prescaler/glitch filter clocking options...
Page 83 Chapter 3 Chip Configuration Peripheral bridge Register access Module signals Real-time clock Figure 3-26. RTC configuration Table 3-41. Reference links to related information Topic Related module Reference Full description System memory map System memory map Clocking Clock Distribution Power management Power management 3.8.4.1 RTC Instantiation Information RTC prescaler is clocked by ERCLK32K.
Page 84: Communication Interfaces
Communication interfaces Communication interfaces 3.9.1 SPI configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Peripheral bridge Register access Module signals Figure 3-27. SPI configuration Table 3-42.
Page 85: I2C Configuration
Chapter 3 Chip Configuration 3.9.2 I2C Configuration This section summarizes how the module has been configured in the chip. For a comprehensive description of the module itself, see the module’s dedicated chapter. Peripheral bridge Register access Module signals Figure 3-28. I2C configuration Table 3-43.
Page 86 Communication interfaces Peripheral bridge Register access Module signals UART Figure 3-29. UART configuration Table 3-44. Reference links to related information Topic Related module Reference Full description UART0 UART System memory map System memory map Clocking Clock Distribution Power management Power management Signal Multiplexing Port control Signal Multiplexing...
Page 87: Human-Machine Interfaces (Hmi)
Chapter 3 Chip Configuration 3.10 Human-machine interfaces (HMI) 3.10.1 GPIO Configuration Peripheral bridge Register access Register access Module signals GPIO controller Figure 3-30. GPIO configuration Table 3-45. Reference links to related information Topic Related module Reference Full description GPIO GPIO System memory map System memory map Clocking...
Page 88: Memory Map
Human-machine interfaces (HMI) All the pins are hard wired to be pullup except for SWD_CLK. The state will be reflected in the PORTx_PCRn[PS] field. 3.10.1.2 Port Control and Interrupt Summary The following table provides more information regarding the Port Control and Interrupt configurations .
Page 89 Chapter 3 Chip Configuration address 0x4000_F000. All BME operations to the GPIO space can be accomplished referencing the aliased slot (15) at address 0x4000_F000. Only some of the BME operations can be accomplished referencing GPIO at address 0x400F_F000. KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc.
Page 90 Human-machine interfaces (HMI) KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc.
Page 91: Introduction
Chapter 4 Memory Map 4.1 Introduction This device contains various memories and memory-mapped peripherals which are located in a 4 GB memory space. This chapter describes the memory and peripheral locations within that memory space. 4.2 System memory map The following table shows the high-level device memory map. Table 4-1.
Page 92: Flash Memory Map
Flash Memory Map Table 4-1. System memory map (continued) System 32-bit Address Range Destination Slave Access 0xF000_1000–0xF000_1FFF MTB Data Watchpoint and Trace (MTBDWT) registers Cortex-M0+ core 0xF000_2000–0xF000_2FFF ROM table Cortex-M0+ core 0xF000_3000–0xF000_3FFF Miscellaneous Control Module (MCM) Cortex-M0+ core 0xF000_4000–0xF7FF_FFFF Reserved –...
Page 93: Alternate Non-Volatile Irc User Trim Description
Chapter 4 Memory Map 4.3.1 Alternate Non-Volatile IRC User Trim Description The following non-volatile locations (4 bytes) are reserved for custom IRC user trim supported by some development tools. An alternate IRC trim to the factory loaded trim can be stored at this location. To override the factory trim, user software must load new values into the MCG trim registers.
Page 94: Peripheral Bridge (Aips-Lite) Memory Map
Peripheral bridge (AIPS-Lite) memory map 4.6 Peripheral bridge (AIPS-Lite) memory map The peripheral memory map is accessible via one slave port on the crossbar in the 0x4000_0000–0x400F_FFFF region. The device implements one peripheral bridge that defines a 1024 KB address space. The three regions associated with this space are: •...
Page 95: Peripheral Bridge (Aips-Lite) Memory Map
Chapter 4 Memory Map 4.6.2 Peripheral Bridge (AIPS-Lite) Memory Map Table 4-2. Peripheral bridge 0 slot assignments System 32-bit base address Slot Module number 0x4000_0000 — 0x4000_1000 — 0x4000_2000 — 0x4000_3000 — 0x4000_4000 — 0x4000_5000 — 0x4000_6000 — 0x4000_7000 — 0x4000_8000 DMA controller 0x4000_9000...
Page 96 Peripheral bridge (AIPS-Lite) memory map Table 4-2. Peripheral bridge 0 slot assignments (continued) System 32-bit base address Slot Module number 0x4002_3000 — 0x4002_4000 — 0x4002_5000 — 0x4002_6000 — 0x4002_7000 — 0x4002_8000 — 0x4002_9000 — 0x4002_A000 — 0x4002_B000 — 0x4002_C000 — 0x4002_D000 —...
Page 97 Chapter 4 Memory Map Table 4-2. Peripheral bridge 0 slot assignments (continued) System 32-bit base address Slot Module number 0x4004_A000 Port B multiplexing control 0x4004_B000 — 0x4004_C000 — 0x4004_D000 — 0x4004_E000 — 0x4004_F000 — 0x4005_0000 — 0x4005_1000 — 0x4005_2000 — 0x4005_3000 —...
Page 98: Modules Restricted Access In User Mode
Private Peripheral Bus (PPB) memory map Table 4-2. Peripheral bridge 0 slot assignments (continued) System 32-bit base address Slot Module number 0x4007_1000 — 0x4007_2000 — 0x4007_3000 Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) 0x4007_4000 — 0x4007_5000 — 0x4007_6000 SPI 0 0x4007_7000 —...
Page 99: Kl04 Sub-Family Reference Manual, Rev. 3.1, November
Chapter 4 Memory Map Table 4-3. PPB memory map (continued) System 32-bit Address Range Resource Additional Range Detail Resource 0xE000_E000–0xE000_EFFF System Control Space 0xE000_E000–0xE000_E00F Reserved (SCS) 0xE000_E010–0xE000_E0FF SysTick 0xE000_E100–0xE000_ECFF NVIC 0xE000_ED00–0xE000_ED8F System Control Block 0xE000_ED90–0xE000_EDEF Reserved 0xE000_EDF0–0xE000_EEFF Debug 0xE000_EF00–0xE000_EFFF Reserved 0xE000_F000–0xE00F_EFFF Reserved 0xE00F_F000–0xE00F_FFFF...
Page 100 Private Peripheral Bus (PPB) memory map KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc.
Page 101: Clock Distribution
Chapter 5 Clock Distribution 5.1 Introduction This chapter presents the clock architecture for the device, the overview of the clocks and includes a terminology section. The Cortex M0+ resides within a synchronous core platform, where the processor and bus masters, Flash and peripherals clocks can be configured independently. The clock distribution figure shows how clocks from the MCG and XOSC modules are distributed to the microcontroller’s other function units.
Page 102: Clock Definitions
Clock definitions 4 MHz IRC FCRDIV Clock options for MCGIRCLK some peripherals 32 kHz IRC (see note) Core clock, OUTDIV1 platform clock, and system clock MCGOUTCLK Bus clock/ Flash clock OUTDIV4 FRDIV MCGFLLCLK System oscillator EXTAL0 OSCCLK XTAL_CLK OSCERCLK XTAL0 logic ERCLK32K OSC32KCLK...
Page 103: Device Clock Summary
Chapter 5 Clock Distribution Clock name Description Flash clock Flash memory clock. On this device it is the same as Bus clock. MCGIRCLK MCG output of the slow or fast internal reference clock MCGOUTCLK MCG output of either IRC, MCGFLLCLK or MCG's external reference clock that sources the core, system, bus, and flash clock.
Page 104 Clock definitions Table 5-1. Clock Summary (continued) Clock name Run mode VLPR mode Clock source Clock is disabled when… clock frequency clock frequency Flash clock Up to 24 MHz Up to 1 MHz in BLPE MCGOUTCLK clock In all stop modes divider except for partial Up to 800 kHz in BLPI...
Page 105: Internal Clocking Requirements
Chapter 5 Clock Distribution 5.5 Internal clocking requirements The clock dividers are programmed via the SIM module’s CLKDIV registers. The following requirements must be met when configuring the clocks for this device: 1. The core, platform, and system clock are programmable from a divide-by-1 through divide-by-16 setting.
Page 106: Vlpr Mode Clocking
Clock Gating The flash erased state defaults to fast clocking mode, since these bits reside in flash, which is logic 1 in the flash erased state. To enable a lower power boot option, program the appropriate bits in FTFA_FOPT. During the reset sequence, if either of the control bits is cleared, the system is in a slower clock configuration.
Page 107: Pmc 1-Khz Lpo Clock
Chapter 5 Clock Distribution Table 5-2. Module clocks Module Bus interface clock Internal clocks I/O interface clocks Core modules ARM Cortex-M0+ core Platform clock Core clock — NVIC Platform clock — — Platform clock — SWD_CLK System modules System clock —...
Page 108: Cop Clocking
Module clocks 5.7.1 PMC 1-kHz LPO clock The Power Management Controller (PMC) generates a 1-kHz clock that is enabled in all modes of operation, including all low power modes except VLLS0. This 1-kHz source is commonly referred to as LPO clock or 1-kHz LPO clock. 5.7.2 COP clocking The COP may be clocked from two clock sources as shown in the following figure.
Page 109: Lptmr Clocking
Chapter 5 Clock Distribution 5.7.4 LPTMR clocking The prescaler and glitch filters in each of the LPTMRx modules can be clocked as shown in the following figure. NOTE The chosen clock must remain enabled if the LPTMRx is to continue operating in all required low-power modes. MCGIRCLK LPTMRx prescaler/glitch ERCLK32K...
Page 110: Uart Clocking
Module clocks MCGIRCLK OSCERCLK TPM clock MCGFLLCLK SIM_SOPT2[TPMSRC] Figure 5-5. TPM clock generation 5.7.6 UART clocking The UART0 module has a selectable clock as shown in the following figure. NOTE The chosen clock must remain enabled if the UART0 is to continue operating in all required low-power modes.
Page 111: Reset And Boot
Chapter 6 Reset and Boot 6.1 Introduction The following reset sources are supported in this MCU: Table 6-1. Reset sources Reset sources Description POR reset • Power-on reset (POR) System resets • External pin reset (PIN) • Low-voltage detect (LVD) •...
Page 112: Power-On Reset (Por)
Reset 6.2.1 Power-on reset (POR) When power is initially applied to the MCU or when the supply voltage drops below the power-on reset re-arm voltage level (V ), the POR circuit causes a POR reset condition. As the supply voltage rises, the LVD circuit holds the MCU in reset until the supply has risen above the LVD low threshold (V ).
Page 113 Chapter 6 Reset and Boot 6.2.2.1.1 Reset pin filter The RESET pin filter supports filtering from both the 1 kHz LPO clock and the bus clock. The RPFC[RSTFLTSS], RPFC[RSTFLTSRW], and RPFW[RSTFLTSEL] fields in the reset control (RCM) register set control this functionality; see the RCM chapter. The filters are asynchronously reset by Chip POR.
Page 114 Reset 6.2.2.4 Low leakage wakeup (LLWU) The LLWU module provides the means for a number of external pins and a number of internal peripherals to wake the MCU from low leakage power modes. The LLWU module is functional only in low leakage power modes. In VLLSx modes, all enabled inputs to the LLWU can generate a system reset.
Page 115: Mcu Resets
Chapter 6 Reset and Boot 6.2.2.7 Software reset (SW) The SYSRESETREQ bit in the NVIC application interrupt and reset control register can be set to force a software reset on the device. (See ARM's NVIC documentation for the full description of the register fields, especially the VECTKEY field requirements.) Setting SYSRESETREQ generates a software reset request.
Page 116: Reset Pin
Reset 6.2.3.2 Chip POR not VLLS The Chip POR not VLLS reset asserts on POR and LVD reset sources. It resets parts of the SMC and SIM. It also resets the LPTMR. The Chip POR not VLLS reset also causes these resets to occur: Chip POR, Chip Reset not VLLS, and Chip Reset (including Early Chip Reset).
Page 117: Debug Resets
Chapter 6 Reset and Boot 6.2.4 Reset Pin For all reset sources except a VLLS Wakeup that does not occur via the RESET pin, the RESET pin is driven low by the MCU for at least 128 bus clock cycles and until flash initialization has completed.
Page 118: Boot
Boot 6.3 Boot This section describes the boot sequence, including sources and options. Some configuration information such as clock trim values stored in factory programmed flash locations is autoloaded. 6.3.1 Boot sources The CM0+ core adds support for a programmable Vector Table Offset Register (VTOR) to relocate the exception vector table.
Page 119: Boot Sequence
Chapter 6 Reset and Boot Table 6-2. Flash Option Register (FTFA_FOPT) Bit Definitions (continued) Field Value Definition FAST_INIT Select initialization speed on POR, VLLSx, and any system reset . Slower initialization. The Flash initialization will be slower with the benefit of reduced average current during this time.
Page 120 Boot 1. A system reset is held on internal logic, the RESET pin is driven out low, and the MCG is enabled in its default clocking mode. 2. Required clocks are enabled (System Clock, Flash Clock, and any Bus Clocks that do not have clock gate control reset to disabled).
Page 121: Power Management
Chapter 7 Power Management 7.1 Introduction This chapter describes the various chip power modes and functionality of the individual modules in these modes. 7.2 Clocking Modes This sections describes the various clocking modes supported on this device. 7.2.1 Partial Stop Partial Stop is a clocking option that can be taken instead of entering STOP mode and is configured in the SMC Stop Control Register (SMC_STOPCTRL).
Page 122: Dma Wakeup
Clocking Modes When configured for PSTOP1, both the system clock and bus clock are gated. All bus masters and bus slaves enter Stop mode, but the clock generators in the MCG and the on- chip regulator in the PMC remain in Run (or VLP Run) mode. Exit from PSTOP1 can be initiated by a reset or an asynchronous interrupt from a bus master or bus slave.
Page 123: Compute Operation
Chapter 7 Power Management NOTE If the requested DMA transfer cannot cause the DMA request to negate then the device will remain in a higher power state until the low power mode is fully exited. An enabled DMA wakeup can cause an aborted entry into the low power mode, if the DMA request asserts during the stop mode entry sequence (or reentry if the request asserts during a DMA wakeup) and can cause the SMC to assert its Stop Abort flag.
Page 124: Peripheral Doze
Clocking Modes During Compute Operation, the AIPS peripheral space is disabled and attempted accesses generate bus errors. The private peripheral space remains accessible during Compute Operation, including the MCM, NVIC, IOPORT and SysTick. Although access to the GPIO registers via the IOPORT is supported, the GPIO port data input registers do not return valid data since clocks are disabled to the Port Control and Interrupt modules.
Page 125: Clock Gating
Chapter 7 Power Management Peripheral Doze can therefore be used to disable selected bus masters or slaves for the duration of WAIT or VLPW mode. It can also be used to disable selected bus slaves immediately on entry into any stop mode (or Compute Operation), instead of waiting for the bus masters to acknowledge the entry as part of the stop entry sequence.
Page 126 Power modes The three primary modes of operation are run, wait and stop. The WFI instruction invokes both wait and stop modes for the chip. The primary modes are augmented in a number of ways to provide lower power based on application needs. Table 7-1.
Page 127: Entering And Exiting Power Modes
Chapter 7 Power Management Table 7-1. Chip power modes (continued) Chip mode Description Core mode Normal recovery method VLLS1 (Very Most peripherals are disabled (with clocks stopped), but OSC, LLWU, Sleep Deep Wakeup Reset Low Leakage LPTMR, RTC, CMP can be used. NVIC is disabled; LLWU is used to Stop1) wake up.
Page 128 Module Operation in Low Power Modes (Debug modules are discussed separately; see Debug in Low Power Modes.) Number ratings (such as 4 MHz and 1 Mbps) represent the maximum frequencies or maximum data rates per mode. Also, these terms are used: •...
Page 129 Chapter 7 Power Management Table 7-2. Module operation in low power modes (continued) Modules VLPR VLPW Stop VLPS VLLSx Core clock 4 MHz max Platform clock 4 MHz max 4 MHz max System clock 4 MHz max 4 MHz max OFF in CPO Bus clock 1 MHz max...
Page 130 Module Operation in Low Power Modes Table 7-2. Module operation in low power modes (continued) Modules VLPR VLPW Stop VLPS VLLSx Async operation Async operation Async operation Async operation Async operation FF in PSTOP2 in CPO Analog 12-bit ADC ADC internal ADC internal static clock only...
Page 131: Security
Chapter 8 Security 8.1 Introduction This device implements security based on the mode selected from the flash module. The following sections provide an overview of flash security and details the effects of security on non-flash modules. 8.2 Flash Security The flash module provides security information to the MCU based on the state held by the FSEC[SEC] bits.
Page 132: Security Interactions With Debug
Security Interactions with other Modules 8.3.1 Security Interactions with Debug When flash security is active the SWD port cannot access the memory resources of the MCU. Although most debug functions are disabled, the debugger can write to the Flash Mass Erase in Progress bit to trigger a mass erase (Erase All Blocks) command.
Page 133: Debug
Chapter 9 Debug 9.1 Introduction This device's debug is based on the ARM CoreSight architecture and is configured to provide the maximum flexibility as allowed by the restrictions of the pinout and other available resources. It provides register and memory accessibility from the external debugger interface, basic run/halt control plus 2 breakpoints and 2 watchpoints.
Page 134: Swd Status And Control Registers
SWD status and control registers 9.3 SWD status and control registers Through the ARM Debug Access Port (DAP), the debugger has access to the status and control elements, implemented as registers on the DAP bus as shown in the following figure.
Page 135: Mdm-Ap Control Register
Chapter 9 Debug DPACC APACC Data[31:0] A[3:2] RnW Data[31:0] A[3:2] RnW SW-DP See the ARM Debug Interface v5p1 Supplement. Generic Debug Port (DP) APSEL Data[31:0] A[7:4] A[3:2] RnW Decode SELECT[31:24] (APSEL) selects the AP SELECT[7:4] (APBANKSEL) selects the bank A[3:2] from the APACC selects the register within the bank AHB-AP SELECT[31:24] = 0x00 selects the AHB-AP...
Page 136: Mdm-Ap Status Register
SWD status and control registers Table 9-3. MDM-AP Control register assignments (continued) Name Secure Description Debug Request Set to force the core to halt. If the core is in a stop or wait mode, this bit can be used to wakeup the core and transition to a halted state.
Page 137 Chapter 9 Debug 9.3.2 MDM-AP Status Register Table 9-4. MDM-AP Status register assignments Name Description Flash Mass Erase Acknowledge The Flash Mass Erase Acknowledge bit is cleared after any system reset. The bit is also cleared at launch of a mass erase command due to write of Flash Mass Erase in Progress bit in MDM AP Control Register.
Page 138: Debug Resets
Debug Resets Table 9-4. MDM-AP Status register assignments (continued) Name Description LLS Mode Exit This bit indicates an exit from LLS mode has occurred. The debugger will lose communication while the system is in LLS (including access to this register). Once communication is reestablished, this bit indicates that the system had been in LLS.
Page 139: Micro Trace Buffer (Mtb)
Chapter 9 Debug 9.5 Micro Trace Buffer (MTB) The Micro Trace Buffer (MTB) provides a simple execution trace capability for the Cortex-M0+ processor. When enabled, the MTB records changes in program flow reported by the Cortex-M0+ processor, via the execution trace interface, into a configurable region of the SRAM.
Page 140: Kl04 Sub-Family Reference Manual, Rev. 3.1, November
Debug & Security KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc.
Page 141: Introduction
Chapter 10 Signal Multiplexing and Signal Descriptions 10.1 Introduction To optimize functionality in small packages, pins have several functions available via signal multiplexing. This chapter illustrates which of this device's signals are multiplexed on which external pin. Port Control block controls which signal is present on the external pin. Reference that chapter to find which register controls the operation of a specific pin.
Page 142: Port Control And Interrupt Module Features
Signal Multiplexing Integration Table 10-1. Reference links to related information (continued) Topic Related module Reference Clocking Clock Distribution Register access Peripheral bus Peripheral bridge controller 10.2.1 Port control and interrupt module features • 32-pin ports NOTE Not all pins are available on the device. See the following section for details.
Page 143: Clock Gating
Chapter 10 Signal Multiplexing and Signal Descriptions Table 10-2. Port control register configuration summary (continued) This field Generally Except for Resets to Configurability resets to PORTx_PC No exceptions - all are cleared on reset. — 1. The RESET pin has the passive analog filter fixed enabled when functioning as the RESET pin (FOPT[RESET_PIN_CFG] = 1) and fixed disabled when configured for other shared functions.
Page 144 Pinout Pin Name Default ALT0 ALT1 ALT2 ALT3 LQFP LQFP — — — PTA14 DISABLED DISABLED PTA14 TPM_CLKIN0 — — — PTA15 DISABLED DISABLED PTA15 CLKOUT VREFH VREFH VREFH VREFL VREFL VREFL PTA3 EXTAL0 EXTAL0 PTA3 I2C0_SCL I2C0_SDA PTA4/ XTAL0 XTAL0 PTA4/ I2C0_SDA...
Page 145: Kl04 Pinouts
Chapter 10 Signal Multiplexing and Signal Descriptions Pin Name Default ALT0 ALT1 ALT2 ALT3 LQFP LQFP — PTA10/ DISABLED DISABLED PTA10/ IRQ_12 IRQ_12 — PTA11/ DISABLED DISABLED PTA11/ IRQ_13 IRQ_13 PTB3/ DISABLED DISABLED PTB3/ I2C0_SCL UART0_TX IRQ_14 IRQ_14 PTB4/ DISABLED DISABLED PTB4/ I2C0_SDA...
Page 146 Pinout PTB4/IRQ_15/LLWU_P6 PTB6/IRQ_2/LPTMR0_ALT3 PTB3/IRQ_14 PTB7/IRQ_3 PTA11/IRQ_13 PTA14 PTA10/IRQ_12 PTA15 PTB14/IRQ_11 VREFH VREFL PTB20 PTA3 PTA9 PTA4/LLWU_P0 PTA8 PTB2/IRQ_10/LLWU_P5 PTB18 PTB1/IRQ_9 Figure 10-2. KL04 48-pin LQFP pinout diagram KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc.
Page 147 Chapter 10 Signal Multiplexing and Signal Descriptions PTB4/IRQ_15/LLWU_P6 PTB6/IRQ_2/LPTMR0_ALT3 PTB3/IRQ_14 PTB7/IRQ_3 PTA11/IRQ_13 VREFH PTA10/IRQ_12 VREFL PTA9 PTA8 PTA3 PTB2/IRQ_10/LLWU_P5 PTA4/LLWU_P0 PTB1/IRQ_9 Figure 10-3. KL04 32-pin LQFP pinout diagram KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc.
Page 148 Pinout PTB4/IRQ_15/LLWU_P6 PTB6/IRQ_2/LPTMR0_ALT3 PTB3/IRQ_14 PTB7/IRQ_3 PTA11/IRQ_13 VREFH PTA10/IRQ_12 VREFL PTA9 PTA8 PTA3 PTB2/IRQ_10/LLWU_P5 PTA4/LLWU_P0 PTB1/IRQ_9 Figure 10-4. KL04 32-pin QFN pinout diagram KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc.
Page 149: Module Signal Description Tables
Chapter 10 Signal Multiplexing and Signal Descriptions PTB4/IRQ_15/LLWU_P6 PTB6/IRQ_2/LPTMR0_ALT3 PTB3/IRQ_14 PTB7/IRQ_3 PTA9 VDD VREFH PTA8 VREFL VSS PTA3 PTB2/IRQ_10/LLWU_P5 PTA4/LLWU_P0 PTB1/IRQ_9 Figure 10-5. KL04 24-pin QFN pinout diagram 10.4 Module Signal Description Tables The following sections correlate the chip-level signal name with the signal name used in the module's chapter.
Page 150: System Modules
Module Signal Description Tables Table 10-3. SWD Signal Descriptions (continued) Chip signal name Module signal Description name SWD_CLK SWD_CLK Serial Wire Clock. This pin is the clock for debug logic when in the Input Serial Wire Debug mode. This pin is pulled down internally. 10.4.2 System Modules Table 10-4.
Page 151: Analog
Chapter 10 Signal Multiplexing and Signal Descriptions 10.4.5 Analog Table 10-6. ADC 0 Signal Descriptions Chip signal name Module signal Description name ADC0_SEn Single-Ended Analog Channel Inputs VREFH Voltage Reference Select High REFSH VREFL Voltage Reference Select Low REFSL VDDA Analog Power Supply VSSA Analog Ground...
Page 152: Communication Interfaces
Module Signal Description Tables Table 10-11. RTC Signal Descriptions Chip signal name Module signal Description name RTC_CLKOUT RTC_CLKOUT 1 Hz square-wave output 1. RTC_CLKOUT can also be driven with OSCERCLK via SIM control bit SIM_SOPT[RCTCLKOUTSEL] 10.4.7 Communication Interfaces Table 10-12. SPI0 Signal Descriptions Chip signal name Module signal Description...
Page 153: Introduction
Chapter 11 Port control and interrupts (PORT) 11.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. 11.2 Overview The port control and interrupt (PORT) module provides support for port control, and external interrupt functions. Most functions can be configured independently for each pin in the 32-bit port and affect the pin regardless of its pin muxing state.
Page 154: Modes Of Operation
External signal description • Individual pull control fields with pullup, pulldown, and pull-disablesupport on selected pins • Individual drive strength field supporting high and low drive strength on selected pins • Individual slew rate field supporting fast and slow slew rates on selected pins •...
Page 155: Detailed Signal Description
Chapter 11 Port control and interrupts (PORT) Table 11-1. Signal properties Name Function Reset Pull PORTx[31:0] External interrupt NOTE Not all pins within each port are implemented on each device. 11.4 Detailed signal description The following table contains the detailed signal description for the PORT interface. Table 11-2.
Page 156: Kl04 Sub-Family Reference Manual, Rev. 3.1, November
Memory map and register definition PORT memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4004_9020 Pin Control Register n (PORTA_PCR8) See section 11.5.1/158 4004_9024 Pin Control Register n (PORTA_PCR9) See section 11.5.1/158 4004_9028 Pin Control Register n (PORTA_PCR10) See section...
Page 157 Chapter 11 Port control and interrupts (PORT) PORT memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4004_A020 Pin Control Register n (PORTB_PCR8) See section 11.5.1/158 4004_A024 Pin Control Register n (PORTB_PCR9) See section 11.5.1/158 4004_A028 Pin Control Register n (PORTB_PCR10)
Page 158: Pin Control Register N (Portx_Pcrn)
Memory map and register definition 11.5.1 Pin Control Register n (PORTx_PCRn) NOTE Refer to the Signal Multiplexing and Pin Assignment chapter for the reset value of this device. See the GPIO Configuration section for details on the available functions for each pin. Do not modify pin configuration registers associated with pins not available in your selected package.
Page 159 Chapter 11 Port control and interrupts (PORT) PORTx_PCRn field descriptions (continued) Field Description Configured interrupt is not detected. Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag.
Page 160: Global Pin Control Low Register (Portx_Gpclr)
Memory map and register definition PORTx_PCRn field descriptions (continued) Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. Passive Filter Enable This bit is read only for pins that do not support a configurable passive input filter. Passive filter configuration is valid in all digital pin muxing modes.
Page 161: Global Pin Control High Register (Portx_Gpchr)
Chapter 11 Port control and interrupts (PORT) PORTx_GPCLR field descriptions Field Description 31–16 Global Pin Write Enable GPWE Selects which Pin Control Registers (15 through 0) bits [15:0] update with the value in GPWD. Corresponding Pin Control Register is not updated with the value in GPWD. Corresponding Pin Control Register is updated with the value in GPWD.
Page 162: Functional Description
Functional description Address: Base address + A0h offset Reset PORTx_ISFR field descriptions Field Description 31–0 Interrupt Status Flag Each bit in the field indicates the detection of the configured interrupt of the same number as the field. Configured interrupt is not detected. Configured interrupt is detected.
Page 163: Global Pin Control
Chapter 11 Port control and interrupts (PORT) When the Pin Muxing mode is configured for analog or is disabled, all the digital functions on that pin are disabled. This includes the pullup and pulldown enables, and passive filter enable. The configuration of each pin control register is retained when the PORT module is disabled.
Page 164 Functional description The PORT module generates a single interrupt that asserts when the interrupt status flag is set for any enabled interrupt for that port. The interrupt negates after the interrupt status flags for all enabled interrupts have been cleared by writing a logic 1 to the ISF flag in either the PORT_ISFR or PORT_PCRn registers.
Page 165: Introduction
Chapter 12 System integration module (SIM) 12.1 Introduction The system integration module (SIM) provides system control and chip configuration registers. 12.1.1 Features • System clocking configuration • System clock divide values • Architectural clock gating control • ERCLK32K clock selection •...
Page 166 Memory map and register definition NOTE The SIM registers can be written only in supervisor mode. In user mode, write accesses are blocked and will result in a bus error. NOTE The SIM_SOPT1 and SIM_SOPT1CFG registers are located at a different base address than the other SIM registers. SIM memory map Absolute Width...
Page 167: System Options Register 1 (Sim_Sopt1)
Chapter 12 System integration module (SIM) 12.2.1 System Options Register 1 (SIM_SOPT1) NOTE The SOPT1 register is only reset on POR or LVD. Address: 4004_7000h base + 0h offset = 4004_7000h OSC32KSEL Reset Reset SIM_SOPT1 field descriptions Field Description 31–20 This field is reserved.
Page 168: System Options Register 2 (Sim_Sopt2)
Memory map and register definition SIM_SOPT1CFG field descriptions Field Description 31–24 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 23–0 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 12.2.3 System Options Register 2 (SIM_SOPT2) SOPT2 contains the controls for selecting many of the module clock source options on this device.
Page 169 Chapter 12 System integration module (SIM) SIM_SOPT2 field descriptions (continued) Field Description Selects the clock source for the TPM counter clock Clock disabled MCGFLLCLK clock OSCERCLK clock MCGIRCLK clock 23–18 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 17–16 This field is reserved.
Page 170: System Options Register 4 (Sim_Sopt4)
Memory map and register definition 12.2.4 System Options Register 4 (SIM_SOPT4) Address: 4004_7000h base + 100Ch offset = 4004_800Ch Reset Reset SIM_SOPT4 field descriptions Field Description 31–27 This field is reserved. Reserved This read-only field is reserved and always has the value 0. This field is reserved.
Page 171: System Options Register 5 (Sim_Sopt5)
Chapter 12 System integration module (SIM) SIM_SOPT4 field descriptions (continued) Field Description TPM1 channel 0 input capture source select TPM1CH0SRC Selects the source for TPM1 channel 0 input capture. NOTE: When TPM1 is not in input capture mode, clear this field. TPM1_CH0 signal CMP0 output 17–0...
Page 172: System Options Register 7 (Sim_Sopt7)
Memory map and register definition SIM_SOPT5 field descriptions (continued) Field Description 15–7 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 6–4 This field is reserved. Reserved This read-only field is reserved and always has the value 0. This field is reserved.
Page 173 Chapter 12 System integration module (SIM) SIM_SOPT7 field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. ADC0 alternate trigger enable ADC0ALTTRGEN Enable alternative conversion triggers for ADC0. TPM1 channel 0 (A) and channel 1 (B) triggers selected for ADC0. Alternate trigger selected for ADC0.
Page 174: System Device Identification Register (Sim_Sdid)
Memory map and register definition 12.2.7 System Device Identification Register (SIM_SDID) Address: 4004_7000h base + 1024h offset = 4004_8024h FAMID SUBFAMID SERIESID SRAMSIZE REVID DIEID PINID Reset * Notes: • FAMID field: Device specific value. • SUBFAMID field: Device specific value. •...
Page 175 Chapter 12 System integration module (SIM) SIM_SDID field descriptions (continued) Field Description 0110 32 KB 0111 64 KB 15–12 Device revision number REVID Specifies the silicon implementation number for the device. 11–7 Device die number DIEID Specifies the silicon implementation number for the device. 6–4 This field is reserved.
Page 176: System Clock Gating Control Register 4 (Sim_Scgc4)
Memory map and register definition 12.2.8 System Clock Gating Control Register 4 (SIM_SCGC4) Address: 4004_7000h base + 1034h offset = 4004_8034h SPI0 Reset I2C0 Reset SIM_SCGC4 field descriptions Field Description 31–28 This field is reserved. Reserved This read-only field is reserved and always has the value 1. 27–24 This field is reserved.
Page 177: System Clock Gating Control Register 5 (Sim_Scgc5)
Chapter 12 System integration module (SIM) SIM_SCGC4 field descriptions (continued) Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. UART0 Clock Gate Control UART0 This bit controls the clock gate to the UART0 module. Clock disabled Clock enabled 9–8...
Page 178 Memory map and register definition SIM_SCGC5 field descriptions (continued) Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. 18–14 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 13–11 This field is reserved.
Page 179: System Clock Gating Control Register 6 (Sim_Scgc6)
Chapter 12 System integration module (SIM) 12.2.10 System Clock Gating Control Register 6 (SIM_SCGC6) Address: 4004_7000h base + 103Ch offset = 4004_803Ch Reset Reset SIM_SCGC6 field descriptions Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. This field is reserved.
Page 180: System Clock Gating Control Register 7 (Sim_Scgc7)
Memory map and register definition SIM_SCGC6 field descriptions (continued) Field Description Clock disabled Clock enabled PIT Clock Gate Control This bit controls the clock gate to the PIT module. Clock disabled Clock enabled 22–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. This field is reserved.
Page 181: System Clock Divider Register 1 (Sim_Clkdiv1)
Chapter 12 System integration module (SIM) SIM_SCGC7 field descriptions (continued) Field Description DMA Clock Gate Control This bit controls the clock gate to the DMA module. Clock disabled Clock enabled 7–0 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 12.2.12 System Clock Divider Register 1 (SIM_CLKDIV1) NOTE The CLKDIV1 register cannot be written to when the device is...
Page 182 Memory map and register definition SIM_CLKDIV1 field descriptions (continued) Field Description 1000 Divide-by-9. 1001 Divide-by-10. 1010 Divide-by-11. 1011 Divide-by-12. 1100 Divide-by-13. 1101 Divide-by-14. 1110 Divide-by-15. 1111 Divide-by-16. 27–19 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 18–16 Clock 4 output divider value OUTDIV4...
Page 183: Flash Configuration Register 1 (Sim_Fcfg1)
Chapter 12 System integration module (SIM) 12.2.13 Flash Configuration Register 1 (SIM_FCFG1) Address: 4004_7000h base + 104Ch offset = 4004_804Ch PFSIZE Reset Reset * Notes: • PFSIZE field: Device specific value. SIM_FCFG1 field descriptions Field Description 31–28 This field is reserved. Reserved This read-only field is reserved and always has the value 0.
Page 184: Flash Configuration Register 2 (Sim_Fcfg2)
Memory map and register definition SIM_FCFG1 field descriptions (continued) Field Description 23–2 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Flash Doze FLASHDOZE When set, Flash memory is disabled for the duration of Doze mode. This bit should be clear during VLP modes.
Page 185: Unique Identification Register Mid-High (Sim_Uidmh)
Chapter 12 System integration module (SIM) SIM_FCFG2 field descriptions (continued) Field Description For example, if MAXADDR0 = 0x10 the first invalid address of program flash is 0x0002_0000. This would be the MAXADDR0 value for a device with 128 KB program flash. This field is reserved.
Page 186: Kl04 Sub-Family Reference Manual, Rev. 3.1, November
Memory map and register definition SIM_UIDML field descriptions Field Description 31–0 Unique Identification Unique identification for the device. 12.2.17 Unique Identification Register Low (SIM_UIDL) Address: 4004_7000h base + 1060h offset = 4004_8060h Reset * Notes: • UID field: Device specific value. SIM_UIDL field descriptions Field Description...
Page 187: Service Cop Register (Sim_Srvcop)
Chapter 12 System integration module (SIM) SIM_COPC field descriptions Field Description 31–4 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 3–2 COP Watchdog Timeout COPT These write-once bits select the timeout period of the COP. The COPT field along with the COPCLKS bit define the COP timeout period.
Page 188: Functional Description
Functional description 12.3 Functional description Introduction section. KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc.
Page 189: Introduction
Chapter 13 System Mode Controller (SMC) 13.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The system mode controller (SMC) is responsible for sequencing the system into and out of all low power stop and run modes. Specifically, it monitors events to trigger transitions between power modes while controlling the power, clocks, and memories of the system to achieve the power consumption and functionality of that mode.
Page 190 Modes of operation ARM CPU mode MCU mode Sleep Wait Deep Sleep Stop Accordingly, the ARM CPU documentation refers to sleep and deep sleep, while the Freescale MCU documentation normally uses wait and stop. In addition, Freescale MCUs also augment stop, wait, and run modes in a number of ways.
Page 191: Memory Map And Register Descriptions
Chapter 13 System Mode Controller (SMC) Table 13-1. Power modes (continued) Mode Description VLLS3 The core clock is gated off. System clocks to other masters and bus clocks are gated off after all stop acknowledge signals from supporting peripherals are valid. The MCU is placed in a low leakage mode by powering down the internal logic.
Page 192 Memory map and register descriptions The PMPROT register can be written only once after any system reset. If the MCU is configured for a disallowed or reserved power mode, the MCU remains in its current power mode. For example, if the MCU is in normal RUN mode and AVLP is 0, an attempt to enter VLPR mode using PMCTRL[RUNM] is blocked and the RUNM bits remain 00b, indicating the MCU is still in Normal Run mode.
Page 193: Power Mode Control Register (Smc_Pmctrl)
Chapter 13 System Mode Controller (SMC) 13.3.2 Power Mode Control register (SMC_PMCTRL) The PMCTRL register controls entry into low-power run and stop modes, provided that the selected power mode is allowed via an appropriate setting of the protection (PMPROT) register. NOTE This register is reset on Chip POR not VLLS and by reset types that trigger Chip POR not VLLS.
Page 194: Stop Control Register (Smc_Stopctrl)
Memory map and register descriptions SMC_PMCTRL field descriptions (continued) Field Description 2–0 Stop Mode Control STOPM When written, controls entry into the selected stop mode when Sleep-Now or Sleep-On-Exit mode is entered with SLEEPDEEP=1 . Writes to this field are blocked if the protection level has not been enabled using the PMPROT register.
Page 195: Power Mode Status Register (Smc_Pmstat)
Chapter 13 System Mode Controller (SMC) SMC_STOPCTRL field descriptions (continued) Field Description clocks are gated allowing peripherals running on bus clock to remain fully functional. In PSTOP1, both system and bus clocks are gated. STOP - Normal Stop mode PSTOP1 - Partial Stop with both system and bus clocks disabled PSTOP2 - Partial Stop with system clock disabled and bus clock enabled Reserved POR Power Option...
Page 196: Functional Description
Functional description Address: 4007_E000h base + 3h offset = 4007_E003h Read PMSTAT Write Reset SMC_PMSTAT field descriptions Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. 6–0 NOTE: When debug is enabled, the PMSTAT will not update to STOP or VLPS PMSTAT NOTE: When a PSTOP mode is enabled, the PMSTAT will not update to STOP or VLPS 000_0001...
Page 197 Chapter 13 System Mode Controller (SMC) Any RESET VLPW VLPR WAIT STOP VLPS VLLS 3, 1, 0 Figure 13-5. Power mode state diagram The following table defines triggers for the various state transitions shown in the previous figure. Table 13-7. Power mode transition triggers Transition # From Trigger conditions...
Page 198 Functional description Table 13-7. Power mode transition triggers (continued) Transition # From Trigger conditions STOP PMCTRL[RUNM]=00, PMCTRL[STOPM]=000 Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core. See note. STOP Interrupt or Reset VLPR The core, system, bus and flash clock frequencies are restricted in this mode.
Page 199: Power Mode Entry/Exit Sequencing
Chapter 13 System Mode Controller (SMC) Table 13-7. Power mode transition triggers (continued) Transition # From Trigger conditions PMPROT[ALLS]=1, PMCTRL[STOPM]=011, Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is controlled in System Control Register in ARM core. Wakeup from enabled LLWU input source or RESET pin. VLPR PMPROT[ALLS]=1, PMCTRL[STOPM]=011, Sleep-now or sleep-on-exit modes entered with SLEEPDEEP set, which is...
Page 200 Functional description Reset Control Low - Module Leakage (RCM) Wakeup (LLWU) Stop/Wait LP exit LP exit System Bus masters low power bus (non-CPU) Clock Mode CCM low power bus Control Bus slaves low power bus Controller Module (SMC) (CCM) PMC low power bus Flash low power bus MCG enable System...
Page 201: Run Modes
Chapter 13 System Mode Controller (SMC) 13.4.2.2 Stop mode exit sequence Exit from a low-power stop mode is initiated either by a reset or an interrupt event. The following sequence then executes to restore the system to a run mode (RUN or VLPR): 1.
Page 202 Functional description 13.4.3.1 RUN mode This is the normal operating mode for the device. This mode is selected after any reset. When the ARM processor exits reset, it sets up the stack, program counter (PC), and link register (LR): • The processor reads the start SP (SP_main) from vector-table offset 0x000 •...
Page 203: Wait Modes
Chapter 13 System Mode Controller (SMC) To reenter Normal Run mode, clear RUNM. The PMSTAT register is a read-only status register that can be used to determine when the system has completed an exit to RUN mode. When PMSTAT=RUN, the system is in run regulation and the MCU can run at full speed in any clock mode.
Page 204: Stop Modes
Functional description When an interrupt from VLPW occurs, the device returns to VLPR mode to execute the interrupt service routine. A system reset will cause an exit from VLPW mode, returning the device to normal RUN mode. 13.4.5 Stop modes This device contains a variety of stop modes to meet your application needs.
Page 205 Chapter 13 System Mode Controller (SMC) A module capable of providing an asynchronous interrupt to the device takes the device out of STOP mode and returns the device to normal RUN mode. Refer to the device's Power Management chapter for peripheral, I/O, and memory operation in STOP mode. When an interrupt request occurs, the CPU exits STOP mode and resumes processing, beginning with the stacking operations leading to the interrupt service routine.
Page 206 Functional description Before entering LLS mode, the user should configure the low-leakage wakeup (LLWU) module to enable the desired wakeup sources. The available wakeup sources in LLS are detailed in the chip configuration details for this device. After wakeup from LLS, the device returns to normal RUN mode with a pending LLWU module interrupt.
Page 207: Debug In Low Power Modes
Chapter 13 System Mode Controller (SMC) When entering VLLS, each I/O pin is latched as configured before executing VLLS. Because all digital logic in the MCU is powered off, all port and peripheral data is lost during VLLS. This information must be restored before the ACKISO bit in the PMC is set.
Page 208 Functional description The MDM AP Control Register also includes a Very Low Leakage Debug Acknowledge (VLLDBGACK) bit that is set to release the ARM core being held in reset following a VLLS recovery. The debugger reinitializes all debug IP, and then asserts the VLLDBGACK control bit to allow the RCM to release the ARM core from reset and allow CPU operation to begin.
Page 209: Introduction
Chapter 14 Power Management Controller (PMC) 14.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The power management controller (PMC) contains the internal voltage regulator, power on reset (POR), and low voltage detect system. 14.2 Features The PMC features include: •...
Page 210: Lvd Reset Operation
Low-voltage detect (LVD) system • The low voltage detect flag (LVDF) operates in a level sensitive manner. The LVDF bit is set when the supply voltage falls below the selected trip point (VLVD). The LVDF bit is cleared by writing one to the LVDACK bit, but only if the internal supply has returned above the trip point;...
Page 211: Kl04 Sub-Family Reference Manual, Rev. 3.1, November
Chapter 14 Power Management Controller (PMC) 14.4 I/O retention When in LLS mode, the I/O pins are held in their input or output state. Upon wakeup, the PMC is re-enabled, goes through a power up sequence to full regulation, and releases the logic from state retention mode.
Page 212: Low Voltage Detect Status And Control 1 Register (Pmc_Lvdsc1)
Memory map and register descriptions 14.5.1 Low Voltage Detect Status And Control 1 register (PMC_LVDSC1) This register contains status and control bits to support the low voltage detect function. This register should be written during the reset initialization program to set the desired controls even if the desired settings are the same as the reset settings.
Page 213: Low Voltage Detect Status And Control 2 Register (Pmc_Lvdsc2)
Chapter 14 Power Management Controller (PMC) PMC_LVDSC1 field descriptions (continued) Field Description Low-Voltage Detect Reset Enable LVDRE This write-once bit enables LVDF events to generate a hardware reset. Additional writes are ignored. LVDF does not generate hardware resets Force an MCU reset when LVDF = 1 3–2 This field is reserved.
Page 214: Regulator Status And Control Register (Pmc_Regsc)
Memory map and register descriptions PMC_LVDSC2 field descriptions Field Description Low-Voltage Warning Flag LVWF This read-only status bit indicates a low-voltage warning event. LVWF is set when V transitions below Supply the trip point, or after reset and V is already below V .
Page 215 Chapter 14 Power Management Controller (PMC) Address: 4007_D000h base + 2h offset = 4007_D002h Read ACKISO REGONS Reserved BGEN Reserved BGBE Write Reset PMC_REGSC field descriptions Field Description 7–6 This field is reserved. Reserved This read-only field is reserved and always has the value 0. This field is reserved.
Page 216 Memory map and register descriptions KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc.
Page 217: Introduction
Chapter 15 Low-Leakage Wakeup Unit (LLWU) 15.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The LLWU module allows the user to select up to 16 external pin sources and up to 8 internal modules as a wakeup source from low-leakage power modes.
Page 218: Modes Of Operation
Introduction 15.1.2 Modes of operation The LLWU module becomes functional on entry into a low-leakage power mode. After recovery from LLS, the LLWU is immediately disabled. After recovery from VLLS, the LLWU continues to detect wakeup events until the user has acknowledged the wakeup via a write to the PMC_REGSC[ACKISO] bit.
Page 219: Block Diagram
Chapter 15 Low-Leakage Wakeup Unit (LLWU) 15.1.2.4 Debug mode When the chip is in Debug mode and then enters LLS or a VLLSx mode, no debug logic works in the fully-functional low-leakage mode. Upon an exit from the LLS or VLLSx mode, the LLWU becomes inactive.
Page 220: Llwu Signal Descriptions
LLWU signal descriptions 15.2 LLWU signal descriptions The signal properties of LLWU are shown in the following table. The external wakeup input pins can be enabled to detect either rising-edge, falling-edge, or on any change. Table 15-1. LLWU signal descriptions Signal Description LLWU_Pn...
Page 221: Llwu Pin Enable 1 Register (Llwu_Pe1)
Chapter 15 Low-Leakage Wakeup Unit (LLWU) LLWU memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4007_C000 LLWU Pin Enable 1 register (LLWU_PE1) 15.3.1/221 4007_C001 LLWU Pin Enable 2 register (LLWU_PE2) 15.3.2/222 4007_C002 LLWU Module Enable register (LLWU_ME) 15.3.3/223 4007_C003 LLWU Flag 1 register (LLWU_F1) 15.3.4/225...
Page 222: Llwu Pin Enable 2 Register (Llwu_Pe2)
Memory map/register definition LLWU_PE1 field descriptions (continued) Field Description External input pin enabled with falling edge detection External input pin enabled with any change detection 3–2 Wakeup Pin Enable For LLWU_P1 WUPE1 Enables and configures the edge detection for the wakeup pin. External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection...
Page 223: Llwu Module Enable Register (Llwu_Me)
Chapter 15 Low-Leakage Wakeup Unit (LLWU) LLWU_PE2 field descriptions (continued) Field Description External input pin enabled with falling edge detection External input pin enabled with any change detection 5–4 Wakeup Pin Enable For LLWU_P6 WUPE6 Enables and configures the edge detection for the wakeup pin. External input pin disabled as wakeup input External input pin enabled with rising edge detection External input pin enabled with falling edge detection...
Page 224 Memory map/register definition LLWU_ME field descriptions Field Description Wakeup Module Enable For Module 7 WUME7 Enables an internal module as a wakeup source input. Internal module flag not used as wakeup source Internal module flag used as wakeup source Wakeup Module Enable For Module 6 WUME6 Enables an internal module as a wakeup source input.
Page 225: Llwu Flag 1 Register (Llwu_F1)
Chapter 15 Low-Leakage Wakeup Unit (LLWU) 15.3.4 LLWU Flag 1 register (LLWU_F1) LLWU_F1 contains the wakeup flags indicating which wakeup source caused the MCU to exit LLS or VLLS mode. For LLS, this is the source causing the CPU interrupt flow. For VLLS, this is the source causing the MCU reset flow.
Page 226: Llwu Flag 3 Register (Llwu_F3)
Memory map/register definition LLWU_F1 field descriptions (continued) Field Description Wakeup Flag For LLWU_P4 WUF4 Indicates that an enabled external wakeup pin was a source of exiting a low-leakage power mode. To clear the flag write a one to WUF4. LLWU_P4 input was not a wakeup source LLWU_P4 input was a wakeup source Wakeup Flag For LLWU_P3 WUF3...
Page 227 Chapter 15 Low-Leakage Wakeup Unit (LLWU) NOTE This register is reset on Chip Reset not VLLS and by reset types that trigger Chip Reset not VLLS. It is unaffected by reset types that do not trigger Chip Reset not VLLS. See the Introduction details for more information.
Page 228: Llwu Pin Filter 1 Register (Llwu_Filt1)
Memory map/register definition LLWU_F3 field descriptions (continued) Field Description Indicates that an enabled internal peripheral was a source of exiting a low-leakage power mode. To clear the flag, follow the internal peripheral flag clearing mechanism. Module 2 input was not a wakeup source Module 2 input was a wakeup source Wakeup flag For module 1 MWUF1...
Page 229: Llwu Pin Filter 2 Register (Llwu_Filt2)
Chapter 15 Low-Leakage Wakeup Unit (LLWU) LLWU_FILT1 field descriptions (continued) Field Description Pin Filter 1 was not a wakeup source Pin Filter 1 was a wakeup source 6–5 Digital Filter On External Pin FILTE Controls the digital filter options for the external pin detect. Filter disabled Filter posedge detect enabled Filter negedge detect enabled...
Page 230: Functional Description
Functional description LLWU_FILT2 field descriptions (continued) Field Description Pin Filter 2 was not a wakeup source Pin Filter 2 was a wakeup source 6–5 Digital Filter On External Pin FILTE Controls the digital filter options for the external pin detect. Filter disabled Filter posedge detect enabled Filter negedge detect enabled...
Page 231: Lls Mode
Chapter 15 Low-Leakage Wakeup Unit (LLWU) For internal module wakeup operation, the WUMEx bit enables the associated module as a wakeup source. 15.4.1 LLS mode Wakeup events triggered from either an external pin input or an internal module input result in a CPU interrupt flow to begin user code execution. 15.4.2 VLLS modes In the case of a wakeup due to external pin or internal module wakeup, recovery is always via a reset flow and the RCM_SRS[WAKEUP] is set indicating the low-leakage...
Page 232 Functional description KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc.
Page 233: Introduction
Chapter 16 Reset Control Module (RCM) 16.1 Introduction This chapter describes the registers of the Reset Control Module (RCM). The RCM implements many of the reset functions for the chip. See the chip's reset chapter for more information. 16.2 Reset memory map and register descriptions The Reset Control Module (RCM) registers provide reset status information and reset filter control.
Page 234: Kl04 Sub-Family Reference Manual, Rev. 3.1, November
Reset memory map and register descriptions NOTE The reset value of this register depends on the reset source: • POR (including LVD) — 0x82 • LVD (without POR) — 0x02 • VLLS mode wakeup due to RESET pin assertion — 0x41 •...
Page 235: System Reset Status Register 1 (Rcm_Srs1)
Chapter 16 Reset Control Module (RCM) RCM_SRS0 field descriptions (continued) Field Description Low-Voltage Detect Reset If the LVDRE bit is set and the supply drops below the LVD trip voltage, an LVD reset occurs. This bit is also set by POR. Reset not caused by LVD trip or POR Reset caused by LVD trip or POR Low Leakage Wakeup Reset...
Page 236: Reset Pin Filter Control Register (Rcm_Rpfc)
Reset memory map and register descriptions RCM_SRS1 field descriptions (continued) Field Description Stop Mode Acknowledge Error Reset SACKERR Indicates that after an attempt to enter Stop mode, a reset has been caused by a failure of one or more peripherals to acknowledge within approximately one second to enter stop mode. Reset not caused by peripheral failure to acknowledge attempt to enter stop mode Reset caused by peripheral failure to acknowledge attempt to enter stop mode This field is reserved.
Page 237: Reset Pin Filter Width Register (Rcm_Rpfw)
Chapter 16 Reset Control Module (RCM) RCM_RPFC field descriptions Field Description 7–3 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Reset Pin Filter Select in Stop Mode RSTFLTSS Selects how the reset pin filter is enabled in Stop and VLPS modes , and also during LLS and VLLS modes.
Page 238 Reset memory map and register descriptions RCM_RPFW field descriptions (continued) Field Description 00101 Bus clock filter count is 6 00110 Bus clock filter count is 7 00111 Bus clock filter count is 8 01000 Bus clock filter count is 9 01001 Bus clock filter count is 10 01010...
Page 239: Introduction
Chapter 17 Bit Manipulation Engine (BME) 17.1 Introduction The Bit Manipulation Engine (BME) provides hardware support for atomic read-modify- write memory operations to the peripheral address space in Cortex-M0+ based microcontrollers. This architectural capability is also known as "decorated storage" as it defines a mechanism for providing additional semantics for load and store operations to memory-mapped peripherals beyond just the reading and writing of data values to the addressed memory locations.
Page 240: Overview
Introduction 17.1.1 Overview The following figure is a generic block diagram of the processor core and platform for this class of ultra low-end microcontrollers. Cortex-M0+ Core CM0+ Core Platform Fetch NVIC SHFT LD/ST IO Port MTB Port AHB Bus PRAM Array RGPIO AXBS...
Page 241: Modes Of Operation
Chapter 17 Bit Manipulation Engine (BME) • Resides between a crossbar switch slave port and a peripheral bridge bus controller • 2-stage pipeline design matching the AHB system bus protocol • Combinationally passes non-decorated accesses to peripheral bridge bus controller •...
Page 242: Memory Map And Register Definition
Memory Map and Register Definition 17.3 Memory Map and Register Definition The BME module provides a memory-mapped capability and does not include any programming model registers. The exact set of functions supported by the BME are detailed in the Functional Description.
Page 243 Chapter 17 Bit Manipulation Engine (BME) CYCLE RULER hclk BME AHB Input Bus next 5..v_wxyz mx_haddr next mx_hattr next mx_hwrite wdata mx_hwdata mx_hrdata mx_hready BME AHB Output Bus next 400v_wxyz 400v_wxyz sx_haddr next sx_hattr next sx_hwrite wdata bfi rdata sx_hwdata rdata sx_hrdata sx_hready...
Page 244 Functional Description NOTE Any wait states inserted by the peripheral slave device (sx_hready = 0) are simply passed through the BME back to the master input bus, stalling the AHB transaction cycle for cycle. 17.4.1.1 Decorated Store Logical AND (AND) This command performs an atomic read-modify-write of the referenced memory location.
Page 245 Chapter 17 Bit Manipulation Engine (BME) Table 17-1. Cycle definitions of decorated store: logical AND Pipeline Stage Cycle BME AHB_ap Forward addr to memory; Recirculate captured addr + <next> Decode decoration; Convert attr to memory as slave_wt master_wt to slave_rd; Capture address, attributes BME AHB_dp <previous>...
Page 246 Functional Description Table 17-2. Cycle definitions of decorated store: logical OR Pipeline Stage Cycle BME AHB_ap Forward addr to memory; Recirculate captured addr + <next> Decode decoration; Convert attr to memory as slave_wt master_wt to slave_rd; Capture address, attributes BME AHB_dp <previous>...
Page 247 Chapter 17 Bit Manipulation Engine (BME) Table 17-3. Cycle definitions of decorated store: logical XOR Pipeline Stage Cycle BME AHB_ap Forward addr to memory; Recirculate captured addr + <next> Decode decoration; Convert attr to memory as slave_wt master_wt to slave_rd; Capture address, attributes BME AHB_dp <previous>...
Page 248 Functional Description & ~mask // modify wdata & mask mem[accessAddress & 0xE007FFFF, size] = tmp // memory write The write data operand (wdata) associated with the store instruction contains the bit field to be inserted. It must be properly aligned within a right-justified container, that is, within the lower 8 bits for a byte operation, the lower 16 bits for a halfword or the entire 32 bits for a word operation.
Page 249 Chapter 17 Bit Manipulation Engine (BME) 17.4.2 BME Decorated Loads The functions supported by the BME's decorated loads include two single-bit load-and- {set, clear} operators plus unsigned bit field extracts. For the two load-and-{set, clear} operations, BME converts a single decorated AHB load transaction into a 2-cycle atomic read-modify-write sequence, where the combined read-modify operations are performed in the first AHB data phase, and then the write is performed in the second AHB data phase as the original read data is returned to the processor core.
Page 250 Functional Description • Cycle x, 1st AHB address phase: Read from input bus is translated into a read operation on the output bus with the actual memory address (with the decoration removed) and then captured in a register • Cycle x+1, 2nd AHB address phase: Write access with the registered (but actual) memory address is output •...
Page 251 Chapter 17 Bit Manipulation Engine (BME) CYCLE RULER hclk BME AHB Input Bus 5..v_wxyz next mx_haddr next mx_hattr next mx_hwrite mx_hwdata ubfx mx_hrdata mx_hready BME AHB Output Bus 400v_wxyz next sx_haddr next sx_hattr next sx_hwrite sx_hwdata rdata sx_hrdata sx_hready BME States + Datapath control_state_dp1 control_state_dp2 5..v_wxyz...
Page 252 Functional Description 17.4.2.1 Decorated Load Load-and-Clear 1 Bit (LAC1) This command loads a 1-bit field defined by the LSB position (b) into the core's general purpose destination register (Rt) and zeroes the bit in the memory space after performing an atomic read-modify-write sequence. The extracted one bit data field from the memory address is right justified and zero filled in the operand returned to the core.
Page 253 Chapter 17 Bit Manipulation Engine (BME) 17.4.2.2 Decorated Load: Load-and-Set 1 Bit (LAS1) This command loads a 1-bit field defined by the LSB position (b) into the core's general purpose destination register (Rt) and sets the bit in the memory space after performing an atomic read-modify-write sequence.
Page 254 Functional Description 17.4.2.3 Decorated Load Unsigned Bit Field Extract (UBFX) This command extracts a bit field defined by LSB position (b) and the bit field width (w +1) from the memory "container" defined by the access size associated with the load instruction using a 2-cycle read sequence.
Page 255: Additional Details On Decorated Addresses And Gpio Accesses
Chapter 17 Bit Manipulation Engine (BME) Table 17-7. Cycle definitions of decorated load: unsigned bit field extract Pipeline Stage Cycle BME AHB_ap Forward addr to memory; Idle AHB address phase <next> Decode decoration; Capture address, attributes BME AHB_dp <previous> Perform memory read; Form Logically right shift registered bit mask;...
Page 256: Application Information
Application Information Table 17-8. Decorated peripheral and GPIO address details (continued) Peripheral address space Description 0x4400_0000 - 0x4FFF_FFFF Decorated AND, OR, XOR, LAC1, LAS1 references to peripherals and GPIO based at either 0x4000_F000 or 0x400F_F000 0x5000_0000 - 0x5FFF_FFFF Decorated BFI, UBFX references to peripherals and GPIO only based at 0x4000_F000 17.5 Application Information In this section, GNU assembler macros with C expression operands are presented as examples of the required instructions to perform decorated operations.
Page 257 Chapter 17 Bit Manipulation Engine (BME) :: [addr] "r" (ADDR), [wdata] "r" (WDATA) : "r2", "r3"); #define IOXORW(ADDR,WDATA) __asm("ldr r3, =(3<<26);" "orr r3, %[addr];" "mov r2, %[wdata];" "str r2, [r3];" :: [addr] "r" (ADDR), [wdata] "r" (WDATA) : "r2", "r3"); #define IOXORH(ADDR,WDATA) __asm("ldr r3, =(3<<26);"...
Page 258 Application Information KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc.
Page 259: Introduction
Chapter 18 Miscellaneous Control Module (MCM) 18.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The Miscellaneous Control Module (MCM) provides a myriad of miscellaneous control functions. 18.1.1 Features The MCM includes the following features: •...
Page 260: Crossbar Switch (Axbs) Slave Configuration (Mcm_Plasc)
Memory map/register descriptions MCM memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) Crossbar Switch (AXBS) Master Configuration F000_300A 0005h 18.2.2/261 (MCM_PLAMC) F000_300C Platform Control Register (MCM_PLACR) 0000_0000h 18.2.3/261 F000_3040 Compute Operation Control Register (MCM_CPO) 0000_0000h 18.2.4/264 18.2.1 Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC)
Page 261: Crossbar Switch (Axbs) Master Configuration (Mcm_Plamc)
Chapter 18 Miscellaneous Control Module (MCM) 18.2.2 Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC) PLAMC is a 16-bit read-only register identifying the presence/absence of bus master connections to the device's crossbar switch. Address: F000_3000h base + Ah offset = F000_300Ah Read Write Reset MCM_PLAMC field descriptions...
Page 262 Memory map/register descriptions The cache in flash controller is enabled and caching both instruction and data type fetches after reset. It is possible to have these states for the cache: DFCC DFCIC DFCDA Description Cache is on for both instruction and data. Cache is on for instruction and off for data.
Page 263 Chapter 18 Miscellaneous Control Module (MCM) MCM_PLACR field descriptions (continued) Field Description Disable Flash Controller Speculation DFCS This field is used to disable flash controller speculation. Enable flash controller speculation. Disable flash controller speculation. Enable Flash Data Speculation EFDS This field is used to enable flash data speculation. Disable flash data speculation.
Page 264: Compute Operation Control Register (Mcm_Cpo)
Memory map/register descriptions 18.2.4 Compute Operation Control Register (MCM_CPO) This register controls the Compute Operation. Address: F000_3000h base + 40h offset = F000_3040h Reset Reset MCM_CPO field descriptions Field Description 31–3 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Compute Operation wakeup on interrupt CPOWOI No effect.
Page 265 Chapter 18 Miscellaneous Control Module (MCM) MCM_CPO field descriptions (continued) Field Description Request is cleared. Request Compute Operation. KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc.
Page 266 Memory map/register descriptions KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc.
Page 267: Introduction
Chapter 19 Micro Trace Buffer (MTB) 19.1 Introduction Microcontrollers using the Cortex-M0+ processor core include support for a CoreSight Micro Trace Buffer to provide program trace capabilities. The proper name for this function is the CoreSight Micro Trace Buffer for the Cortex-M0+ Processor; in this document, it is simply abbreviated as the MTB.
Page 268 Introduction Cortex-M0+ Core CM0+ Core Platform Fetch NVIC SHFT LD/ST IO Port AHB Bus MTB Port PRAM Array RGPIO Slave Peripherals Alt-Master PBRIDGE DMA_4ch AXBS Array Figure 19-1. Generic Cortex-M0+ core platform block diagram As shown in the block diagram, the platform RAM (PRAM) controller connects to two input buses: •...
Page 269 Chapter 19 Micro Trace Buffer (MTB) The following figure shows how the execution trace information is stored in memory as a sequence of packets. Nth destination address Odd word address Nth source address Even word address Incrementing SRAM memory address Start bit 2nd destination address 2nd source address...
Page 270: Features
Introduction • Destination address field set to bits[31:1] of the EXC_RETURN value. See the ARM v6-M Architecture Reference Manual. • The A-bit set to 0. • The second packet has the: • Source address field set to bits[31:1] of the EXC_RETURN value. •...
Page 271: Kl04 Sub-Family Reference Manual, Rev. 3.1, November
Chapter 19 Micro Trace Buffer (MTB) • Two DWT comparators (addresses or address + data) provide programmable start/ stop recording • CoreSight compliant debug functionality 19.1.3 Modes of Operation The MTB_RAM and MTB_DWT functions do not support any special modes of operation.
Page 272: Memory Map And Register Definition
Memory Map and Register Definition In addition, there are two signals formed by the MTB_DWT module and driven to the MTB_RAM controller: TSTART (trace start) and TSTOP (trace stop). These signals can be configured using the trace watchpoints to define programmable addresses and data values to affect the program trace recording state.
Page 273 Chapter 19 Micro Trace Buffer (MTB) MTB memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) F000_0FB4 Lock Status Register (MTB_LOCKSTAT) 0000_0000h 19.31.9/281 19.31.10/ F000_0FB8 Authentication Status Register (MTB_AUTHSTAT) 0000_0000h 19.31.11/ F000_0FBC Device Architecture Register (MTB_DEVICEARCH) 4770_0A31h 19.31.12/ F000_0FC8 Device Configuration Register (MTB_DEVICECFG)
Page 274 Memory Map and Register Definition For the standard configuration where the size of the MTB is ≤ 25% of the total RAM capacity, it is recommended the MTB be based at the address defined by the MTB_BASE register. The read-only MTB_BASE register is defined by the expression (0x2000_0000 - (RAM_Size/4)).
Page 275 Chapter 19 Micro Trace Buffer (MTB) MTB_POSITION field descriptions (continued) Field Description A debug agent can calculate the system memory map address for the current location in the MTB using the following "generic" equation: Given mtb_size = 1 << (MTB_MASTER[MASK] + 4), systemAddress = MTB_BASE + (((MTB_POSITION &...
Page 276 Memory Map and Register Definition Address: F000_0000h base + 4h offset = F000_0004h Reset MASK Reset * Notes: • x = Undefined at reset. MTB_MASTER field descriptions Field Description Main trace enable bit When this bit is 1, trace data is written into the RAM memory location addressed by MTB_POSITION[POINTER].
Page 277 Chapter 19 Micro Trace Buffer (MTB) MTB_MASTER field descriptions (continued) Field Description permitted; user write accesses are ignored. The HPROT[1] signal determines if an access is user or privileged. Note MTB_RAM SFR read access are not controlled by this bit and are always permitted. Trace stop input enable TSTOPEN If this bit is 1 and the TSTOP signal is HIGH, then the EN bit is set to 0.
Page 278 Memory Map and Register Definition Address: F000_0000h base + 8h offset = F000_0008h WATERMARK Reset WATERMARK Reset * Notes: • x = Undefined at reset. MTB_FLOW field descriptions Field Description 31–3 WATERMARK[28:0] WATERMARK This field contains an address in the same format as the MTB_POSITION[POINTER] field. When the MTB_POSITION[POINTER] matches the WATERMARK field value, actions defined by the AUTOHALT and AUTOSTOP bits are performed.
Page 279 Chapter 19 Micro Trace Buffer (MTB) 19.31.4 MTB Base Register (MTB_BASE) The read-only MTB_BASE Register indicates where the RAM is located in the system memory map. This register is provided to enable auto discovery of the MTB RAM location, by a debug agent and is defined by a hardware design parameter. For this device, the base address is defined by the expression: MTB_BASE[BASEADDR] = 0x2000_0000 - (RAM_Size/4) Address: F000_0000h base + Ch offset = F000_000Ch...
Page 280 Memory Map and Register Definition 19.31.6 Claim TAG Set Register (MTB_TAGSET) The Claim Tag Set Register returns the number of bits that can be set on a read, and enables individual bits to be set on a write. It is hardwired to specific values used during the auto-discovery process by an external debug agent.
Page 281 Chapter 19 Micro Trace Buffer (MTB) 19.31.8 Lock Access Register (MTB_LOCKACCESS) The Lock Access Register enables a write access to component registers. It is hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_0000h base + FB0h offset = F000_0FB0h LOCKACCESS Reset MTB_LOCKACCESS field descriptions...
Page 282 Memory Map and Register Definition 19.31.10 Authentication Status Register (MTB_AUTHSTAT) The Authentication Status Register reports the required security level and current status of the security enable bit pairs. Where functionality changes on a given security level, this change must be reported in this register. It is connected to specific signals used during the auto-discovery process by an external debug agent.
Page 283 Chapter 19 Micro Trace Buffer (MTB) 19.31.11 Device Architecture Register (MTB_DEVICEARCH) This register indicates the device architecture. It is hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_0000h base + FBCh offset = F000_0FBCh DEVICEARCH Reset MTB_DEVICEARCH field descriptions...
Page 284 Memory Map and Register Definition 19.31.13 Device Type Identifier Register (MTB_DEVICETYPID) This register indicates the device type ID. It is hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_0000h base + FCCh offset = F000_0FCCh DEVICETYPID Reset MTB_DEVICETYPID field descriptions...
Page 285: Mtb_Dwt Memory Map
Chapter 19 Micro Trace Buffer (MTB) 19.31.15 Component ID Register (MTB_COMPIDn) These registers indicate the component IDs. They are hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_0000h base + FF0h offset + (4d × i), where i=0d to 3d COMPID x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* Reset...
Page 286 Memory Map and Register Definition MTBDWT memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) F000_1FCC Device Type Identifier Register (MTBDWT_DEVICETYPID) 0000_0004h 19.32.8/294 F000_1FD0 Peripheral ID Register (MTBDWT_PERIPHID4) See section 19.32.9/295 F000_1FD4 Peripheral ID Register (MTBDWT_PERIPHID5) See section 19.32.9/295 F000_1FD8 Peripheral ID Register (MTBDWT_PERIPHID6)
Page 287 Chapter 19 Micro Trace Buffer (MTB) MTBDWT_CTRL field descriptions (continued) Field Description MTBDWT_CTRL[26] = NOEXTTRIG = 1, external match signals are not supported MTBDWT_CTRL[25] = NOCYCCNT = 1, cycle counter is not supported MTBDWT_CTRL[24] = NOPRFCNT = 1, profiling counters are not supported MTBDWT_CTRL[22] = CYCEBTENA = 0, no POSTCNT underflow packets generated MTBDWT_CTRL[21] = FOLDEVTENA = 0, no folded instruction counter overflow events MTBDWT_CTRL[20] = LSUEVTENA = 0, no LSU counter overflow events...
Page 288 Memory Map and Register Definition 19.32.3 MTB_DWT Comparator Mask Register (MTBDWT_MASKn) The MTBDWT_MASKn registers define the size of the ignore mask applied to the reference address for address range matching by comparator n. Note the format of this mask field is different than the MTB_MASTER[MASK]. Address: F000_1000h base + 24h offset + (16d ×...
Page 289 Chapter 19 Micro Trace Buffer (MTB) 19.32.4 MTB_DWT Comparator Function Register 0 (MTBDWT_FCT0) The MTBDWT_FCTn registers control the operation of comparator n. Address: F000_1000h base + 28h offset = F000_1028h Reset DATAVADDR0 DATAVSIZE FUNCTION Reset MTBDWT_FCT0 field descriptions Field Description 31–25 This field is reserved.
Page 290 Memory Map and Register Definition MTBDWT_FCT0 field descriptions (continued) Field Description No match. Match occurred. 23–20 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 19–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 15–12 Data Value Address 0 DATAVADDR0...
Page 291 Chapter 19 Micro Trace Buffer (MTB) 19.32.5 MTB_DWT Comparator Function Register 1 (MTBDWT_FCT1) The MTBDWT_FCTn registers control the operation of comparator n. Since the MTB_DWT only supports data value comparisons on comparator 0, there are several fields in the MTBDWT_FCT1 register that are RAZ/WI (bits 12, 11:10, 8). Address: F000_1000h base + 38h offset = F000_1038h Reset FUNCTION...
Page 292 Memory Map and Register Definition MTBDWT_FCT1 field descriptions (continued) Field Description No match. Match occurred. 23–4 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 3–0 Function FUNCTION Selects the action taken on a comparator match. If MTBDWT_COMP0 is used for a data value and MTBDWT_COMP1 for an address value, then MTBDWT_FCT1[FUNCTION] must be set to zero.
Page 293 Chapter 19 Micro Trace Buffer (MTB) Reset MTBDWT_TBCTRL field descriptions Field Description 31–28 Number of Comparators NUMCOMP This read-only field specifies the number of comparators in the MTB_DWT. This implementation includes two registers. 27–2 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Action based on Comparator 1 match ACOMP1 When the MTBDWT_FCT1[MATCHED] is set, it indicates MTBDWT_COMP1 address compare has...
Page 294 Memory Map and Register Definition 19.32.7 Device Configuration Register (MTBDWT_DEVICECFG) This register indicates the device configuration. It is hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_1000h base + FC8h offset = F000_1FC8h DEVICECFG Reset MTBDWT_DEVICECFG field descriptions...
Page 295 Chapter 19 Micro Trace Buffer (MTB) 19.32.9 Peripheral ID Register (MTBDWT_PERIPHIDn) These registers indicate the peripheral IDs. They are hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_1000h base + FD0h offset + (4d × i), where i=0d to 7d PERIPHID x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* Reset...
Page 296 Memory Map and Register Definition 19.3.3 System ROM Memory Map The System ROM Table registers are also mapped into a sparsely-populated 4 KB address space. For core configurations like that supported by Cortex-M0+, ARM recommends that a debugger identifies and connects to the debug components using the CoreSight debug infrastructure.
Page 297 Chapter 19 Micro Trace Buffer (MTB) ROM memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) F000_2FDC Peripheral ID Register (ROM_PERIPHID7) See section 19.33.4/299 F000_2FE0 Peripheral ID Register (ROM_PERIPHID0) See section 19.33.4/299 F000_2FE4 Peripheral ID Register (ROM_PERIPHID1) See section 19.33.4/299 F000_2FE8 Peripheral ID Register (ROM_PERIPHID2)
Page 298 Memory Map and Register Definition 19.33.2 End of Table Marker Register (ROM_TABLEMARK) This register indicates end of table marker. It is hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_2000h base + Ch offset = F000_200Ch MARK Reset ROM_TABLEMARK field descriptions...
Page 299 Chapter 19 Micro Trace Buffer (MTB) 19.33.4 Peripheral ID Register (ROM_PERIPHIDn) These registers indicate the peripheral IDs. They are hardwired to specific values used during the auto-discovery process by an external debug agent. Address: F000_2000h base + FD0h offset + (4d × i), where i=0d to 7d PERIPHID x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* Reset...
Page 300 Memory Map and Register Definition KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc.
Page 301: Introduction
Chapter 20 Crossbar Switch Lite (AXBS-Lite) 20.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. This chapter provides information on the layout, configuration, and programming of the crossbar switch. The crossbar switch connects bus masters and bus slaves using a crossbar switch structure.
Page 302: Functional Description
Functional Description 20.3 Functional Description 20.3.1 General operation When a master accesses the crossbar switch the access is immediately taken. If the targeted slave port of the access is available, then the access is immediately presented on the slave port. Single-clock or zero-wait-state accesses are possible through the crossbar. If the targeted slave port of the access is busy or parked on a different master port, the requesting master simply sees wait states inserted until the targeted slave port can service the master's request.
Page 303: Arbitration
Chapter 20 Crossbar Switch Lite (AXBS-Lite) 20.3.2 Arbitration The crossbar switch supports two arbitration algorithms: • Fixed priority • Round robin The selection of the global slave port arbitration is controlled by MCM_PLACR[ARB]. For fixed priority, set ARB to 0. For round robin, set ARB to 1. This arbitration setting applies to all slave ports.
Page 304: Initialization/Application Information
Initialization/application information Table 20-1. How AXBS grants control of a slave port to a master When Then AXBS grants control to the requesting master Both of the following are true: At the next clock edge • The current master is not running a transfer. •...
Page 305: Introduction
Chapter 21 Peripheral Bridge (AIPS-Lite) 21.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The peripheral bridge converts the crossbar switch interface to an interface that can access most of the slave peripherals on this chip. The peripheral bridge supports up to 128 peripherals, each with a 4K-byte address space.
Page 306: General Operation
Functional description 21.1.2 General operation The slave devices connected to the peripheral bridge are modules which contain a programming model of control and status registers. The system masters read and write these registers through the peripheral bridge. The peripheral bridge performs a bus protocol conversion of the master transactions and generates the following as inputs to the peripherals: •...
Page 307: Introduction
Chapter 22 Direct Memory Access Multiplexer (DMAMUX) 22.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. 22.1.1 Overview The direct memory access multiplexer (DMAMUX) routes DMA sources, called slots, to any of the 4 DMA channels. This process is illustrated in the following figure. KL04 Sub-Family Reference Manual, Rev.
Page 308: Features
Introduction DMA channel #0 DMAMUX Source #1 DMA channel #1 Source #2 Source #3 Source #x Always #1 Always #y Trigger #1 DMA channel #n Trigger #z Figure 22-1. DMAMUX block diagram 22.1.2 Features The DMAMUX module provides these features: •...
Page 309: External Signal Description
Chapter 22 Direct Memory Access Multiplexer (DMAMUX) In this mode, the DMA channel is disabled. Because disabling and enabling of DMA channels is done primarily via the DMA configuration registers, this mode is used mainly as the reset state for a DMA channel in the DMA channel MUX. It may also be used to temporarily suspend a DMA channel while reconfiguration of the system takes place, for example, changing the period of a DMA trigger.
Page 310: Kl04 Sub-Family Reference Manual, Rev. 3.1, November
Functional description NOTE Setting multiple CHCFG registers with the same Source value will result in unpredictable behavior. NOTE Before changing the trigger or source settings a DMA channel must be disabled via the CHCFGn[ENBL] bit. Address: 4002_1000h base + 0h offset + (1d × i), where i=0d to 3d Read ENBL TRIG...
Page 311: Dma Channels With Periodic Triggering Capability
Chapter 22 Direct Memory Access Multiplexer (DMAMUX) • Channels which implement the normal routing functionality plus periodic triggering capability • Channels which implement only the normal routing functionality 22.4.1 DMA channels with periodic triggering capability Besides the normal routing functionality, the first 2 channels of the DMAMUX provide a special periodic triggering capability that can be used to provide an automatic mechanism to transmit bytes, frames, or packets at fixed intervals without the need for processor intervention.
Page 312: Freescale Semiconductor, Inc
Functional description The DMA channel triggering capability allows the system to schedule regular DMA transfers, usually on the transmit side of certain peripherals, without the intervention of the processor. This trigger works by gating the request from the peripheral to the DMA until a trigger event has been seen.
Page 313: Dma Channels With No Triggering Capability
Chapter 22 Direct Memory Access Multiplexer (DMAMUX) By configuring the DMA to transfer data to one or more GPIO ports, it is possible to create complex waveforms using tabular data stored in on-chip memory. Conversely, using the DMA to periodically transfer data from one or more GPIO ports, it is possible to sample complex waveforms and store the results in tabular form in on- chip memory.
Page 314: Initialization/Application Information
Initialization/application information By configuring the DMA to transfer all of the data in a single minor loop (that is, major loop counter = 1), no reactivation of the channel is necessary. The disadvantage to this option is the reduced granularity in determining the load that the DMA transfer will impose on the system.
Page 315: Freescale Semiconductor, Inc
Chapter 22 Direct Memory Access Multiplexer (DMAMUX) 3. Ensure that the DMA channel is properly configured in the DMA. The DMA channel may be enabled at this point. 4. Configure the corresponding timer. 5. Select the source to be routed to the DMA channel. Write to the corresponding CHCFG register, ensuring that the CHCFG[ENBL] and CHCFG[TRIG] fields are set.
Page 316: Freescale Semiconductor, Inc
Initialization/application information 3. Ensure that the DMA channel is properly configured in the DMA. The DMA channel may be enabled at this point. 4. Select the source to be routed to the DMA channel. Write to the corresponding CHCFG register, ensuring that CHCFG[ENBL] is set while CHCFG[TRIG] is cleared.
Page 317: Freescale Semiconductor, Inc
Chapter 22 Direct Memory Access Multiplexer (DMAMUX) 1. Disable the DMA channel in the DMA and re-configure the channel for the new source. 2. Clear the CHCFG[ENBL] and CHCFG[TRIG] bits of the DMA channel. 3. Select the source to be routed to the DMA channel. Write to the corresponding CHCFG register, ensuring that the CHCFG[ENBL] and CHCFG[TRIG] fields are set.
Page 318: Freescale Semiconductor, Inc
Initialization/application information KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc.
Page 319: Introduction
Chapter 23 DMA Controller Module 23.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. This chapter describes the direct memory access (DMA) controller module. It provides an overview of the module and describes in detail its signals and programming model. The latter sections of this chapter describe operations, features, and supported data transfer modes in detail.
Page 320: Features
Introduction The following figure is a simplified block diagram of the 4-channel DMA controller. DREQ0 DREQ1 DREQ2 DREQ3 DACK0 DACK1 DACK2 DACK3 Channel 0 Channel 1 Channel 2 Channel 3 SAR0 SAR1 SAR2 SAR3 Slave Interrupts DAR0 DAR1 DAR2 DAR3 Peripheral Bus DSR0 DSR1...
Page 321: Dma Transfer Overview
Chapter 23 DMA Controller Module • Continuous-mode or cycle-steal transfers from software or peripheral initiation • Automatic hardware acknowledge/done indicator from each channel • Independent source and destination address registers • Optional modulo addressing and automatic updates of source and destination addresses •...
Page 322: Memory Map And Registers
Memory Map and Registers Control and Data Memory/ Peripheral Read Write Memory/ Peripheral Control and Data Figure 23-2. Dual-Address Transfer Any operation involving a DMA channel follows the same three steps: 1. Channel initialization—The transfer control descriptor, contained in the channel registers, is loaded with address pointers, a byte-transfer count, and control information using accesses from the slave peripheral bus.
Page 323: Source Address Register (Dma_Sarn)
Chapter 23 DMA Controller Module DMA memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4000_8100 Source Address Register (DMA_SAR0) 0000_0000h 23.3.1/323 4000_8104 Destination Address Register (DMA_DAR0) 0000_0000h 23.3.2/324 DMA Status Register / Byte Count Register 4000_8108 0000_0000h 23.3.3/325...
Page 324: Destination Address Register (Dma_Darn)
Memory Map and Registers DMA_SARn field descriptions Field Description 31–0 Each SAR contains the byte address used by the DMA controller to read data. The SARn is typically aligned on a 0-modulo-ssize boundary—that is, on the natural alignment of the source data. Restriction: Bits 31-20 of this register must be written with one of only four allowed values.
Page 325: Dma Status Register / Byte Count Register (Dma_Dsr_Bcrn)
Chapter 23 DMA Controller Module DMA_DARn field descriptions (continued) Field Description After being written with one of the allowed values, bits 31-20 read back as the written value. After being written with any other value, bits 31-20 read back as an indeterminate value. 23.3.3 DMA Status Register / Byte Count Register (DMA_DSR_BCRn) DSR and BCR are two logical registers that occupy one 32-bit address.
Page 326: Freescale Semiconductor, Inc
Memory Map and Registers DMA_DSR_BCRn field descriptions Field Description This field is reserved. Reserved This read-only field is reserved and always has the value 0. Configuration error Any of the following conditions causes a configuration error: • BCR, SAR, or DAR does not match the requested transfer size. •...
Page 327: Dma Control Register (Dma_Dcrn)
Chapter 23 DMA Controller Module DMA_DSR_BCRn field descriptions (continued) Field Description greater than 0F_FFFFh causes a configuration error when the channel starts to execute. After being written with a value in this range, bits 23-20 of BCR read back as 1111b. 23.3.4 DMA Control Register (DMA_DCRn) Address: 4000_8000h base + 10Ch offset + (16d ×...
Page 328: Freescale Semiconductor, Inc
Memory Map and Registers DMA_DCRn field descriptions (continued) Field Description Cycle steal DMA continuously makes read/write transfers until the BCR decrements to 0. Forces a single read/write transfer per request. Auto-align AA and SIZE bits determine whether the source or destination is auto-aligned; that is, transfers are optimized based on the address and size.
Page 329: Freescale Semiconductor, Inc
Chapter 23 DMA Controller Module DMA_DCRn field descriptions (continued) Field Description 16-bit Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation) Start transfer START DMA inactive The DMA begins the transfer in accordance to the values in the TCDn. START is cleared automatically after one module clock and always reads as logic 0.
Page 330: Freescale Semiconductor, Inc
Memory Map and Registers DMA_DCRn field descriptions (continued) Field Description 1010 Circular buffer size is 8 KB 1011 Circular buffer size is 16 KB 1100 Circular buffer size is 32 KB 1101 Circular buffer size is 64 KB 1110 Circular buffer size is 128 KB 1111 Circular buffer size is 256 KB Disable request...
Page 331: Functional Description
Chapter 23 DMA Controller Module 23.4 Functional Description In the following discussion, the term DMA request implies that DCRn[START] is set, or DCRn[ERQ] is set and then followed by assertion of the properly selected DMA peripheral request. The START bit is cleared when the channel is activated. Before initiating a dual-address access, the DMA module verifies that DCRn[SSIZE] and DCRn[DSIZE] are consistent with the source and destination addresses.
Page 332: Channel Initialization And Startup
Functional Description 23.4.2 Channel Initialization and Startup Before a data transfer starts, the channel's transfer control descriptor must be initialized with information describing configuration, request-generation method, and pointers to the data to be moved. 23.4.2.1 Channel Prioritization The four DMA channels are prioritized based on number, with channel 0 having highest priority and channel 3 having the lowest, that is, channel 0 >...
Page 333: Dual-Address Data Transfer Mode
Chapter 23 DMA Controller Module • SARn and DARn change after each data transfer depending on DCRn[SSIZE, DSIZE, SINC, DINC, SMOD, DMOD] and the starting addresses. Increment values can be 1, 2, or 4 for 8-bit, 16-bit, or 32-bit transfers, respectively. If the address register is programmed to remain unchanged, the register is not incremented after the data transfer.
Page 334: Advanced Data Transfer Controls: Auto-Alignment
Functional Description • Dual-address write—The DMA controller drives the DARn value onto the system address bus. When the appropriate number of write cycles complete (multiple writes if the source size is larger than the destination), DARn increments by the appropriate number of bytes if DCRn[DINC] is set.
Page 335: Termination
Chapter 23 DMA Controller Module 3. Read 4 bytes from 0x2000_0004, increment SARn, write 4 bytes. 4. Repeat 4-byte operations until SARn equals 0x2000_00F0. 5. Read byte from 0x2000_00F0, increment SARn, write byte. If DSIZE is another size, data writes are optimized to write the largest size allowed based on the address, but not exceeding the configured size.
Page 336: Kl04 Sub-Family Reference Manual, Rev. 3.1, November
Functional Description KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc.
Page 337: Introduction
Chapter 24 Multipurpose Clock Generator (MCG) 24.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The multipurpose clock generator (MCG) module provides several clock source choices for the MCU. The module contains a frequency-locked loop (FLL). The FLL is controllable by either an internal or an external reference clock.
Page 338: Freescale Semiconductor, Inc
Introduction • Internal or external reference clock can be used as the FLL source. • Can be used as a clock source for other on-chip peripherals. • Internal reference clock generator: • Slow clock with nine trim bits for accuracy •...
Page 339: Freescale Semiconductor, Inc
Chapter 24 Multipurpose Clock Generator (MCG) Crystal Oscillator External Reference Clock CLKS OSCINIT0 MCG Crystal Oscillator Enable Detect EREFS0 IREFS HGO0 ATMS RANGE0 STOP IREFSTEN Auto Trim Machine IRCLKEN MCGIRCLK SCTRIM IRCS Internal CLKS CLKS Reference SCFTRIM Slow Clock Clock IRCSCLK Generator Fast Clock...
Page 340: Modes Of Operation
External Signal Description 24.1.2 Modes of Operation The MCG has the following modes of operation: FEI, FEE, FBI, FBE, BLPI, BLPE, and Stop. For details, see MCG modes of operation. 24.2 External Signal Description There are no MCG signals that connect off chip. 24.3 Memory Map/Register Definition This section includes the memory map and register definition.
Page 341: Freescale Semiconductor, Inc
Chapter 24 Multipurpose Clock Generator (MCG) MCG_C1 field descriptions Field Description 7–6 Clock Source Select CLKS Selects the clock source for MCGOUTCLK . Encoding 0 — Output of FLL is selected. Encoding 1 — Internal reference clock is selected. Encoding 2 — External reference clock is selected. Encoding 3 —...
Page 342: Mcg Control 2 Register (Mcg_C2)
Memory Map/Register Definition 24.3.2 MCG Control 2 Register (MCG_C2) Address: 4006_4000h base + 1h offset = 4006_4001h Read LOCRE0 RANGE0 HGO0 EREFS0 IRCS Write Reset MCG_C2 field descriptions Field Description Loss of Clock Reset Enable LOCRE0 Determines whether an interrupt or a reset request is made following a loss of OSC0 external reference clock.
Page 343: Mcg Control 3 Register (Mcg_C3)
Chapter 24 Multipurpose Clock Generator (MCG) MCG_C2 field descriptions (continued) Field Description Slow internal reference clock selected. Fast internal reference clock selected. 24.3.3 MCG Control 3 Register (MCG_C3) Address: 4006_4000h base + 2h offset = 4006_4002h Read SCTRIM Write Reset * Notes: •...
Page 344: Freescale Semiconductor, Inc
Memory Map/Register Definition MCG_C4 field descriptions Field Description DCO Maximum Frequency with 32.768 kHz Reference DMX32 The DMX32 bit controls whether the DCO frequency range is narrowed to its maximum frequency with a 32.768 kHz reference. The following table identifies settings for the DCO frequency range. NOTE: The system clocks derived from this source should not exceed their specified maximums.
Page 345: Mcg Control 6 Register (Mcg_C6)
Chapter 24 Multipurpose Clock Generator (MCG) 24.3.5 MCG Control 6 Register (MCG_C6) Address: 4006_4000h base + 5h offset = 4006_4005h Read Write Reset MCG_C6 field descriptions Field Description 7–6 Reserved Reserved This field is reserved. This read-only field is reserved and always has the value 0. Clock Monitor Enable Determines if a reset request is made following a loss of external clock indication.
Page 346: Mcg Status And Control Register (Mcg_Sc)
Memory Map/Register Definition MCG_S field descriptions (continued) Field Description Internal Reference Status IREFST This bit indicates the current source for the FLL reference clock. The IREFST bit does not update immediately after a write to the IREFS bit due to internal synchronization between clock domains. Source of FLL reference clock is the external reference clock.
Page 347: Freescale Semiconductor, Inc
Chapter 24 Multipurpose Clock Generator (MCG) MCG_SC field descriptions (continued) Field Description Writing to C1, C3, C4, and SC registers or entering Stop mode aborts the auto trim operation and clears this bit. Auto Trim Machine disabled. Auto Trim Machine enabled. Automatic Trim Machine Select ATMS Selects the IRCS clock for Auto Trim Test.
Page 348: Mcg Auto Trim Compare Value High Register (Mcg_Atcvh)
Functional Description 24.3.8 MCG Auto Trim Compare Value High Register (MCG_ATCVH) Address: 4006_4000h base + Ah offset = 4006_400Ah Read ATCVH Write Reset MCG_ATCVH field descriptions Field Description 7–0 ATM Compare Value High ATCVH Values are used by Auto Trim Machine to compare and adjust Internal Reference trim values during ATM SAR conversion.
Page 349: Freescale Semiconductor, Inc
Chapter 24 Multipurpose Clock Generator (MCG) Reset BLPE BLPI Returns to the state that was active before Entered from any state when the MCU entered Stop mode, unless a the MCU enters Stop mode Stop reset occurs while in Stop mode. Figure 24-11.
Page 350: Freescale Semiconductor, Inc
Functional Description Table 24-11. MCG modes of operation (continued) Mode Description FLL Engaged External FLL engaged external (FEE) mode is entered when all the following conditions occur: (FEE) • C1[CLKS] bits are written to 00 • C1[IREFS] bit is written to 0 •...
Page 351: Freescale Semiconductor, Inc
Chapter 24 Multipurpose Clock Generator (MCG) Table 24-11. MCG modes of operation (continued) Mode Description Bypassed Low Power Bypassed Low Power External (BLPE) mode is entered when all the following conditions occur: External (BLPE) • C1[CLKS] bits are written to 10 •...
Page 352: Low Power Bit Usage
Functional Description 24.4.2 Low Power Bit Usage The C2[LP] bit is provided to allow the FLL to be disabled and thus conserve power when these systems are not being used. The C4[DRST_DRS] can not be written while C2[LP] bit is 1. However, in some applications, it may be desirable to enable the FLL and allow it to lock for maximum accuracy before switching to an engaged mode.
Page 353: External Reference Clock
Chapter 24 Multipurpose Clock Generator (MCG) 24.4.4 External Reference Clock The MCG module can support an external reference clock in all modes. See the device datasheet for external reference frequency range. When C1[IREFS] is set, the external reference clock will not be used by the FLL. In these mode, the frequency can be equal to the maximum frequency the chip-level timing specifications will support.
Page 354: Freescale Semiconductor, Inc
Functional Description enabled is controlled by the ATC[ATMS] control bit (ATC[ATMS]=0 selects the 32 kHz IRC and ATC[ATMS]=1 selects the 4 MHz IRC). If 4 MHz IRC is selected for the ATM, a divide by 128 is enabled to divide down the 4 MHz IRC to a range of 31.250 kHz. When MCG ATM is enabled by writing ATC[ATME] bit to 1, The ATM machine will start auto trimming the selected IRC clock.
Page 355: Initialization / Application Information
Chapter 24 Multipurpose Clock Generator (MCG) 24.5 Initialization / Application information This section describes how to initialize and configure the MCG module in an application. The following sections include examples on how to initialize the MCG and properly switch between the various available modes. 24.5.1 MCG module initialization sequence The MCG comes out of reset configured for FEI mode.
Page 356: Freescale Semiconductor, Inc
Initialization / Application information appropriately here according to the external reference frequency to keep the FLL reference clock in the range of 31.25 kHz to 39.0625 kHz. Although the FLL is bypassed, it is still on in FBE mode. • The internal reference can optionally be kept running by setting the C1[IRCLKEN] bit.
Page 357: Using A 32.768 Khz Reference
Chapter 24 Multipurpose Clock Generator (MCG) • When using a 32.768 kHz external reference, if the maximum mid-range DCO frequency that can be achieved with a 32.768 kHz reference is desired, set C4[DRST_DRS] bits to 2'b01 and set C4[DMX32] bit to 1. The resulting DCO output (MCGOUTCLK) frequency with the new multiplier of 1464 will be 48 MHz.
Page 358: Kl04 Sub-Family Reference Manual, Rev. 3.1, November
Initialization / Application information resulting DCO output frequency is 62.91 MHz at mid high-range. If C4[DRST_DRS] bits are set to 2'b11, the multiplication factor is set to 2560, and the resulting DCO output frequency is 83.89 MHz at high-range. In FBI and FEI modes, setting C4[DMX32] bit is not recommended. If the internal reference is trimmed to a frequency above 32.768 kHz, the greater FLL multiplication factor could potentially push the microcontroller system clock out of specification and damage the part.
Page 359: Freescale Semiconductor, Inc
Chapter 24 Multipurpose Clock Generator (MCG) This section will include three mode switching examples using an 4 MHz external crystal. 24.5.3.1 Example 1: Moving from FEI to BLPE mode: External Crystal = 4 MHz, MCGOUTCLK frequency = 4 MHz In this example, the MCG will move through the proper operational modes from FEI to BLPE to achieve 4 MHz MCGOUTCLK frequency from 4 MHz external crystal reference.
Page 360: Freescale Semiconductor, Inc
Initialization / Application information START IN FEI MODE C2 = 0x1C C1 = 0x40 CHECK S[OSCINIT0] = 1? CHECK S[IREFST] = 0? CHECK S[CLKST] = %10? C2 = 0x1E (C2[LP] = 1) Continue in BLPE mode Figure 24-12. Flowchart of FEI to BLPE mode transition using a 4 MHz crystal KL04 Sub-Family Reference Manual, Rev.
Page 361: Freescale Semiconductor, Inc
Chapter 24 Multipurpose Clock Generator (MCG) 24.5.3.2 Example 2: Moving from BLPE to BLPI mode: MCGOUTCLK frequency = 2 MHz In this example, the MCG will move through the proper operational modes from BLPE mode with a 4 MHz crystal configured for a 4 MHz MCGOUTCLK frequency (see previous example) to BLPI mode with a 2 MHz MCGOUTCLK frequency.
Page 362: Freescale Semiconductor, Inc
Initialization / Application information START IN BLPE MODE C2 = 0x1C (C2[LP] = 0) C1 = 0x64 CHECK S[IREFST] = 0? CHECK S[CLKST] = %01? C2 = 0x23 CHECK S[IRCST] = 1? CONTINUE IN BLPI MODE Figure 24-13. Flowchart of BLPE to BLPI mode transition using an 4 MHz crystal KL04 Sub-Family Reference Manual, Rev.
Page 363: Freescale Semiconductor, Inc
Chapter 24 Multipurpose Clock Generator (MCG) 24.5.3.3 Example 3: Moving from BLPI to FEE mode In this example, the MCG will move through the proper operational modes from BLPI mode at a 32 kHz MCGOUTCLK frequency running off the internal reference clock (see previous example) to FEE mode using a 4 MHz crystal configured for a 20 MHz MCGOUTCLK frequency.
Page 364: Freescale Semiconductor, Inc
Initialization / Application information multiplication factor from 640 to 1280. To return the MCGOUTCLK frequency to 20 MHz, set C4[DRST_DRS] bits to 2'b00 again, and the FLL multiplication factor will switch back to 640. START IN BLPI MODE CHECK S[IREFST] = 0? C2 = 0x00 C2 = 0x1C CHECK...
Page 365: Introduction
Chapter 25 Oscillator (OSC) 25.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The OSC module is a crystal oscillator. The module, in conjunction with an external crystal or resonator, generates a reference clock for the MCU. 25.2 Features and Modes Key features of the module are: •...
Page 366: Block Diagram
Block Diagram 25.3 Block Diagram The OSC module uses a crystal or resonator to generate three filtered oscillator clock signals. Three clocks are output from OSC module: OSCCLK for MCU system, OSCERCLK for on-chip peripherals, and OSC32KCLK. The OSCCLK can only work in run mode.
Page 367: External Crystal / Resonator Connections
Chapter 25 Oscillator (OSC) Table 25-1. OSC Signal Descriptions Signal Description EXTAL External clock/Oscillator input XTAL Oscillator output 25.5 External Crystal / Resonator Connections The connections for a crystal/resonator frequency reference are shown in the following figures. When using low-frequency, low-power mode, the only external component is the crystal or ceramic resonator itself.
Page 368: External Clock Connections
External Clock Connections XTAL EXTAL Crystal or Resonator Figure 25-3. Crystal/Ceramic Resonator Connections - Connection 2 NOTE Connection 1 and Connection 2 should use internal capacitors as the load of the oscillator by configuring the CR[SCxP] bits. XTAL EXTAL Crystal or Resonator Figure 25-4.
Page 369: Memory Map/Register Definitions
Chapter 25 Oscillator (OSC) XTAL EXTAL Clock Input Figure 25-5. External Clock Connections 25.7 Memory Map/Register Definitions Some oscillator module register bits are typically incorporated into other peripherals such as MCG or SIM. 25.7.1 OSC Memory Map/Register Definition OSC memory map Absolute Width Section/...
Page 370: Functional Description
Functional Description OSCx_CR field descriptions (continued) Field Description External reference clock is inactive. External reference clock is enabled. This field is reserved. Reserved This read-only field is reserved and always has the value 0. External Reference Stop Enable EREFSTEN Controls whether or not the external reference clock (OSCERCLK) remains enabled when MCU enters Stop mode.
Page 371: Freescale Semiconductor, Inc
Chapter 25 Oscillator (OSC) Oscillator OFF OSCCLK OSC_CLK_OUT = Static not requested OSCCLK requested OSCCLK requested && && Select OSC internal clock Select clock from EXTAL signal Start-Up External Clock Mode Oscillator ON, not yet stable Oscillator ON OSC_CLK_OUT = Static OSC_CLK_OUT = EXTAL CNT_DONE_4096 Stable...
Page 372: Osc Module Modes
Functional Description 25.8.1.2 Oscillator Start-Up The OSC enters start-up state when it is configured to generate clocks (internally the OSC_EN transitions high) using the internal oscillator circuits by setting the external reference clock selection bit. In this state, the OSC module is enabled and oscillations are starting up, but have not yet stabilized.
Page 373: Counter
Chapter 25 Oscillator (OSC) NOTE For information about low power modes of operation used in this chip and their alignment with some OSC modes, refer to the chip's Power Management details. 25.8.2.1 Low-Frequency, Low-Power Mode In low-frequency, low-power mode, the oscillator uses a gain control loop to minimize power consumption.
Page 374: Reset
Reset 25.9 Reset There is no reset state associated with the OSC module. The counter logic is reset when the OSC is not configured to generate clocks. There are no sources of reset requests for the OSC module. 25.10 Low Power Modes Operation When the MCU enters Stop modes, the OSC is functional depending on ERCLKEN and EREFSETN bit settings.
Page 375: Introduction
Chapter 26 Flash Memory Controller (FMC) 26.1 Introduction The Flash Memory Controller (FMC) is a memory acceleration unit that provides: • an interface between bus masters and the 32-bit program flash memory. • a buffer and a cache that can accelerate program flash memory data transfers. 26.1.1 Overview The Flash Memory Controller manages the interface between bus masters and the 32-bit program flash memory.
Page 376: Modes Of Operation
Modes of operation • 32-bit prefetch speculation buffer for program flash accesses with controls for instruction/data access • 4-way, 4-set, 32-bit line size program flash memory cache for a total of sixteen 32-bit entries with invalidation control 26.2 Modes of operation The FMC operates only when a bus master accesses the program flash memory.
Page 377: Kl04 Sub-Family Reference Manual, Rev. 3.1, November
Chapter 26 Flash Memory Controller (FMC) • Data speculation is disabled • Data caching is enabled Though the default configuration provides flash acceleration, advanced users may desire to customize the FMC buffer configurations to maximize throughput for their use cases. For example, the user may adjust the controls to enable buffering per access type (data or instruction).
Page 378: Freescale Semiconductor, Inc
Functional description KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc.
Page 379: Introduction
Chapter 27 Flash Memory Module (FTFA) 27.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The flash memory module includes the following accessible memory regions: • Program flash memory for vector space and code store Flash memory is ideal for single-supply applications, permitting in-the-field erase and reprogramming operations without the need for any external high voltage power sources.
Page 380: Features
Introduction 27.1.1 Features The flash memory module includes the following features. NOTE See the device's Chip Configuration details for the exact amount of flash memory available on your device. 27.1.1.1 Program Flash Memory Features • Sector size of 1 Kbyte •...
Page 381: Glossary
Chapter 27 Flash Memory Module (FTFA) Interrupt Program flash Status Register access registers Memory controller Control registers To MCU's flash controller Figure 27-1. Flash Block Diagram 27.1.3 Glossary Command write sequence — A series of MCU writes to the flash FCCOB register group that initiates and controls the execution of flash algorithms that are built into the flash memory module.
Page 382: External Signal Description
External Signal Description NVM Special Mode — An NVM mode enabling external, off-chip access to the memory resources in the flash memory module. A reduced flash command set is available when the MCU is secured. See the Chip Configuration details for information on when this mode is used.
Page 383: Flash Configuration Field Description
Chapter 27 Flash Memory Module (FTFA) 27.3.1 Flash Configuration Field Description The program flash memory contains a 16-byte flash configuration field that stores default protection settings (loaded on reset) and security information that allows the MCU to restrict access to the flash memory module. Flash Configuration Field Byte Size (Bytes) Field Description...
Page 384: Register Descriptions
Memory Map and Registers user. The Program Once Field can be read any number of times. This section of the program flash IFR is accessed in 4-Byte records using the Read Once and Program Once commands (see Read Once Command Program Once Command).
Page 385: Freescale Semiconductor, Inc
Chapter 27 Flash Memory Module (FTFA) FTFA memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) Flash Common Command Object Registers 4002_000D 27.33.5/390 (FTFA_FCCOBA) Flash Common Command Object Registers 4002_000E 27.33.5/390 (FTFA_FCCOB9) Flash Common Command Object Registers 4002_000F 27.33.5/390 (FTFA_FCCOB8)
Page 386: Freescale Semiconductor, Inc
Memory Map and Registers FTFA_FSTAT field descriptions (continued) Field Description Flash command in progress Flash command has completed Flash Read Collision Error Flag RDCOLERR The RDCOLERR error bit indicates that the MCU attempted a read from a flash memory resource that was being manipulated by a flash command (CCIF=0).
Page 387: Freescale Semiconductor, Inc
Chapter 27 Flash Memory Module (FTFA) Address: 4002_0000h base + 1h offset = 4002_0001h Read ERSAREQ CCIE RDCOLLIE ERSSUSP Write Reset FTFA_FCNFG field descriptions Field Description Command Complete Interrupt Enable CCIE The CCIE bit controls interrupt generation when a flash command completes. Command complete interrupt disabled Command complete interrupt enabled.
Page 388: Freescale Semiconductor, Inc
Memory Map and Registers 27.33.3 Flash Security Register (FTFA_FSEC) This read-only register holds all bits associated with the security of the MCU and flash memory module. During the reset sequence, the register is loaded with the contents of the flash security byte in the Flash Configuration Field located in program flash memory.
Page 389: Freescale Semiconductor, Inc
Chapter 27 Flash Memory Module (FTFA) FTFA_FSEC field descriptions (continued) Field Description Freescale factory access granted Freescale factory access denied Freescale factory access denied Freescale factory access granted 1–0 Flash Security These bits define the security state of the MCU. In the secure state, the MCU limits access to flash memory module resources.
Page 390: Freescale Semiconductor, Inc
Memory Map and Registers 27.33.5 Flash Common Command Object Registers (FTFA_FCCOBn) The FCCOB register group provides 12 bytes for command codes and parameters. The individual bytes within the set append a 0-B hex identifier to the FCCOB register name: FCCOB0, FCCOB1, ..., FCCOBB. Address: 4002_0000h base + 4h offset + (1d ×...
Page 391: Freescale Semiconductor, Inc
Chapter 27 Flash Memory Module (FTFA) FTFA_FCCOBn field descriptions (continued) Field Description FCCOB Number Typical Command Parameter Contents [7:0] Data Byte 6 Data Byte 7 FCCOB Endianness and Multi-Byte Access : The FCCOB register group uses a big endian addressing convention. For all command parameter fields larger than 1 byte, the most significant data resides in the lowest FCCOB register number.
Page 392: Functional Description
Functional Description Program flash protection register Flash Configuration Field offset address FPROT2 0x0009 FPROT3 0x0008 To change the program flash protection that is loaded during the reset sequence, unprotect the sector of program flash memory that contains the Flash Configuration Field.
Page 393: Flash Protection
Chapter 27 Flash Memory Module (FTFA) 27.4.1 Flash Protection Individual regions within the flash memory can be protected from program and erase operations. Protection is controlled by the following registers: • FPROTn — Four registers that protect 32 regions of the program flash memory as shown in the following figure Program flash 0x0_0000...
Page 394: Flash Operation In Low-Power Modes
Functional Description Note Vector addresses and their relative interrupt priority are determined at the MCU level. Some devices also generate a bus error response as a result of a Read Collision Error event. See the chip configuration information to determine if a bus error response is also supported.
Page 395: Flash Reads And Ignored Writes
Chapter 27 Flash Memory Module (FTFA) 27.4.5 Flash Reads and Ignored Writes The flash memory module requires only the flash address to execute a flash memory read. The MCU must not read from the flash memory while commands are running (as evidenced by CCIF=0) on that block.
Page 396: Freescale Semiconductor, Inc
Functional Description 27.4.8.1 Command Write Sequence Flash commands are specified using a command write sequence illustrated in Figure 27-25. The flash memory module performs various checks on the command (FCCOB) content and continues with command execution if all requirements are fulfilled. Before launching a command, the ACCERR and FPVIOL bits in the FSTAT register must be zero and the CCIF flag must read 1 to verify that any previous command has completed.
Page 397: Freescale Semiconductor, Inc
Chapter 27 Flash Memory Module (FTFA) Program and erase commands also check the address to determine if the operation is requested to execute on protected areas. If the protection check fails, the FSTAT[FPVIOL] (protection error) flag is set. Command processing never proceeds to execution when the parameter or protection step fails.
Page 398: Freescale Semiconductor, Inc
Functional Description START Read: FSTAT register FCCOB Availability Check CCIF Previous command complete? = ‘1’? Results from previous command Access Error and ACCERR/ Protection Violation Clear the old errors FPVIOL Check Write 0x30 to FSTAT register Set? Write to the FCCOB registers to load the required command parameter.
Page 399: Freescale Semiconductor, Inc
Chapter 27 Flash Memory Module (FTFA) FCMD Command Program flash Function 0x09 Erase Flash Sector × Erase all bytes in a program flash sector. 0x40 Read 1s All Blocks × Verify that the program flash block is erased then release MCU security.
Page 400: Margin Read Commands
Functional Description 27.4.9 Margin Read Commands The Read-1s commands (Read 1s All Blocks and Read 1s Section) and the Program Check command have a margin choice parameter that allows the user to apply non- standard read reference levels to the program flash array reads performed by these commands.
Page 401: Flash Command Description
Chapter 27 Flash Memory Module (FTFA) 27.4.10 Flash Command Description This section describes all flash commands that can be launched by a command write sequence. The flash memory module sets the FSTAT[ACCERR] bit and aborts the command execution if any of the following illegal conditions occur: •...
Page 402: Freescale Semiconductor, Inc
Functional Description Upon clearing CCIF to launch the Read 1s Section command, the flash memory module sets the read margin for 1s according to Table 27-27 and then reads all locations within the specified section of flash memory. If the flash memory module fails to read all 1s (i.e. the flash section is not erased), the FSTAT[MGSTAT0] bit is set.
Page 403: Freescale Semiconductor, Inc
Chapter 27 Flash Memory Module (FTFA) Upon clearing CCIF to launch the Program Check command, the flash memory module sets the read margin for 1s according to Table 27-30, reads the specified longword, and compares the actual read data to the expected data provided by the FCCOB. If the comparison at margin-1 fails, the FSTAT[MGSTAT0] bit is set.
Page 404: Freescale Semiconductor, Inc
Functional Description Table 27-32. Read Resource Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0x03 (RDRSRC) Flash address [23:16] Flash address [15:8] Flash address [7:0] Returned Values Read Data [31:24] Read Data [23:16] Read Data [15:8] Read Data [7:0] User-provided values Resource Select Code (see Table 27-33)
Page 405: Freescale Semiconductor, Inc
Chapter 27 Flash Memory Module (FTFA) CAUTION A flash memory location must be in the erased state before being programmed. Cumulative programming of bits (back-to- back program operations without an intervening erase) within a flash memory location is not allowed. Re-programming of existing 0s to 0 is not allowed as this overstresses the device.
Page 406: Freescale Semiconductor, Inc
Functional Description Table 27-36. Program Longword Command Error Handling (continued) Error Condition Error Bit Any errors have been encountered during the verify operation FSTAT[MGSTAT0] 27.4.10.5 Erase Flash Sector Command The Erase Flash Sector operation erases all addresses in a flash sector. Table 27-37.
Page 407: Freescale Semiconductor, Inc
Chapter 27 Flash Memory Module (FTFA) ERSSUSP bit is set, the Erase Flash Sector operation is suspended and the flash memory module sets CCIF. While ERSSUSP is set, all writes to flash registers are ignored except for writes to the FSTAT and FCNFG registers. If an Erase Flash Sector operation effectively completes before the flash memory module detects that a suspend request has been made, the flash memory module clears the ERSSUSP bit prior to setting CCIF.
Page 408: Freescale Semiconductor, Inc
Functional Description Enter with CCIF = 1 Command Initiation ERSSCR Command (Write FCCOB) Memory Controller Command Processing Launch/Resume Command (Clear CCIF) Resume ERSSCR SUSPACK=1 Next Command CCIF = 1? (Write FCCOB) Restore Erase Algo Start Clear SUSPACK = 0 Interrupt? Execute DONE? Request Suspend...
Page 409: Freescale Semiconductor, Inc
Chapter 27 Flash Memory Module (FTFA) 27.4.10.6 Read 1s All Blocks Command The Read 1s All Blocks command checks if the program flash blocks have been erased to the specified read margin level, if applicable, and releases security if the readout passes, i.e.
Page 410: Freescale Semiconductor, Inc
Functional Description 27.4.10.7 Read Once Command The Read Once command provides read access to a reserved 64-byte field located in the program flash 0 IFR (see Program Flash IFR Map Program Once Field). Access to this field is via 16 records, each 4 bytes long. The Read Once field is programmed using the Program Once command described in Program Once Command.
Page 411: Freescale Semiconductor, Inc
Chapter 27 Flash Memory Module (FTFA) Table 27-44. Program Once Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0x43 (PGMONCE) Program Once record index (0x00 - 0x0F) Not Used Not Used Program Once Byte 0 value Program Once Byte 1 value Program Once Byte 2 value Program Once Byte 3 value After clearing CCIF to launch the Program Once command, the flash memory module...
Page 412: Freescale Semiconductor, Inc
Functional Description Table 27-46. Erase All Blocks Command FCCOB Requirements FCCOB Number FCCOB Contents [7:0] 0x44 (ERSALL) After clearing CCIF to launch the Erase All Blocks command, the flash memory module erases all program flash memory, then verifies that all are erased. If the flash memory module verifies that all flash memories were properly erased, security is released by setting the FSEC[SEC] field to the unsecure state.
Page 413: Freescale Semiconductor, Inc
Chapter 27 Flash Memory Module (FTFA) 27.4.10.10 Verify Backdoor Access Key Command The Verify Backdoor Access Key command only executes if the mode and security conditions are satisfied (see Flash Commands by Mode). Execution of the Verify Backdoor Access Key command is further qualified by the FSEC[KEYEN] bits. The Verify Backdoor Access Key command releases security if user-supplied keys in the FCCOB match those stored in the Backdoor Comparison Key bytes of the Flash Configuration Field (see...
Page 414: Security
Functional Description Table 27-49. Verify Backdoor Access Key Command Error Handling (continued) Error Condition Error Bit Backdoor key access has not been enabled (see the description of the FSEC register) FSTAT[ACCERR] This command is launched and the backdoor key has mismatched since the last power down FSTAT[ACCERR] reset 27.4.11 Security...
Page 415: Freescale Semiconductor, Inc
Chapter 27 Flash Memory Module (FTFA) 27.4.11.2 Changing the Security State The security state out of reset can be permanently changed by programming the security byte of the flash configuration field. This assumes that you are starting from a mode where the necessary program flash erase and program commands are available and that the region of the program flash containing the flash configuration field is unprotected.
Page 416: Reset Sequence
Functional Description module reverts back to the flash security byte in the Flash Configuration Field. The Verify Backdoor Access Key command sequence has no effect on the program and erase protections defined in the program flash protection registers. If the backdoor keys successfully match, the unsecured chip has full control of the contents of the Flash Configuration Field.
Page 417: Introduction
Chapter 28 Analog-to-Digital Converter (ADC) 28.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The 12-bit analog-to-digital converter (ADC) is a successive approximation ADC designed for operation within an integrated microcontroller system-on-chip. NOTE For the chip specific modes of operation, see the power management information of the device.
Page 418: Block Diagram
Introduction • Input clock selectable from up to four sources • Operation in Low-Power modes for lower noise • Asynchronous clock source for lower noise operation with option to output the clock • Selectable hardware conversion trigger with hardware channel select •...
Page 419: Kl04 Sub-Family Reference Manual, Rev. 3.1, November
Chapter 28 Analog-to-Digital Converter (ADC) ADHWTSA SC1A Conversion SC1n ADHWTSn trigger control A D T R G ADHWT (SC2, CFG1, CFG2) C o m p a re tru e Control Registers A D A C K E N Async Clock Gen Interrupt ADACK Clock...
Page 420: Voltage Reference Select
ADC Signal Descriptions Table 28-1. ADC Signal Descriptions Signal Description Single-Ended Analog Channel Inputs Voltage Reference Select High REFSH Voltage Reference Select Low REFSL Analog Power Supply Analog Ground 28.2.1 Analog Power (V The ADC analog portion uses V as its power connection. In some packages, V connected internally to V .
Page 421: Analog Channel Inputs (Adx)
Chapter 28 Analog-to-Digital Converter (ADC) In some packages, V is connected in the package to V and V to V . If REFH REFL externally available, the positive reference(s) may be connected to the same potential as or may be driven by an external source to a level between the minimum Ref Voltage High and the V potential.
Page 422: Adc Status And Control Registers 1 (Adcx_Sc1N)
Register definition ADC memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) ADC Plus-Side General Calibration Value Register 4003_B048 0000_0040h 28.3.15/437 (ADC0_CLP1) ADC Plus-Side General Calibration Value Register 4003_B04C 0000_0020h 28.3.16/437 (ADC0_CLP0) 28.3.1 ADC Status and Control Registers 1 (ADCx_SC1n) SC1A is used for both software and hardware trigger modes of operation.
Page 423: Freescale Semiconductor, Inc
Chapter 28 Analog-to-Digital Converter (ADC) Address: 4003_B000h base + 0h offset + (4d × i), where i=0d to 1d Reset AIEN ADCH Reset KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc.
Page 424: Freescale Semiconductor, Inc
Register definition ADCx_SC1n field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Conversion Complete Flag COCO This is a read-only field that is set each time a conversion is completed when the compare function is disabled, or SC2[ACFE]=0 and the hardware average function is disabled, or SC3[AVGE]=0.
Page 425: Adc Configuration Register 1 (Adcx_Cfg1)
Chapter 28 Analog-to-Digital Converter (ADC) ADCx_SC1n field descriptions (continued) Field Description 01110 AD14 is selected as input. 01111 AD15 is selected as input. 10000 AD16 is selected as input. 10001 AD17 is selected as input. 10010 AD18 is selected as input. 10011 AD19 is selected as input.
Page 426: Freescale Semiconductor, Inc
Register definition ADCx_CFG1 field descriptions (continued) Field Description Low-Power Configuration ADLPC Controls the power configuration of the successive approximation converter. This optimizes power consumption when higher sample rates are not required. Normal power configuration. Low-power configuration. The power is reduced at the expense of maximum clock speed. 6–5 Clock Divide Select ADIV...
Page 427: Adc Configuration Register 2 (Adcx_Cfg2)
Chapter 28 Analog-to-Digital Converter (ADC) 28.3.3 ADC Configuration Register 2 (ADCx_CFG2) Configuration Register 2 (CFG2) selects the special high-speed configuration for very high speed conversions and selects the long sample time duration during long sample mode. Address: 4003_B000h base + Ch offset = 4003_B00Ch Reset ADLSTS Reset...
Page 428: Adc Data Result Register (Adcx_Rn)
Register definition ADCx_CFG2 field descriptions (continued) Field Description Configures the ADC for very high-speed operation. The conversion sequence is altered with 2 ADCK cycles added to the conversion time to allow higher speed conversion clocks. Normal conversion sequence selected. High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time. 1–0 Long Sample Time Select ADLSTS...
Page 429: Compare Value Registers (Adcx_Cvn)
Chapter 28 Analog-to-Digital Converter (ADC) Address: 4003_B000h base + 10h offset + (4d × i), where i=0d to 1d Reset ADCx_Rn field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 15–0 Data result 28.3.5 Compare Value Registers (ADCx_CVn)
Page 430: Status And Control Register 2 (Adcx_Sc2)
Register definition 28.3.6 Status and Control Register 2 (ADCx_SC2) The status and control register 2 (SC2) contains the conversion active, hardware/software trigger select, compare function, and voltage reference select of the ADC module. Address: 4003_B000h base + 20h offset = 4003_B020h Reset REFSEL Reset...
Page 431: Freescale Semiconductor, Inc
Chapter 28 Analog-to-Digital Converter (ADC) ADCx_SC2 field descriptions (continued) Field Description • Software trigger: When software trigger is selected, a conversion is initiated following a write to SC1A. • Hardware trigger: When hardware trigger is selected, a conversion is initiated following the assertion of the ADHWT input after a pulse of the ADHWTSn input.
Page 432: Status And Control Register 3 (Adcx_Sc3)
Register definition 28.3.7 Status and Control Register 3 (ADCx_SC3) The Status and Control Register 3 (SC3) controls the calibration, continuous convert, and hardware averaging functions of the ADC module. Address: 4003_B000h base + 24h offset = 4003_B024h Reset AVGS Reset ADCx_SC3 field descriptions Field Description...
Page 433: Adc Offset Correction Register (Adcx_Ofs)
Chapter 28 Analog-to-Digital Converter (ADC) ADCx_SC3 field descriptions (continued) Field Description Calibration completed normally. Calibration failed. ADC accuracy specifications are not guaranteed. 5–4 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Continuous Conversion Enable ADCO Enables continuous conversions.
Page 434: Adc Plus-Side Gain Register (Adcx_Pg)
Register definition ADCx_OFS field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 15–0 Offset Error Correction Value 28.3.9 ADC Plus-Side Gain Register (ADCx_PG) The Plus-Side Gain Register (PG) contains the gain error correction for the overall conversion in single-ended mode.
Page 435: Adc Plus-Side General Calibration Value Register (Adcx_Clps)
Chapter 28 Analog-to-Digital Converter (ADC) Address: 4003_B000h base + 34h offset = 4003_B034h CLPD Reset ADCx_CLPD field descriptions Field Description 31–6 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 5–0 Calibration Value CLPD 28.3.11 ADC Plus-Side General Calibration Value Register (ADCx_CLPS)
Page 436: Adc Plus-Side General Calibration Value Register (Adcx_Clp3)
Register definition ADCx_CLP4 field descriptions Field Description 31–10 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 9–0 Calibration Value CLP4 28.3.13 ADC Plus-Side General Calibration Value Register (ADCx_CLP3) For more information, see CLPD register description. Address: 4003_B000h base + 40h offset = 4003_B040h CLP3 Reset...
Page 437: Adc Plus-Side General Calibration Value Register (Adcx_Clp1)
Chapter 28 Analog-to-Digital Converter (ADC) 28.3.15 ADC Plus-Side General Calibration Value Register (ADCx_CLP1) For more information, see CLPD register description. Address: 4003_B000h base + 48h offset = 4003_B048h CLP1 Reset ADCx_CLP1 field descriptions Field Description 31–7 This field is reserved. Reserved This read-only field is reserved and always has the value 0.
Page 438: Functional Description
Functional description 28.4 Functional description The ADC module is disabled during reset, in Low-Power Stop mode, or when SC1n[ADCH] are all high; see the power management information for details. The module is idle when a conversion has completed and another conversion has not been initiated.
Page 439: Voltage Reference Selection
Chapter 28 Analog-to-Digital Converter (ADC) • ALTCLK: As defined for this MCU. See the chip configuration information. • Asynchronous clock (ADACK): This clock is generated from a clock source within the ADC module. When the ADACK clock source is selected, it is not required to be active prior to conversion start.
Page 440: Conversion Control
Functional description When an ADHWT source is available and hardware trigger is enabled, that is SC2[ADTRG]=1, a conversion is initiated on the rising-edge of ADHWT after a hardware trigger select event, that is, ADHWTSn, has occurred. If a conversion is in progress when a rising-edge of a trigger occurs, the rising-edge is ignored.
Page 441: Freescale Semiconductor, Inc
Chapter 28 Analog-to-Digital Converter (ADC) • Continuous conversion • Hardware average • Automatic compare of the conversion result to a software determined compare value 28.4.4.1 Initiating conversions A conversion is initiated: • Following a write to SC1A, with SC1n[ADCH] not all 1's, if software triggered operation is selected, that is, when SC2[ADTRG]=0.
Page 442: Freescale Semiconductor, Inc
Functional description 28.4.4.2 Completing conversions A conversion is completed when the result of the conversion is transferred into the data result registers, Rn. If the compare functions are disabled, this is indicated by setting of SC1n[COCO]. If hardware averaging is enabled, the respective SC1n[COCO] sets only if the last of the selected number of conversions is completed.
Page 443: Freescale Semiconductor, Inc
Chapter 28 Analog-to-Digital Converter (ADC) 28.4.4.4 Power control The ADC module remains in its idle state until a conversion is initiated. If ADACK is selected as the conversion clock source, but the asynchronous clock output is disabled, that is CFG2[ADACKEN]=0, the ADACK clock generator also remains in its idle state (disabled) until a conversion is initiated.
Page 444: Freescale Semiconductor, Inc
Functional description CFG2[ADHSC] is used to configure a higher clock input frequency. This will allow faster overall conversion times. To meet internal ADC timing requirements, CFG2[ADHSC] adds additional ADCK cycles. Conversions with CFG2[ADHSC]=1 take two more ADCK cycles. CFG2[ADHSC] must be used when the ADCLK exceeds the limit for CFG2[ADHSC]=0.
Page 445: Freescale Semiconductor, Inc
Chapter 28 Analog-to-Digital Converter (ADC) Table 28-55. Average number factor (AverageNum) (continued) SC3[AVGE] SC3[AVGS] Average number factor (AverageNum) Table 28-56. Base conversion time (BCT) Mode Base conversion time (BCT) 8b single-ended 17 ADCK cycles 10b single-ended 20 ADCK cycles 12b single-ended 20 ADCK cycles Table 28-57.
Page 446: Freescale Semiconductor, Inc
Functional description 28.4.4.6.1 Typical conversion time configuration A typical configuration for ADC conversion is: • 10-bit mode, with the bus clock selected as the input clock source • The input clock divide-by-1 ratio selected • Bus frequency of 8 MHz •...
Page 447: Automatic Compare Function
Chapter 28 Analog-to-Digital Converter (ADC) Table 28-60. Typical conversion time (continued) Variable Time LSTAdder 0 ADCK cycles HSCAdder The resulting conversion time is generated using the parameters listed in in the preceding table. Therefore, for bus clock and ADCK frequency equal to 20 MHz, the resulting conversion time is 1.45 µs.
Page 448: Freescale Semiconductor, Inc
Functional description CV2. After the input is sampled and converted, the compare values in CV1 and CV2 are used as described in the following table. There are six Compare modes as shown in the following table. Table 28-61. Compare modes ADCCV1 SC2[AC SC2[AC...
Page 449: Calibration Function
Chapter 28 Analog-to-Digital Converter (ADC) 28.4.6 Calibration function The ADC contains a self-calibration function that is required to achieve the specified accuracy. Calibration must be run, or valid calibration values written, after any reset and before a conversion is initiated. The calibration function sets the offset calibration value and the plus-side calibration values.
Page 450: Kl04 Sub-Family Reference Manual, Rev. 3.1, November
Functional description 2. Add the plus-side calibration results CLP0, CLP1, CLP2, CLP3, CLP4, and CLPS to the variable. 3. Divide the variable by two. 4. Set the MSB of the variable. 5. The previous two steps can be achieved by setting the carry bit, rotating to the right through the carry bit on the high byte and again on the low byte.
Page 451: Temperature Sensor
Chapter 28 Analog-to-Digital Converter (ADC) Note There is an effective limit to the values of offset that can be set by the user. If the magnitude of the offset is too high, the results of the conversions will cap off at the limits. The offset calibration function may be employed by the user to remove application offsets or DC bias values.
Page 452: Mcu Wait Mode Operation
Functional description the preceding equation. ADC Electricals table may only specify one temperature sensor slope value. In that case, the user could use the same slope for the calculation across the operational temperature range. For more information on using the temperature sensor, see the application note titled Temperature Sensor for the HCS08 Microcontroller Family (document AN3031).
Page 453: Mcu Low-Power Stop Mode Operation
Chapter 28 Analog-to-Digital Converter (ADC) 28.4.10.1 Normal Stop mode with ADACK disabled If the asynchronous clock, ADACK, is not selected as the conversion clock, executing a stop instruction aborts the current conversion and places the ADC in its Idle state. The contents of the ADC registers, including Rn, are unaffected by Normal Stop mode.
Page 454: Initialization Information
Initialization information 28.5 Initialization information This section gives an example that provides some basic direction on how to initialize and configure the ADC module. The user can configure the module for 12-bit, 10-bit, or 8-bit single-ended resolution, single or continuous conversion, and a polled or interrupt approach, among many other options.
Page 455: Freescale Semiconductor, Inc
Chapter 28 Analog-to-Digital Converter (ADC) 28.5.1.2 Pseudo-code example In this example, the ADC module is set up with interrupts enabled to perform a single 10- bit conversion at low-power with a long sample time on input channel 1, where ADCK is derived from the bus clock divided by 1.
Page 456: Application Information
Application information Reset Initialize ADC CFG1 = 0x98 SC2 = 0x00 SC1n = 0x41 Check SC1n[COCO]=1? Read Rn to clear SC1n[COCO] Continue Figure 28-48. Initialization flowchart example 28.6 Application information The ADC has been designed to be integrated into a microcontroller for use in embedded control applications requiring an ADC.
Page 457: Freescale Semiconductor, Inc
Chapter 28 Analog-to-Digital Converter (ADC) • V is shared on the same pin as the MCU digital V • V and V are shared with the MCU digital supply pins—In these cases, there are separate pads for the analog supplies bonded to the same pin as the corresponding digital supply so that some degree of isolation between the supplies is maintained.
Page 458: Sources Of Error
Application information 28.6.1.3 Analog input pins The external analog inputs are typically shared with digital I/O pins on MCU devices. Empirical data shows that capacitors on the analog inputs improve performance in the presence of noise or when the source impedance is high. Use of 0.01 μF capacitors with good high-frequency characteristics is sufficient.
Page 459: Freescale Semiconductor, Inc
Chapter 28 Analog-to-Digital Converter (ADC) LSBERR = value of acceptable sampling error in LSBs N = 8 in 8-bit mode, 10 in 10-bit mode, 12 in 12-bit mode Higher source resistances or higher-accuracy sampling is possible by setting CFG1[ADLSMP] and changing CFG2[ADLSTS] to increase the sample window, or decreasing ADCK frequency to increase sample time.
Page 460: Freescale Semiconductor, Inc
Application information There are some situations where external system activity causes radiated or conducted noise emissions or excessive V noise is coupled into the ADC. In these situations, or when the MCU cannot be placed in Wait or Normal Stop mode, or I/O activity cannot be halted, the following actions may reduce the effect of noise on the accuracy: •...
Page 461: Freescale Semiconductor, Inc
Chapter 28 Analog-to-Digital Converter (ADC) • Zero-scale error (E ), sometimes called offset: This error is defined as the difference between the actual code width of the first conversion and the ideal code width. This is 1/2 LSB in 8-bit, 10-bit, or 12-bit modes. If the first conversion is 0x001, the difference between the actual 0x001 code width and its ideal (1 LSB) is used.
Page 462: Freescale Semiconductor, Inc
Application information KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc.
Page 463: Introduction
Chapter 29 Comparator (CMP) 29.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The comparator (CMP) module provides a circuit for comparing two analog input voltages. The comparator circuit is designed to operate across the full range of the supply voltage, known as rail-to-rail operation.
Page 464: Bit Dac Key Features
6-bit DAC key features • Selectable interrupt on rising-edge, falling-edge, or both rising or falling edges of the comparator output • Selectable inversion on comparator output • Capability to produce a wide range of outputs such as: • Sampled • Windowed, which is ideal for certain PWM zero-crossing-detection applications •...
Page 465: Anmux Key Features
Chapter 29 Comparator (CMP) 29.4 ANMUX key features • Two 8-to-1 channel mux • Operational over the entire supply range 29.5 CMP, DAC and ANMUX diagram The following figure shows the block diagram for the High-Speed Comparator, DAC, and ANMUX modules. KL04 Sub-Family Reference Manual, Rev.
Page 466: Cmp Block Diagram
CMP block diagram VRSEL VOSEL[5:0] DACEN DAC output PSEL[2:0] Reference Input 0 Reference Input 1 Reference Input 2 Reference Input 3 Reference Input 4 Sample input Reference Input 5 Reference Input 6 Window ANMUX and filter control CMPO MSEL[2:0] Figure 29-1. CMP, DAC and ANMUX block diagram 29.6 CMP block diagram The following figure shows the block diagram for the CMP module.
Page 467: Freescale Semiconductor, Inc
Chapter 29 Comparator (CMP) Internal bus FILT_PER FILTER_CNT COUT IER/F CFR/F EN,PMODE,HYSCTRL[1:0] Window Interrupt Polarity Filter control select control block CMPO COUT To other SOC functions WINDOW/SAMPLE bus clock Clock COUTA CMPO to divided prescaler FILT_PER CGMUX clock Figure 29-2. Comparator module block diagram In the CMP block diagram: •...
Page 468: Memory Map/Register Definitions
Memory map/register definitions • If enabled, the Filter block will incur up to one bus clock additional latency penalty on COUT due to the fact that COUT, which is crossing clock domain boundaries, must be resynchronized to the bus clock. •...
Page 469: Cmp Control Register 1 (Cmpx_Cr1)
Chapter 29 Comparator (CMP) CMPx_CR0 field descriptions (continued) Field Description 5 consecutive samples must agree. 6 consecutive samples must agree. 7 consecutive samples must agree. This field is reserved. Reserved This read-only field is reserved and always has the value 0. This field is reserved.
Page 470: Freescale Semiconductor, Inc
Memory map/register definitions CMPx_CR1 field descriptions (continued) Field Description CMP Trigger mode depends on an external timer resource to periodically enable the CMP and 6-bit DAC in order to generate a triggered compare. Upon setting TRIGM, the CMP and DAC are placed in a standby state until an external timer resource trigger is received.
Page 471: Cmp Filter Period Register (Cmpx_Fpr)
Chapter 29 Comparator (CMP) 29.7.3 CMP Filter Period Register (CMPx_FPR) Address: 4007_3000h base + 2h offset = 4007_3002h Read FILT_PER Write Reset CMPx_FPR field descriptions Field Description 7–0 Filter Sample Period FILT_PER Specifies the sampling period, in bus clock cycles, of the comparator output filter, when CR1[SE]=0. Setting FILT_PER to 0x0 disables the filter.
Page 472: Dac Control Register (Cmpx_Daccr)
Memory map/register definitions CMPx_SCR field descriptions (continued) Field Description Interrupt is disabled. Interrupt is enabled. Comparator Interrupt Enable Falling Enables the CFF interrupt from the CMP. When this field is set, an interrupt will be asserted when CFF is set. Interrupt is disabled.
Page 473: Mux Control Register (Cmpx_Muxcr)
Chapter 29 Comparator (CMP) CMPx_DACCR field descriptions (continued) Field Description V is selected as resistor ladder network supply reference V. in1in V is selected as resistor ladder network supply reference V. in2in 5–0 DAC Output Voltage Select VOSEL Selects an output voltage from one of 64 distinct levels. /64) * (VOSEL[5:0] + 1) , so the DACO range is from V /64 to V DACO = (V...
Page 474: Functional Description
Functional description CMPx_MUXCR field descriptions (continued) Field Description 29.8 Functional description The CMP module can be used to compare two analog input voltages applied to INP and INM. CMPO is high when the non-inverting input is greater than the inverting input, and is low when the non-inverting input is less than the inverting input.
Page 475: Freescale Semiconductor, Inc
Chapter 29 Comparator (CMP) The comparator filter and sampling features can be combined as shown in the following table. Individual modes are discussed below. Table 29-15. Comparator sample/filter controls CR0[FILTER_C Mode # CR1[EN] CR1[WE] CR1[SE] FPR[FILT_PER] Operation Disabled See the Disabled mode (# Continuous Mode 0x00...
Page 476: Freescale Semiconductor, Inc
Functional description Note Filtering and sampling settings must be changed only after setting CR1[SE]=0 and CR0[FILTER_CNT]=0x00. This resets the filter to a known state. 29.8.1.1 Disabled mode (# 1) In Disabled mode, the analog comparator is non-functional and consumes no power. CMPO is 0 in this mode.
Page 477: Freescale Semiconductor, Inc
Chapter 29 Comparator (CMP) The analog comparator block is powered and active. CMPO may be optionally inverted, but is not subject to external sampling or filtering. Both window control and filter blocks are completely bypassed. SCR[COUT] is updated continuously. The path from comparator input pins to output pin is operating in combinational unclocked mode.
Page 478: Freescale Semiconductor, Inc
Functional description The only difference in operation between Sampled, Non-Filtered (# 3A) and Sampled, Non-Filtered (# 3B) is in how the clock to the filter block is derived. In #3A, the clock to filter block is externally derived while in #3B, the clock to filter block is internally derived.
Page 479: Freescale Semiconductor, Inc
Chapter 29 Comparator (CMP) Internal bus FILT_PER FILTER_CNT COUT IER/F CFR/F EN, PMODE, HYSTCTR[1:0] > 0x01 Polarity Interrupt Window Filter select control control block CMPO COUT To other SOC functions WINDOW/SAMPLE bus clock Clock COUTA CMPO to prescaler divided FILT_PER CGMUX clock SE=1...
Page 480: Freescale Semiconductor, Inc
Functional description Internal bus FILT_PER FILTER_CNT COUT IER/F CFR/F EN, PMODE,HYSTCTR[1:0 > 0x01 Polarity Filter Window Interrupt block select control control CMPO COUT To other SOC functions WINDOW/SAMPLE bus clock Clock COUTA CMPO to prescaler divided FILT_PER CGMUX clock SE=0 Figure 29-19.
Page 481: Freescale Semiconductor, Inc
Chapter 29 Comparator (CMP) WI NDOW Plus input Minus input CMPO COUTA Figure 29-20. Windowed mode operation Internal bus FILT_PER FILTER_CNT COUT IER/F CFR/F EN, PMODE,HYSCTR[1:0] 0x01 Interrupt Polarity Window Filter select control control block CMPO COUT To other SOC functions WINDOW/SAMPLE bus clock Clock...
Page 482: Freescale Semiconductor, Inc
Functional description When any windowed mode is active, COUTA is clocked by the bus clock whenever WINDOW = 1. The last latched value is held when WINDOW = 0. 29.8.1.6 Windowed/Resampled mode (# 6) The following figure uses the same input stimulus shown in Figure 29-20, and adds resampling of COUTA to generate COUT.
Page 483: Power Modes
Chapter 29 Comparator (CMP) 29.8.1.7 Windowed/Filtered mode (#7) This is the most complex mode of operation for the comparator block, as it uses both windowing and filtering features. It also has the highest latency of any of the modes. This can be approximated: up to 1 bus clock synchronization in the window function + ((CR0[FILTER_CNT] * FPR[FILT_PER]) + 1) * bus clock for the filter function.
Page 484: Startup And Operation
Functional description 29.8.2.2 Stop mode operation Depending on clock restrictions related to the MCU core or core peripherals, the MCU is brought out of stop when a compare event occurs and the corresponding interrupt is enabled. Similarly, if CR1[OPE] is enabled, the comparator output operates as in the normal operating mode and comparator output is placed onto the external pin.
Page 485: Kl04 Sub-Family Reference Manual, Rev. 3.1, November
Chapter 29 Comparator (CMP) 29.8.4 Low-pass filter The low-pass filter operates on the unfiltered and unsynchronized and optionally inverted comparator output COUTA and generates the filtered and synchronized output COUT. Both COUTA and COUT can be configured as module outputs and are used for different purposes within the system.
Page 486: Freescale Semiconductor, Inc
Functional description If CR1[SE]=1, the filter takes samples of COUTA on each positive transition of the sample input. The output state of the filter changes when all the consecutive CR0[FILTER_CNT] samples agree that the output value has changed. 29.8.4.2 Latency issues The value of FPR[FILT_PER] or SAMPLE period must be set such that the sampling period is just longer than the period of the expected noise.
Page 487: Cmp Interrupts
Chapter 29 Comparator (CMP) 1. T represents the intrinsic delay of the analog component plus the polarity select logic. T is the clock period of the SAMPLE external sample clock. T is the period of the bus clock. 29.9 CMP interrupts The CMP module is capable of generating an interrupt on either the rising- or falling- edge of the comparator output, or both.
Page 488: Digital-To-Analog Converter
Digital-to-analog converter system from STOP modes. After the data transfer has finished, system will go back to STOP modes. Refer to DMA chapters in the device reference manual for the asynchronous DMA function for details. 29.12 Digital-to-analog converter The following figure shows the block diagram of the DAC module. It contains a 64-tap resistor ladder network and a 64-to-1 multiplexer, which selects an output voltage from one of 64 distinct levels that outputs from DACO.
Page 489: Voltage Reference Source Select
Chapter 29 Comparator (CMP) 29.13.1 Voltage reference source select • V connects to the primary voltage source as supply reference of 64 tap resistor ladder • V connects to an alternate voltage source 29.14 DAC resets This module has a single reset input, corresponding to the chip-wide peripheral reset. 29.15 DAC clocks This module has a single clock input, the bus clock.
Page 490: Freescale Semiconductor, Inc
CMP Trigger Mode KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc.
Page 491: Introduction
Chapter 30 Timer/PWM Module (TPM) 30.1 Introduction The TPM (Timer/PWM Module) is a two to eight channel timer which supports input capture, output compare, and the generation of PWM signals to control electric motor and power management applications. The counter, compare and capture registers are clocked by an asynchronous clock that can remain enabled in low power modes.
Page 492: Modes Of Operation
Introduction • It can be a free-running counter or modulo counter • The counting can be up or up-down • Includes 6 channels that can be configured for input capture, output compare, or edge-aligned PWM mode • In input capture mode the capture can occur on rising edges, falling edges or both edges •...
Page 493: Tpm Signal Descriptions
Chapter 30 Timer/PWM Module (TPM) The following figure shows the TPM structure. The central component of the TPM is the 16-bit counter with programmable final value and its counting can be up or up-down. CMOD no clock selected (counter disable) module clock prescaler external clock...
Page 494: Tpm_Extclk — Tpm External Clock
Memory Map and Register Definition 30.2.1 TPM_EXTCLK — TPM External Clock The rising edge of the external input signal is used to increment the TPM counter if selected by CMOD[1:0] bits in the SC register. This input signal must be less than half of the TPM counter clock frequency.
Page 495: Freescale Semiconductor, Inc
Chapter 30 Timer/PWM Module (TPM) TPM memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4003_9000 Status and Control (TPM1_SC) 0000_0000h 30.3.1/496 4003_9004 Counter (TPM1_CNT) 0000_0000h 30.3.2/497 4003_9008 Modulo (TPM1_MOD) 0000_FFFFh 30.3.3/498 4003_900C Channel (n) Status and Control (TPM1_C0SC) 0000_0000h 30.3.4/499 4003_9010...
Page 496: Status And Control (Tpmx_Sc)
Memory Map and Register Definition 30.3.1 Status and Control (TPMx_SC) SC contains the overflow status flag and control bits used to configure the interrupt enable, module configuration and prescaler factor. These controls relate to all channels within this module. Address: Base address + 0h offset Reset TOIE CMOD...
Page 497: Counter (Tpmx_Cnt)
Chapter 30 Timer/PWM Module (TPM) TPMx_SC field descriptions (continued) Field Description LPTPM counter has not overflowed. LPTPM counter has overflowed. Timer Overflow Interrupt Enable TOIE Enables LPTPM overflow interrupts. Disable TOF interrupts. Use software polling or DMA request. Enable TOF interrupts. An interrupt is generated when TOF equals one. Center-aligned PWM Select CPWMS Selects CPWM mode.
Page 498: Modulo (Tpmx_Mod)
Memory Map and Register Definition Reading the CNT register adds two wait states to the register access due to synchronization delays. Address: Base address + 4h offset COUNT Reset TPMx_CNT field descriptions Field Description 31–16 This field is reserved. Reserved This read-only field is reserved and always has the value 0.
Page 499: Channel (N) Status And Control (Tpmx_Cnsc)
Chapter 30 Timer/PWM Module (TPM) 30.3.4 Channel (n) Status and Control (TPMx_CnSC) CnSC contains the channel-interrupt-status flag and control bits used to configure the interrupt enable, channel configuration, and pin function. When switching from one channel mode to a different channel mode, the channel must first be disabled and this must be acknowledged in the LPTPM counter clock domain.
Page 500: Freescale Semiconductor, Inc
Memory Map and Register Definition CHIE MSB MSA ELSB ELSA Reset TPMx_CnSC field descriptions Field Description 31–8 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Channel Flag Set by hardware when an event occurs on the channel. CHF is cleared by writing a 1 to the CHF bit. Writing a 0 to CHF has no effect.
Page 501: Channel (N) Value (Tpmx_Cnv)
Chapter 30 Timer/PWM Module (TPM) 30.3.5 Channel (n) Value (TPMx_CnV) These registers contain the captured LPTPM counter value for the input modes or the match value for the output modes. In input capture mode, any write to a CnV register is ignored. In compare modes, writing to a CnV register latches the value into a buffer.
Page 502: Freescale Semiconductor, Inc
Memory Map and Register Definition Address: Base address + 50h offset Reset Reset TPMx_STATUS field descriptions Field Description 31–9 This field is reserved. Reserved This read-only field is reserved and always has the value 0. Timer Overflow Flag See register description LPTPM counter has not overflowed.
Page 503: Configuration (Tpmx_Conf)
Chapter 30 Timer/PWM Module (TPM) TPMx_STATUS field descriptions (continued) Field Description Channel 2 Flag CH2F See the register description. No channel event has occurred. A channel event has occurred. Channel 1 Flag CH1F See the register description. No channel event has occurred. A channel event has occurred.
Page 504: Kl04 Sub-Family Reference Manual, Rev. 3.1, November
Memory Map and Register Definition TPMx_CONF field descriptions (continued) Field Description 27–24 Trigger Select TRGSEL Selects the input trigger to use for starting the counter and/or reloading the counter. This field should only be changed when the LPTPM counter is disabled. See Chip configuration section for available options. 23–19 This field is reserved.
Page 505: Functional Description
Chapter 30 Timer/PWM Module (TPM) TPMx_CONF field descriptions (continued) Field Description Configures the LPTPM behavior in debug mode. All other configurations are reserved. LPTPM counter is paused and does not increment during debug mode. Trigger inputs and input capture events are also ignored. LPTPM counter continues in debug mode.
Page 506: Prescaler
Functional Description The CMOD[1:0] bits may be read or written at any time. Disabling the TPM counter by writing zero to the CMOD[1:0] bits does not affect the TPM counter value or other registers, but must be acknowledged by the TPM counter clock domain before they read as zero.
Page 507: Freescale Semiconductor, Inc
Chapter 30 Timer/PWM Module (TPM) The value of zero is loaded into the TPM counter, and the counter increments until the value of MOD is reached, at which point the counter is reloaded with zero. The TPM period when using up counting is (MOD + 0x0001) × period of the TPM counter clock.
Page 508: Input Capture Mode
Functional Description MOD = 0x0004 Timer module counter TOF bit set TOF bit set TOF bit period of timer module counter clock period of counting = 2 x MOD x period of timer module counter clock Figure 30-61. Example of Up-Down Counting 30.4.3.3 Counter Reset Any write to CNT resets the TPM counter and the channel outputs to their initial values (except for channels in output compare mode).
Page 509: Output Compare Mode
Chapter 30 Timer/PWM Module (TPM) was rising edge selected? CHnIE channel (n) interrupt CHnF synchronizer rising edge channel (n) input edge detector timer module clock falling edge was falling edge selected? timer module counter Figure 30-62. Input capture mode The CHnF bit is set on the third rising edge of the counter clock after a valid edge occurs on the channel input.
Page 510: Freescale Semiconductor, Inc
Functional Description MOD = 0x0005 CnV = 0x0003 channel (n) counter channel (n) counter counter overflow match match overflow overflow previous value channel (n) output previous value CHnF bit TOF bit Figure 30-63. Example of the output compare mode when the match toggles the channel output MOD = 0x0005 CnV = 0x0003...
Page 511: Edge-Aligned Pwm (Epwm) Mode
Chapter 30 Timer/PWM Module (TPM) 30.4.6 Edge-Aligned PWM (EPWM) Mode The edge-aligned mode is selected when (CPWMS = 0), and (MSnB:MSnA = 1:0). The EPWM period is determined by (MOD + 0x0001) and the pulse width (duty cycle) is determined by CnV. The CHnF bit is set and the channel (n) interrupt is generated (if CHnIE = 1) at the channel (n) match (TPM counter = CnV), that is, at the end of the pulse width.
Page 512: Center-Aligned Pwm (Cpwm) Mode
Functional Description MOD = 0x0008 CnV = 0x0005 counter channel (n) counter overflow match overflow channel (n) output previous value CHnF bit TOF bit Figure 30-68. EPWM signal with ELSnB:ELSnA = X:1 If (CnV = 0x0000), then the channel (n) output is a 0% duty cycle EPWM signal. If (CnV >...
Page 513: Freescale Semiconductor, Inc
Chapter 30 Timer/PWM Module (TPM) timer module counter = 0 channel (n) match channel (n) match counter overflow counter overflow (timer module counting (timer module counting timer module counter = timer module counter = is down) is up) channel (n) output pulse width (2 x CnV) period...
Page 514: Registers Updated From Write Buffers
Functional Description If (CnV = 0x0000) then the channel (n) output is a 0% duty cycle CPWM signal. If (CnV > MOD), then the channel (n) output is a 100% duty cycle CPWM signal, although the CHnF bit is set when the counter changes from incrementing to decrementing.
Page 515: Reset Overview
Chapter 30 Timer/PWM Module (TPM) 30.4.9 DMA The channel generates a DMA transfer request according to DMA and CHnIE bits (see the following table). Table 30-83. Channel DMA Transfer Request CHnIE Channel DMA Transfer Request Channel Interrupt The channel DMA transfer request is not The channel interrupt is not generated.
Page 516: Freescale Semiconductor, Inc
Functional Description 30.4.11.1 Timer Overflow Interrupt The timer overflow interrupt is generated when (TOIE = 1) and (TOF = 1). 30.4.11.2 Channel (n) Interrupt The channel (n) interrupt is generated when (CHnIE = 1) and (CHnF = 1). KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc.
Page 517: Introduction
Chapter 31 Periodic Interrupt Timer (PIT-RTI) 31.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The PIT module is an array of timers that can be used to raise interrupts and trigger DMA channels.
Page 518: Features
Signal description Peripheral registers load_value Timer 1 I i nterrupts Triggers Timer n Peripheral bus clock Figure 31-1. Block diagram of the PIT NOTE See the chip configuration details for the number of PIT channels used in this MCU. 31.1.2 Features The main features of this block are: •...
Page 519: Memory Map/Register Description
Chapter 31 Periodic Interrupt Timer (PIT-RTI) 31.3 Memory map/register description This section provides a detailed description of all registers accessible in the PIT module. NOTE • Reserved registers will read as 0, writes will have no effect. • See the chip configuration details for the number of PIT channels used in this MCU. Table 31-2.
Page 520: Freescale Semiconductor, Inc
Memory map/register description Address: 4003_7000h base + 0h offset = 4003_7000h Reset MDIS Reset PIT_MCR field descriptions Field Description 0–28 This field is reserved. Reserved This read-only field is reserved and always has the value 0. This field is reserved. Reserved Module Disable - (PIT section) MDIS...
Page 521: Pit Upper Lifetime Timer Register (Pit_Ltmr64H)
Chapter 31 Periodic Interrupt Timer (PIT-RTI) 31.3.2 PIT Upper Lifetime Timer Register (PIT_LTMR64H) This register is intended for applications that chain timer 0 and timer 1 to build a 64-bit lifetimer. Address: 4003_7000h base + E0h offset = 4003_70E0h Reset PIT_LTMR64H field descriptions Field Description...
Page 522: Timer Load Value Register (Pit_Ldvaln)
Memory map/register description 31.3.4 Timer Load Value Register (PIT_LDVALn) These registers select the timeout period for the timer interrupts. Address: 4003_7000h base + 100h offset + (16d × i), where i=0d to 1d Reset PIT_LDVALn field descriptions Field Description 0–31 Timer Start Value Sets the timer start value.
Page 523: Timer Control Register (Pit_Tctrln)
Chapter 31 Periodic Interrupt Timer (PIT-RTI) 31.3.6 Timer Control Register (PIT_TCTRLn) These register contain the control bits for each timer. Address: 4003_7000h base + 108h offset + (16d × i), where i=0d to 1d Reset Reset PIT_TCTRLn field descriptions Field Description 0–28 This field is reserved.
Page 524: Timer Flag Register (Pit_Tflgn)
Functional description 31.3.7 Timer Flag Register (PIT_TFLGn) These registers hold the PIT interrupt flags. Address: 4003_7000h base + 10Ch offset + (16d × i), where i=0d to 1d Reset Reset PIT_TFLGn field descriptions Field Description 0–30 This field is reserved. Reserved This read-only field is reserved and always has the value 0.
Page 525: Freescale Semiconductor, Inc
Chapter 31 Periodic Interrupt Timer (PIT-RTI) 31.4.1.1 Timers The timers generate triggers at periodic intervals, when enabled. The timers load the start values as specified in their LDVAL registers, count down to 0 and then load the respective start value again. Each time a timer reaches 0, it will generate a trigger pulse and set the interrupt flag.
Page 526: Interrupts
Initialization and application information Timer enabled New start Value p2 set Start value = p1 Trigger event Figure 31-19. Dynamically setting a new load value 31.4.1.2 Debug mode In Debug mode, the timers will be frozen based on MCR[FRZ]. This is intended to aid software development, allowing the developer to halt the processor, investigate the current state of the system, for example, the timer values, and then continue the operation.
Page 527: Kl04 Sub-Family Reference Manual, Rev. 3.1, November
Chapter 31 Periodic Interrupt Timer (PIT-RTI) • Timer 1 creates an interrupt every 5.12 ms. • Timer 3 creates a trigger event every 30 ms. The PIT module must be activated by writing a 0 to MCR[MDIS]. The 50 MHz clock frequency equates to a clock period of 20 ns. Timer 1 needs to trigger every 5.12 ms/20 ns = 256,000 cycles and Timer 3 every 30 ms/20 ns = 1,500,000 cycles.
Page 528: Example Configuration For The Lifetime Timer
Example configuration for the lifetime timer The 100 MHz clock frequency equates to a clock period of 10 ns, so the PIT needs to count for 6000 million cycles, which is more than a single timer can do. So, Timer 1 is set up to trigger every 6 s (600 million cycles).
Page 529: Freescale Semiconductor, Inc
Chapter 31 Periodic Interrupt Timer (PIT-RTI) PIT_LDVAL0 = 0xFFFFFFFF; // setup timer 0 for maximum counting period PIT_TCTRL0 = TEN; // start timer 0 To access the lifetime, read first LTMR64H and then LTMR64L. current_uptime = PIT_LTMR64H<<32; current_uptime = current_uptime + PIT_LTMR64L; KL04 Sub-Family Reference Manual, Rev.
Page 530: Freescale Semiconductor, Inc
Example configuration for the lifetime timer KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc.
Page 531: Introduction
Chapter 32 Low-Power Timer (LPTMR) 32.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The low-power timer (LPTMR) can be configured to operate as a time counter with optional prescaler, or as a pulse counter with optional glitch filter, across all power modes, including the low-leakage modes.
Page 532: Lptmr Signal Descriptions
LPTMR signal descriptions Table 32-1. Modes of operation Modes Description The LPTMR operates normally. The LPTMR continues to operate normally and Wait may be configured to exit the low-power mode by generating an interrupt request. The LPTMR continues to operate normally and Stop may be configured to exit the low-power mode by generating an interrupt request.
Page 533: Low Power Timer Control Status Register (Lptmrx_Csr)
Chapter 32 Low-Power Timer (LPTMR) LPTMR memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4004_0000 Low Power Timer Control Status Register (LPTMR0_CSR) 0000_0000h 32.3.1/533 4004_0004 Low Power Timer Prescale Register (LPTMR0_PSR) 0000_0000h 32.3.2/534 4004_0008 Low Power Timer Compare Register (LPTMR0_CMR) 0000_0000h...
Page 534: Low Power Timer Prescale Register (Lptmrx_Psr)
Memory map and register definition LPTMRx_CSR field descriptions (continued) Field Description Pulse counter input 1 is selected. Pulse counter input 2 is selected. Pulse counter input 3 is selected. Timer Pin Polarity Configures the polarity of the input source in Pulse Counter mode. TPP must be changed only when the LPTMR is disabled.
Page 535: Freescale Semiconductor, Inc
Chapter 32 Low-Power Timer (LPTMR) LPTMRx_PSR field descriptions Field Description 31–7 This field is reserved. Reserved This read-only field is reserved and always has the value 0. 6–3 Prescale Value PRESCALE Configures the size of the Prescaler in Time Counter mode or width of the glitch filter in Pulse Counter mode.
Page 536: Low Power Timer Compare Register (Lptmrx_Cmr)
Memory map and register definition LPTMRx_PSR field descriptions (continued) Field Description Prescaler/glitch filter clock 0 selected. Prescaler/glitch filter clock 1 selected. Prescaler/glitch filter clock 2 selected. Prescaler/glitch filter clock 3 selected. 32.3.3 Low Power Timer Compare Register (LPTMRx_CMR) Address: 4004_0000h base + 8h offset = 4004_0008h COMPARE Reset LPTMRx_CMR field descriptions...
Page 537: Functional Description
Chapter 32 Low-Power Timer (LPTMR) 32.4 Functional description 32.4.1 LPTMR power and reset The LPTMR remains powered in all power modes, including low-leakage modes. If the LPTMR is not required to remain operating during a low-power mode, then it must be disabled before entering the mode.
Page 538: Freescale Semiconductor, Inc
Functional description NOTE The prescaler/glitch filter configuration must not be altered when the LPTMR is enabled. 32.4.3.1 Prescaler enabled In Time Counter mode, when the prescaler is enabled, the output of the prescaler directly clocks the CNR. When the LPTMR is enabled, the CNR will increment every 2 to 2 prescaler clock cycles.
Page 539: Lptmr Compare
Chapter 32 Low-Power Timer (LPTMR) 32.4.3.4 Glitch filter bypassed In Pulse Counter mode, when the glitch filter is bypassed, the selected input source increments the CNR every time it asserts. Before the LPTMR is first enabled, the selected input source is forced to be asserted. This prevents the CNR from incrementing if the selected input source is already asserted when the LPTMR is first enabled.
Page 540: Lptmr Hardware Trigger
Functional description 32.4.6 LPTMR hardware trigger The LPTMR hardware trigger asserts at the same time the CSR[TCF] is set and can be used to trigger hardware events in other peripherals without software intervention. The hardware trigger is always enabled. When Then The CMR is set to 0 with CSR[TFC] clear The LPTMR hardware trigger will assert on the first compare...
Page 541: Introduction
Chapter 33 Real Time Clock (RTC) 33.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. 33.1.1 Features The RTC module features include: • 32-bit seconds counter with roll-over protection and 32-bit alarm •...
Page 542: Kl04 Sub-Family Reference Manual, Rev. 3.1, November
Register definition 33.1.3 RTC Signal Descriptions Table 33-1. RTC signal descriptions Signal Description RTC_CLKOUT 1 Hz square-wave output 33.1.3.1 RTC clock output The clock to the seconds counter is available on the RTC_CLKOUT signal. It is a 1 Hz square wave output. 33.2 Register definition All registers must be accessed using 32-bit writes and all register accesses incur three wait states.
Page 543: Rtc Time Seconds Register (Rtc_Tsr)
Chapter 33 Real Time Clock (RTC) 33.2.1 RTC Time Seconds Register (RTC_TSR) Address: 4003_D000h base + 0h offset = 4003_D000h Reset RTC_TSR field descriptions Field Description 31–0 Time Seconds Register When the time counter is enabled, the TSR is read only and increments once a second provided SR[TOF] or SR[TIF] are not set.
Page 544: Rtc Time Alarm Register (Rtc_Tar)
Register definition 33.2.3 RTC Time Alarm Register (RTC_TAR) Address: 4003_D000h base + 8h offset = 4003_D008h Reset RTC_TAR field descriptions Field Description 31–0 Time Alarm Register When the time counter is enabled, the SR[TAF] is set whenever the TAR[TAR] equals the TSR[TSR] and the TSR[TSR] increments.
Page 545: Rtc Control Register (Rtc_Cr)
Chapter 33 Real Time Clock (RTC) RTC_TCR field descriptions (continued) Field Description Time Prescaler Register overflows every 32896 clock cycles. Time Prescaler Register overflows every 32769 clock cycles. Time Prescaler Register overflows every 32768 clock cycles. Time Prescaler Register overflows every 32767 clock cycles. Time Prescaler Register overflows every 32641 clock cycles.
Page 546: Freescale Semiconductor, Inc
Register definition RTC_CR field descriptions (continued) Field Description This field is reserved. Reserved It must always be written to 0. Oscillator 2pF Load Configure SC2P Disable the load. Enable the additional load. Oscillator 4pF Load Configure SC4P Disable the load. Enable the additional load.
Page 547: Rtc Status Register (Rtc_Sr)
Chapter 33 Real Time Clock (RTC) RTC_CR field descriptions (continued) Field Description No effect. Resets all RTC registers except for the SWR bit . The SWR bit is cleared by POR and by software explicitly clearing it. 33.2.6 RTC Status Register (RTC_SR) Address: 4003_D000h base + 14h offset = 4003_D014h Reset Reset...
Page 548: Rtc Lock Register (Rtc_Lr)
Register definition RTC_SR field descriptions (continued) Field Description Time Invalid Flag The time invalid flag is set on POR or software reset. The TSR and TPR do not increment and read as zero when this bit is set. This bit is cleared by writing the TSR register when the time counter is disabled. Time is valid.
Page 549: Rtc Interrupt Enable Register (Rtc_Ier)
Chapter 33 Real Time Clock (RTC) RTC_LR field descriptions (continued) Field Description Time Compensation Lock After being cleared, this bit can be set only by POR or software reset. Time Compensation Register is locked and writes are ignored. Time Compensation Register is not locked and writes complete as normal. 2–0 This field is reserved.
Page 550: Functional Description
Functional description RTC_IER field descriptions (continued) Field Description Seconds interrupt is disabled. Seconds interrupt is enabled. This field is reserved. Reserved Time Alarm Interrupt Enable TAIE Time alarm flag does not generate an interrupt. Time alarm flag does generate an interrupt. Time Overflow Interrupt Enable TOIE Time overflow flag does not generate an interrupt.
Page 551: Time Counter
Chapter 33 Real Time Clock (RTC) 33.3.1.2 Software reset Writing one to the CR[SWR] forces the equivalent of a POR to the rest of the RTC module. The CR[SWR] is not affected by the software reset and must be cleared by software.
Page 552: Time Alarm
Functional description register. The RTC itself does not calculate the amount of compensation that is required, although the 1 Hz clock is output to an external pin in support of external calibration logic. Crystal compensation can be supported by using firmware and crystal characteristics to determine the compensation amount.
Page 553: Update Mode
Chapter 33 Real Time Clock (RTC) 33.3.5 Update mode The Update Mode bit in the Control register (CR[UM]) configures software write access to the Time Counter Enable (SR[TCE]) bit. When CR[UM] is clear, SR[TCE] can be written only when the LR[SRL] bit is set. When CR[UM] is set, the SR[TCE] can also be written when SR[TCE] is clear or when SR[TIF] or SR[TOF] are set.
Page 554: Freescale Semiconductor, Inc
Functional description KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc.
Page 555: Introduction
Chapter 34 Serial Peripheral Interface (SPI) 34.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The serial peripheral interface (SPI) module provides for full-duplex, synchronous, serial communication between the MCU and peripheral devices. These peripheral devices can include other microcontrollers, analog-to-digital converters, shift registers, sensors, and memories, among others.
Page 556: Modes Of Operation
Introduction • Programmable transmit bit rate • Double-buffered transmit and receive data register • Serial clock phase and polarity options • Slave select output • Mode fault error flag with CPU interrupt capability • Control of SPI operation during wait mode •...
Page 557: Block Diagrams
Chapter 34 Serial Peripheral Interface (SPI) The SPI is completely disabled in stop modes where the peripheral bus clock is stopped and internal logic states are not retained. When the CPU wakes from these stop modes, all SPI register content is reset. Detailed descriptions of operating modes appear in Low Power Mode Options.
Page 558: Freescale Semiconductor, Inc
Introduction 34.1.3.2 SPI Module Block Diagram The following is a block diagram of the SPI module. The central element of the SPI is the SPI shift register. Data is written to the double-buffered transmitter (write to SPIx_D) and gets transferred to the SPI shift register at the start of a data transfer. After shifting in 8 bits of data, the data is transferred into the double-buffered receiver where it can be read from SPIx_D.
Page 559: External Signal Description
Chapter 34 Serial Peripheral Interface (SPI) PIN CONTROL MOSI (MOMI) Tx BUFFER (WRITE SPIxD) ENABLE MISO SPI SYSTEM (SISO) SPI SHIFT REGISTER SHIFT SHIFT Rx BUFFER (READ SPIxD) SPC0 BIDIROE SHIFT SHIFT Rx BUFFER Tx BUFFER LSBFE DIRECTION CLOCK FULL EMPTY MASTER CLOCK BUS RATE...
Page 560: Spsck — Spi Serial Clock
External Signal Description 34.2.1 SPSCK — SPI Serial Clock When the SPI is enabled as a slave, this pin is the serial clock input. When the SPI is enabled as a master, this pin is the serial clock output. 34.2.2 MOSI — Master Data Out, Slave Data In When the SPI is enabled as a master and SPI pin control zero (SPC0) is 0 (not bidirectional mode), this pin is the serial data output.
Page 561: Kl04 Sub-Family Reference Manual, Rev. 3.1, November
Chapter 34 Serial Peripheral Interface (SPI) 34.3 Memory Map and Register Descriptions The SPI has 8-bit registers to select SPI options, to control baud rate, to report SPI status, to hold an SPI data match value, and for transmit/receive data. SPI memory map Absolute Address...
Page 562: Freescale Semiconductor, Inc
Memory Map and Register Descriptions SPI0_C1 field descriptions (continued) Field Description SPI system inactive SPI system enabled SPI transmit interrupt enable SPTIE This is the interrupt enable bit for SPI transmit buffer empty (SPTEF). An interrupt occurs when the SPI transmit buffer is empty (SPTEF is set).
Page 563: Spi Control Register 2 (Spix_C2)
Chapter 34 Serial Peripheral Interface (SPI) 34.3.2 SPI control register 2 (SPIx_C2) This read/write register is used to control optional features of the SPI system. Bit 6 is not implemented and always reads 0. Address: 4007_6000h base + 1h offset = 4007_6001h Read SPMIE Reserved...
Page 564: Spi Baud Rate Register (Spix_Br)
Memory Map and Register Descriptions SPI0_C2 field descriptions (continued) Field Description DMA request for receive is disabled and interrupt from SPRF is allowed DMA request for receive is enabled and interrupt from SPRF is disabled SPI stop in wait mode SPISWAI This bit is used for power conservation while the device is in wait mode.
Page 565: Spi Status Register (Spix_S)
Chapter 34 Serial Peripheral Interface (SPI) SPI0_BR field descriptions (continued) Field Description Baud rate prescaler divisor is 2 Baud rate prescaler divisor is 3 Baud rate prescaler divisor is 4 Baud rate prescaler divisor is 5 Baud rate prescaler divisor is 6 Baud rate prescaler divisor is 7 Baud rate prescaler divisor is 8 3–0...
Page 566: Spi Data Register (Spix_D)
Memory Map and Register Descriptions SPI0_S field descriptions (continued) Field Description No data available in the receive data buffer Data available in the receive data buffer SPI match flag SPMF SPMF is set after SPRF is 1 when the value in the receive data buffer matches the value in the M register. To clear the flag, read SPMF when it is set and then write a 1 to it.
Page 567: Spi Match Register (Spix_M)
Chapter 34 Serial Peripheral Interface (SPI) The SPTEF bit in the S register indicates when the transmit data buffer is ready to accept new data. When the transmit DMA request is disabled (TXDMAE is 0): The S register must be read when SPTEF is set before writing to the SPI data register; otherwise, the write is ignored.
Page 568: Functional Description
Functional Description 34.4 Functional Description This section provides the functional description of the module. 34.4.1 General The SPI system is enabled by setting the SPI enable (SPE) bit in SPI Control Register 1. While the SPE bit is set, the four associated SPI port pins are dedicated to the SPI function as: •...
Page 569: Freescale Semiconductor, Inc
Chapter 34 Serial Peripheral Interface (SPI) • SPSCK • The SPR3, SPR2, SPR1, and SPR0 baud rate selection bits in conjunction with the SPPR2, SPPR1, and SPPR0 baud rate preselection bits in the SPI Baud Rate register control the baud rate generator and determine the speed of the transmission.
Page 570: Slave Mode
Functional Description 34.4.3 Slave Mode The SPI operates in slave mode when the MSTR bit in SPI Control Register1 is clear. • SPSCK In slave mode, SPSCK is the SPI clock input from the master. • MISO, MOSI pin In slave mode, the function of the serial data output pin (MISO) and serial data input pin (MOSI) is determined by the SPC0 bit and BIDIROE bit in SPI Control Register •...
Page 571: Spi Transmission By Dma
Chapter 34 Serial Peripheral Interface (SPI) If the CPHA bit is set, even numbered edges on the SPSCK input cause the data at the serial data input pin to be latched. Odd numbered edges cause the value previously latched from the serial data input pin to shift into the LSB or MSB of the SPI shift register, depending on the LSBFE bit.
Page 572: Freescale Semiconductor, Inc
Functional Description 34.4.4.1 Transmit by DMA Transmit by DMA is supported only when TXDMAE is set. A transmit DMA request is asserted when both SPE and SPTEF are set. Then the on-chip DMA controller detects this request and transfers data from memory into the SPI data register. After that, TX DMA DONE is asserted to clear SPTEF automatically.
Page 573: Spi Clock Formats
Chapter 34 Serial Peripheral Interface (SPI) 34.4.4.2 Receive by DMA Receive by DMA is supported only when RXDMAE is set. A receive DMA request is asserted when both SPE and SPRF are set. Then the on-chip DMA controller detects this request and transfers data from the SPI data register into memory.
Page 574: Freescale Semiconductor, Inc
Functional Description BIT TIME # (REFERENCE) SPSCK (CPOL = 0) SPSCK (CPOL = 1) SAMPLE IN (MISO OR MOSI) MOSI (MASTER OUT) MSB FIRST BIT 7 BIT 6 BIT 2 BIT 1 BIT 0 LSB FIRST BIT 0 BIT 1 BIT 5 BIT 6 BIT 7...
Page 575: Freescale Semiconductor, Inc
Chapter 34 Serial Peripheral Interface (SPI) Between these two successive transmissions, no pause is inserted; the SS pin remains low. The following figure shows the clock formats when CPHA = 0. At the top of the figure, the eight bit times are shown for reference with bit 1 starting as the slave is selected (SS IN goes low), and bit 8 ends at the last SPSCK edge.
Page 576: Spi Baud Rate Generation
Functional Description When CPHA = 0, the slave begins to drive its MISO output with the first data bit value (MSB or LSB depending on LSBFE) when SS goes to active low. The first SPSCK edge causes both the master and the slave to sample the data bit values on their MISO and MOSI inputs, respectively.
Page 577: Freescale Semiconductor, Inc
Chapter 34 Serial Peripheral Interface (SPI) 34.4.7.1 SS Output The SS output feature automatically drives the SS pin low during transmission to select external devices and drives the SS pin high during idle to deselect external devices. When the SS output is selected, the SS output pin is connected to the SS input pin of the external device.
Page 578: Error Conditions
Functional Description SS is the input or output for the master mode, and it is always the input for the slave mode. The bidirectional mode does not affect SPSCK and SS functions. Note In bidirectional master mode, with the mode fault feature enabled, both data pins MISO and MOSI can be occupied by the SPI, though MOSI is normally used for transmissions in bidirectional mode and MISO is not used by the SPI.
Page 579: Low Power Mode Options
Chapter 34 Serial Peripheral Interface (SPI) The mode fault flag is cleared automatically by a read of the SPI Status Register (with MODF set) followed by a write to SPI Control Register 1. If the mode fault flag is cleared, the SPI becomes a normal master or slave again. 34.4.9 Low Power Mode Options This section describes the low power mode options.
Page 580: Reset
Functional Description Note Care must be taken when expecting data from a master while the slave is in a wait mode or a stop mode where the peripheral bus clock is stopped but internal logic states are retained. Even though the shift register continues to operate, the rest of the SPI is shut down (that is, an SPRF interrupt is not generated until an exit from stop or wait mode).
Page 581: Interrupts
Chapter 34 Serial Peripheral Interface (SPI) 34.4.11 Interrupts The SPI originates interrupt requests only when the SPI is enabled (the SPE bit in the SPIx_C1 register is set). The following is a description of how the SPI makes a request and how the MCU should acknowledge that request.
Page 582: Initialization/Application Information
Initialization/Application Information 34.4.11.3 SPTEF SPTEF occurs when the SPI transmit buffer is ready to accept new data. After SPTEF is set, it does not clear until it is serviced. SPTEF has an automatic clearing process that is described in the SPI Status Register details. 34.4.11.4 SPMF SPMF occurs when the data in the receive data buffer is equal to the data in the SPI match register.
Page 583: Pseudo-Code Example
Chapter 34 Serial Peripheral Interface (SPI) 1. Update control register 1 (SPIx_C1) to enable the SPI and to control interrupt enables. This register also sets the SPI as master or slave, determines clock phase and polarity, and configures the main SPI options. 2.
Page 584: Freescale Semiconductor, Inc
Initialization/Application Information SPIx_C2 = 0x80(%10000000) Bit 2 RXDMAE DMA request disabled Bit 1 SPISWAI SPI clocks operate in wait mode Bit 0 SPC0 uses separate pins for data input and output SPIx_BR = 0x00(%00000000) Bit 7 Reserved Bit 6:4 Sets prescale divisor to 1 Bit 3:0 0000 Sets baud rate divisor to 2 SPIx_S = 0x00(%00000000)
Page 585: Freescale Semiconductor, Inc
Chapter 34 Serial Peripheral Interface (SPI) RESET INITIALIZE SPI SPIxC1 = 0x54 0x80 SPIxC2 = SPIxBR = 0x00 SPTEF = 1 WRITE TO SPIxD SPRF = 1 READ SPIxD SPMF = 1 READ SPMF WHILE SET TO CLEAR FLAG, THEN WRITE A 1 TO IT CONTINUE Figure 34-20.
Page 586: Freescale Semiconductor, Inc
Initialization/Application Information KL04 Sub-Family Reference Manual, Rev. 3.1, November 2012 Freescale Semiconductor, Inc.
Page 587: Introduction
Chapter 35 Inter-Integrated Circuit (I2C) 35.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The inter-integrated circuit (I C, I2C, or IIC) module provides a method of communication between a number of devices. The interface is designed to operate up to 100 kbit/s with maximum bus loading and timing.
Page 588: Modes Of Operation
Introduction • 10-bit address extension • Support for System Management Bus (SMBus) Specification, version 2 • Programmable glitch input filter • Low power mode wakeup on slave address match • Range slave address support • DMA support 35.1.2 Modes of operation The I2C module's operation in various low power modes is as follows: •...
Page 589: Kl04 Sub-Family Reference Manual, Rev. 3.1, November
Chapter 35 Inter-Integrated Circuit (I2C) Module Enable Address Write/Read Interrupt ADDR_DECODE DATA_MUX CTRL_REG FREQ_REG ADDR_REG STATUS_REG DATA_REG Input Sync In/Out START Data STOP Shift Arbitration Register Control Clock Address Control Compare Figure 35-1. I2C Functional block diagram 35.2 I C signal descriptions The signal properties of I C are shown in the following table.
Page 590: I2C Address Register 1 (I2Cx_A1)
Memory map and register descriptions I2C memory map Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 4006_6000 I2C Address Register 1 (I2C0_A1) 35.3.1/590 4006_6001 I2C Frequency Divider register (I2C0_F) 35.3.2/591 4006_6002 I2C Control Register 1 (I2C0_C1) 35.3.3/592 4006_6003 I2C Status register (I2C0_S)
Page 591: I2C Frequency Divider Register (I2Cx_F)
Chapter 35 Inter-Integrated Circuit (I2C) 35.3.2 I2C Frequency Divider register (I2Cx_F) Address: 4006_6000h base + 1h offset = 4006_6001h Read MULT Write Reset I2Cx_F field descriptions Field Description 7–6 The MULT bits define the multiplier factor mul. This factor is used along with the SCL divider to generate MULT the I2C baud rate.
Page 592: I2C Control Register 1 (I2Cx_C1)
Memory map and register descriptions 35.3.3 I2C Control Register 1 (I2Cx_C1) Address: 4006_6000h base + 2h offset = 4006_6002h Read IICEN IICIE TXAK WUEN DMAEN Write RSTA Reset I2Cx_C1 field descriptions Field Description I2C Enable IICEN Enables I2C module operation. Disabled Enabled I2C Interrupt Enable...
Page 593: I2C Status Register (I2Cx_S)
Chapter 35 Inter-Integrated Circuit (I2C) I2Cx_C1 field descriptions (continued) Field Description Repeat START RSTA Writing a one to this bit generates a repeated START condition provided it is the current master. This bit will always be read as zero. Attempting a repeat at the wrong time results in loss of arbitration. Wakeup Enable WUEN The I2C module can wake the MCU from low power mode with no peripheral bus running when slave...
Page 594: Freescale Semiconductor, Inc
Memory map and register descriptions I2Cx_S field descriptions (continued) Field Description Addressed As A Slave IAAS This bit is set by one of the following conditions: • The calling address matches the programmed slave primary address in the A1 register or range address in the RA register (which must be set to a nonzero value).
Page 595: I2C Data I/O Register (I2Cx_D)
Chapter 35 Inter-Integrated Circuit (I2C) I2Cx_S field descriptions (continued) Field Description • One byte transfer, including ACK/NACK bit, completes if FACK is 0. An ACK or NACK is sent on the bus by writing 0 or 1 to TXAK after this bit is set in receive mode. •...
Page 596: I2C Control Register 2 (I2Cx_C2)
Memory map and register descriptions I2Cx_D field descriptions (continued) Field Description In master transmit mode, the first byte of data written to the Data register following assertion of MST (start bit) or assertion of RSTA (repeated start bit) is used for the address transfer and must consist of the calling address (in bits 7-1) concatenated with the required R/W bit (in position bit 0).
Page 597: I2C Programmable Input Glitch Filter Register (I2Cx_Flt)
Chapter 35 Inter-Integrated Circuit (I2C) I2Cx_C2 field descriptions (continued) Field Description Range mode disabled. No address match occurs for an address within the range of values of the A1 and RA registers. Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers.
Page 598: I2C Range Address Register (I2Cx_Ra)
Memory map and register descriptions I2Cx_FLT field descriptions (continued) Field Description Hardware sets this bit when the I2C bus's stop status is detected. The STOPF bit must be cleared by writing 1 to it. No stop happens on I2C bus Stop detected on I2C bus I2C Bus Stop Interrupt Enable STOPIE...
Page 599: I2C Smbus Control And Status Register (I2Cx_Smb)
Chapter 35 Inter-Integrated Circuit (I2C) 35.3.9 I2C SMBus Control and Status register (I2Cx_SMB) NOTE When the SCL and SDA signals are held high for a length of time greater than the high timeout period, the SHTF1 flag sets. Before reaching this threshold, while the system is detecting how long these signals are being held high, a master assumes that the bus is free.
Page 600: I2C Address Register 2 (I2Cx_A2)
Memory map and register descriptions I2Cx_SMB field descriptions (continued) Field Description Timeout Counter Clock Select TCKSEL Selects the clock source of the timeout counter. Timeout counter counts at the frequency of the bus clock / 64 Timeout counter counts at the frequency of the bus clock SCL Low Timeout Flag SLTF This bit is set when the SLT register (consisting of the SLTH and SLTL registers) is loaded with a non-zero...
Page 601: I2C Scl Low Timeout Register High (I2Cx_Slth)
Chapter 35 Inter-Integrated Circuit (I2C) I2Cx_A2 field descriptions (continued) Field Description Contains the slave address used by the SMBus. This field is used on the device default address or other related addresses. This field is reserved. Reserved This read-only field is reserved and always has the value 0. 35.3.11 I2C SCL Low Timeout Register High (I2Cx_SLTH) Address: 4006_6000h base + Ah offset = 4006_600Ah Read...
Page 602: I2C Protocol
Functional description 35.4.1 I2C protocol The I2C bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfers. All devices connected to it must have open drain or open collector outputs. A logic AND function is exercised on both lines with external pull-up resistors. The value of these resistors depends on the system.
Page 603: Freescale Semiconductor, Inc
Chapter 35 Inter-Integrated Circuit (I2C) 35.4.1.2 Slave address transmission Immediately after the START signal, the first byte of a data transfer is the slave address transmitted by the master. This address is a 7-bit calling address followed by an R/W bit. The R/W bit tells the slave the desired direction of data transfer.
Page 604: Freescale Semiconductor, Inc
Functional description • Relinquishes the bus by generating a STOP signal. • Commences a new call by generating a repeated START signal. 35.4.1.4 STOP signal The master can terminate the communication by generating a STOP signal to free the bus. A STOP signal is defined as a low-to-high transition of SDA while SCL is asserted. The master can generate a STOP signal even if the slave has generated an acknowledgement, at which point the slave must release the bus.
Page 605: Freescale Semiconductor, Inc
Chapter 35 Inter-Integrated Circuit (I2C) 35.4.1.7 Clock synchronization Because wire AND logic is performed on SCL, a high-to-low transition on SCL affects all devices connected on the bus. The devices start counting their low period and, after a device's clock has gone low, that device holds SCL low until the clock reaches its high state.
Page 606: Freescale Semiconductor, Inc
Functional description low period, the resulting SCL bus signal's low period is stretched. In other words, the SCL bus signal's low period is increased to be the same length as the slave's SCL low period. 35.4.1.10 I2C divider and hold values NOTE For some cases on some devices, the SCL divider value may vary by +/-2 or +/-4 when ICR’s value ranges from 00h to 0Fh.
Page 607: Bit Address
Chapter 35 Inter-Integrated Circuit (I2C) Table 35-28. I2C divider and hold values (continued) SDA hold SCL hold SCL hold SDA hold SCL hold SCL hold divider value (start) (stop) divider (clocks) (start) (stop) (hex) (hex) value value (clocks) value value 1280 1536 1792...
Page 608: Address Matching
Functional description After the master-transmitter has sent the first byte of the 10-bit address, the slave-receiver sees an I2C interrupt. User software must ensure that for this interrupt, the contents of the Data register are ignored and not treated as valid data. 35.4.2.2 Master-receiver addresses a slave-transmitter The transfer direction is changed after the second R/W bit.
Page 609: System Management Bus Specification
Chapter 35 Inter-Integrated Circuit (I2C) Additional conditions that affect address matching include: • If the GCAEN bit is set, general call participates the address matching process. • If the ALERTEN bit is set, alert response participates the address matching process. •...
Page 610: Freescale Semiconductor, Inc
Functional description 35.4.4.1.1 SCL low timeout If the SCL line is held low by a slave device on the bus, no further communication is possible. Furthermore, the master cannot force the SCL line high to correct the error condition. To solve this problem, the SMBus protocol specifies that devices participating in a transfer must detect any clock cycle held low longer than a timeout value condition.
Page 611: Freescale Semiconductor, Inc
Chapter 35 Inter-Integrated Circuit (I2C) Stop Start LOW:SEXT ClkAck ClkAck LOW:MEXT LOW:MEXT LOW:MEXT Figure 35-28. Timeout measurement intervals A master is allowed to abort the transaction in progress to any slave that violates the or T specifications. To abort the transaction, the master issues a LOW:SEXT TIMEOUT,MIN STOP condition at the conclusion of the byte transfer in progress.
Page 612: Resets
Functional description have the ability to generate the not acknowledge after the transfer of each byte and before the completion of the transaction. This requirement is important because SMBus does not provide any other resend signaling. This difference in the use of the NACK signaling has implications on the specific implementation of the SMBus port, especially in devices that handle critical system data such as the SMBus host and the SBS components.
Page 613: Freescale Semiconductor, Inc
Chapter 35 Inter-Integrated Circuit (I2C) 35.4.6.1 Byte transfer interrupt The Transfer Complete Flag (TCF) bit is set at the falling edge of the ninth clock to indicate the completion of a byte and acknowledgement transfer. When FACK is enabled, TCF is then set at the falling edge of eighth clock to indicate the completion of byte. 35.4.6.2 Address detect interrupt When the calling address matches the programmed slave address (I2C Address Register) or when the GCAEN bit is set and a general call is received, the IAAS bit in the Status...
Page 614: Programmable Input Glitch Filter
Functional description 2. SDA is sampled as low when the master drives high during the acknowledge bit of a data receive cycle. 3. A START cycle is attempted when the bus is busy. 4. A repeated START cycle is requested in slave mode. 5.
Page 615: Address Matching Wakeup
Chapter 35 Inter-Integrated Circuit (I2C) 35.4.8 Address matching wakeup When a primary, range, or general call address match occurs when the I2C module is in slave receive mode, the MCU wakes from a low power mode with no peripheral bus running.
Page 616: Initialization/Application Information
Initialization/application information NOTE In 10-bit address mode transmission, the addresses to send occupy 2-3 bytes. During this transfer period, the DMA must be disabled because the C1 register is written to send a repeat start or to change the transfer direction. 35.5 Initialization/application information Module Initialization (Slave) 1.
Page 617: Freescale Semiconductor, Inc
Chapter 35 Inter-Integrated Circuit (I2C) Clear IICIF Master mode? Arbitration Tx/Rx? lost? Last byte Clear ARBL transmitted? Last byte RXAK=0? IIAAS=1? IIAAS=1? to be read? Data transfer see note 2 Address transfer see note 1 End of 2nd to (read) address cycle last byte to be SRW=1?
Page 618: Freescale Semiconductor, Inc
Initialization/application information See typical I2C SLTF or FACK=1? interrupt routine SHTF2=1? flow chart Clear IICIF Master mode? Arbitration Tx/Rx? lost? Last byte Last byte Clear ARBL transmitted? to be read? 2nd to RXAK=0? last byte to be IAAS=1? IAAS=1? read? Address transfer see note 1 Delay (note 2)
Page 619: Introduction
Chapter 36 Universal Asynchronous Receiver/Transmitter (UART0) 36.1 Introduction 36.1.1 Features Features of the UART module include: • Full-duplex, standard non-return-to-zero (NRZ) format • Double-buffered transmitter and receiver with separate enables • Programmable baud rates (13-bit modulo divider) • Transmit and receive baud rate can operate asynchronous to the bus clock: •...
Page 620: Kl04 Sub-Family Reference Manual, Rev. 3.1, November
Introduction 36.1.2 Modes of operation 36.1.2.1 Stop mode The UART will remain functional during Stop mode, provided the asynchronous transmit and receive clock remains enabled. The UART can generate an interrupt or DMA request to cause a wakeup from Stop mode. 36.1.2.2 Wait mode The UART can be configured to Stop in Wait modes, when the DOZEEN bit is set.
Page 621: Freescale Semiconductor, Inc
Chapter 36 Universal Asynchronous Receiver/Transmitter (UART0) Internal Bus (Write-Only) LOOPS ASYNCH UART_D – Tx Buffer MODULE RSRC CLOCK Loop To Receive 11-BIT Transmit Shift Register Control BAUD Data In Divider To TxD Pin Divider SHIFT DIRECTION TXINV Parity Generation UART Controls TxD TO TxD Transmit Control Pin Logic...
Page 622: Register Definition
Register definition INTERNAL BUS SBR12:0 DATA BUFFER ASYNCH BAUDRATE MODULE VARIABLE 12-BIT RECEIVE CLOCK GENERATOR SHIFT REGISTER LBKDE RECEIVE MSBF CONTROL RXINV SHIFT DIRECTION LOOPS RECEIVER RSRC SOURCE CONTROL PARITY WAKEUP LOGIC LOGIC From Transmitter DMA Requests IRQ / DMA ACTIVE EDGE LOGIC IRQ Requests...
Page 623: Uart Baud Rate Register High (Uartx_Bdh)
Chapter 36 Universal Asynchronous Receiver/Transmitter (UART0) UART memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 36.2.10/ 4006_A009 UART Match Address Registers 2 (UART0_MA2) 36.2.11/ 4006_A00A UART Control Register 4 (UART0_C4) 36.2.12/ 4006_A00B UART Control Register 5 (UART0_C5) 36.2.1 UART Baud Rate Register High (UARTx_BDH) This register, along with UART _BDL, controls the prescale divisor for UART baud rate generation.
Page 624: Uart Baud Rate Register Low (Uartx_Bdl)
Register definition 36.2.2 UART Baud Rate Register Low (UARTx_BDL) This register, along with UART _BDH, control the prescale divisor for UART baud rate generation. The 13-bit baud rate setting [SBR12:SBR0] can only be updated when the transmitter and receiver are both disabled. UART _BDL is reset to a non-zero value, so after reset the baud rate generator remains disabled until the first time the receiver or transmitter is enabled;...
Page 625: Freescale Semiconductor, Inc
Chapter 36 Universal Asynchronous Receiver/Transmitter (UART0) UARTx_C1 field descriptions (continued) Field Description Normal operation - UART _RX and UART _TX use separate pins. Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input. (See RSRC bit.) UART _RX pin is not used by UART . Doze Enable DOZEEN UART is enabled in Wait mode.
Page 626: Uart Control Register 2 (Uartx_C2)
Register definition 36.2.4 UART Control Register 2 (UARTx_C2) This register can be read or written at any time. Address: 4006_A000h base + 3h offset = 4006_A003h Read TCIE ILIE Write Reset UARTx_C2 field descriptions Field Description Transmit Interrupt Enable for TDRE Hardware interrupts from TDRE disabled;...
Page 627: Uart Status Register 1 (Uartx_S1)
Chapter 36 Universal Asynchronous Receiver/Transmitter (UART0) UARTx_C2 field descriptions (continued) Field Description This bit can be written to 1 to place the UART receiver in a standby state where it waits for automatic hardware detection of a selected wakeup condition. The wakeup condition is an idle line between messages, WAKE = 0, idle-line wakeup, or a logic 1 in the most significant data bit in a character, WAKE = 1, address-mark wakeup.
Page 628: Freescale Semiconductor, Inc
Register definition UARTx_S1 field descriptions (continued) Field Description Receive Data Register Full Flag RDRF RDRF becomes set whenever the receive data buffer is full. To clear RDRF, read the UART data register ( UART _D). Receive data buffer empty. Receive data buffer full. Idle Line Flag IDLE IDLE is set when the UART receive line becomes idle for a full character time after a period of activity.
Page 629: Uart Status Register 2 (Uartx_S2)
Chapter 36 Universal Asynchronous Receiver/Transmitter (UART0) UARTx_S1 field descriptions (continued) Field Description No parity error. Parity error. 36.2.6 UART Status Register 2 (UARTx_S2) This register contains one read-only status flag. When using an internal oscillator in a LIN system, it is necessary to raise the break detection threshold one bit time.
Page 630: Freescale Semiconductor, Inc
Register definition UARTx_S2 field descriptions (continued) Field Description LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. MSB (bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit depending on the setting of C1[M], C1[PE] and C4[M10].
Page 631: Uart Control Register 3 (Uartx_C3)
Chapter 36 Universal Asynchronous Receiver/Transmitter (UART0) 36.2.7 UART Control Register 3 (UARTx_C3) Address: 4006_A000h base + 6h offset = 4006_A006h Read R8T9 R9T8 TXDIR TXINV ORIE NEIE FEIE PEIE Write Reset UARTx_C3 field descriptions Field Description Receive Bit 8 / Transmit Bit 9 R8T9 When the UART is configured for 9-bit data (M = 1), R8 can be thought of as a ninth receive data bit to the left of the msb of the buffered data in the UART_D register.
Page 632: Uart Data Register (Uartx_D)
Register definition UARTx_C3 field descriptions (continued) Field Description OR interrupts disabled; use polling. Hardware interrupt requested when OR is set. Noise Error Interrupt Enable NEIE This bit enables the noise flag (NF) to generate hardware interrupt requests. NF interrupts disabled; use polling. Hardware interrupt requested when NF is set.
Page 633: Uart Match Address Registers 1 (Uartx_Ma1)
Chapter 36 Universal Asynchronous Receiver/Transmitter (UART0) UARTx_D field descriptions (continued) Field Description Read receive data buffer 4 or write transmit data buffer 4. R4T4 Read receive data buffer 3 or write transmit data buffer 3. R3T3 Read receive data buffer 2 or write transmit data buffer 2. R2T2 Read receive data buffer 1 or write transmit data buffer 1.
Page 634: Uart Match Address Registers 2 (Uartx_Ma2)
Register definition 36.2.10 UART Match Address Registers 2 (UARTx_MA2) The MA1 and MA2 registers are compared to input data addresses when the most significant bit is set and the associated C4[MAEN] bit is set. If a match occurs, the following data is transferred to the data register. If a match fails, the following data is discarded.
Page 635: Uart Control Register 5 (Uartx_C5)
Chapter 36 Universal Asynchronous Receiver/Transmitter (UART0) UARTx_C4 field descriptions (continued) Field Description 10-bit Mode select The M10 bit causes a tenth bit to be part of the serial transmission. This bit should only be changed when the transmitter and receiver are both disabled. Receiver and transmitter use 8-bit or 9-bit data characters.
Page 636: Functional Description
Functional description UARTx_C5 field descriptions (continued) Field Description Receiver samples input data using the rising edge of the baud rate clock. Receiver samples input data using the rising and falling edge of the baud rate clock. Resynchronization Disable RESYNCDIS When set, disables the resynchronization of the received data word when a data one followed by data zero transition is detected.
Page 637: Freescale Semiconductor, Inc
Chapter 36 Universal Asynchronous Receiver/Transmitter (UART0) The transmitter output (UART_TX) idle state defaults to logic high, C3[TXINV] is cleared following reset. The transmitter output is inverted by setting C3[TXINV]. The transmitter is enabled by setting the C2[TE] bit. This queues a preamble character that is one full character frame of the idle state.
Page 638: Receiver Functional Description
Functional description the transmit shifter, then write 0 and then write 1 to the UART_C2[TE] bit. This action queues an idle character to be sent as soon as the shifter is available. As long as the character in the shifter does not finish whileUART_C2[TE] is cleared, the UART transmitter never actually releases control of the UART_TX pin.
Page 639: Freescale Semiconductor, Inc
Chapter 36 Universal Asynchronous Receiver/Transmitter (UART0) status flag is set and the new data is lost. Because the UART receiver is double-buffered, the program has one full character time after UART_S1[RDRF] is set before the data in the receive data buffer must be read to avoid a receiver overrun. When a program detects that the receive data register is full (UART_S1[RDRF] = 1), it gets the data from the receive data register by reading UART_D.
Page 640: Freescale Semiconductor, Inc
Functional description In the case of a framing error, provided the received character was not a break character, the sampling logic that searches for a falling edge is filled with three logic 1 samples so that a new start bit can be detected almost immediately. 36.3.3.2 Receiver wakeup operation Receiver wakeup is a hardware mechanism that allows an UART receiver to ignore the characters in a message intended for a different UART receiver.
Page 641: Additional Uart Functions
Chapter 36 Universal Asynchronous Receiver/Transmitter (UART0) 36.3.3.2.2 Address-mark wakeup When wake is set, the receiver is configured for address-mark wakeup. In this mode, UART_C2[RWU] is cleared automatically when the receiver detects a logic 1 in the most significant bit of a received character. Address-mark wakeup allows messages to contain idle characters, but requires the msb be reserved for use in address frames.
Page 642: Freescale Semiconductor, Inc
Functional description 36.3.4.1 8-bit, 9-bit and 10-bit data modes The UART system, transmitter and receiver, can be configured to operate in 9-bit data mode by setting the UART_C1[M] or 10-bit data mode by setting UART_C4[M10]. In 9- bit mode, there is a ninth data bit to the left of the msb of the UART data register, in 10- bit mode there is a tenth data bit.
Page 643: Interrupts And Status Flags
Chapter 36 Universal Asynchronous Receiver/Transmitter (UART0) In single-wire mode, the UART_C3[TXDIR] bit controls the direction of serial data on the UART_TX pin. When UART_C3[TXDIR] is cleared, the UART_TX pin is an input to the UART receiver and the transmitter is temporarily disconnected from the UART_TX pin so an external device can send serial data to the receiver.
Page 644: Freescale Semiconductor, Inc
Functional description If the associated error was detected in the received character that caused UART_S1[RDRF] to be set, the error flags - noise flag (UART_S1[NF]), framing error (UART_S1[FE]), and parity error flag (UART_S1[PF]) - are set at the same time as UART_S1[RDRF].
Page 645: Introduction
Chapter 37 General-Purpose Input/Output (GPIO) 37.1 Introduction NOTE For the chip-specific implementation details of this module's instances see the chip configuration information. The general-purpose input and output (GPIO) module communicates to the processor core via a zero wait state interface for maximum pin performance. The GPIO registers support 8-bit, 16-bit or 32-bit accesses.
Page 646: Modes Of Operation
Introduction 37.1.2 Modes of operation The following table depicts different modes of operation and the behavior of the GPIO module in these modes. Table 37-1. Modes of operation Modes of operation Description The GPIO module operates normally. Wait The GPIO module operates normally. Stop The GPIO module is disabled.
Page 647: Memory Map And Register Definition
Chapter 37 General-Purpose Input/Output (GPIO) 37.1.3.1 Detailed signal description Table 37-3. GPIO interface-detailed signal descriptions Signal Description PORTA31–PORTA0 General-purpose input/output State meaning Asserted: The pin is logic 1. PORTB31–PORTB0 Deasserted: The pin is logic 0. Timing Assertion: When output, this signal occurs on the rising- edge of the system clock.
Page 648: Port Data Output Register (Gpiox_Pdor)
Memory map and register definition GPIO memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) 400F_F044 Port Set Output Register (GPIOB_PSOR) (always 0000_0000h 37.2.2/649 reads 0) 400F_F048 Port Clear Output Register (GPIOB_PCOR) (always 0000_0000h 37.2.3/649 reads 0)
Page 649: Kl04 Sub-Family Reference Manual, Rev. 3.1, November
Chapter 37 General-Purpose Input/Output (GPIO) 37.2.2 Port Set Output Register (GPIOx_PSOR) This register configures whether to set the fields of the PDOR. Address: Base address + 4h offset PTSO Reset GPIOx_PSOR field descriptions Field Description 31–0 Port Set Output PTSO Writing to this register will update the contents of the corresponding bit in the PDOR as follows: Corresponding bit in PDORn does not change.
Page 650: Port Toggle Output Register (Gpiox_Ptor)
Memory map and register definition 37.2.4 Port Toggle Output Register (GPIOx_PTOR) Address: Base address + Ch offset PTTO Reset GPIOx_PTOR field descriptions Field Description 31–0 Port Toggle Output PTTO Writing to this register will update the contents of the corresponding bit in the PDOR as follows: Corresponding bit in PDORn does not change.
Page 651: Port Data Direction Register (Gpiox_Pddr)
Chapter 37 General-Purpose Input/Output (GPIO) 37.2.6 Port Data Direction Register (GPIOx_PDDR) The PDDR configures the individual port pins for input or output. Address: Base address + 14h offset Reset GPIOx_PDDR field descriptions Field Description 31–0 Port Data Direction Configures individual port pins for input or output. Pin is configured as general-purpose input, for the GPIO function.
Page 652: Port Data Output Register (Fgpiox_Pdor)
FGPIO memory map and register definition FGPIO memory map (continued) Absolute Width Section/ address Register name Access Reset value (in bits) page (hex) F80F_F044 Port Set Output Register (FGPIOB_PSOR) (always 0000_0000h 37.3.2/652 reads 0) F80F_F048 Port Clear Output Register (FGPIOB_PCOR) (always 0000_0000h 37.3.3/653...
Page 653: Port Clear Output Register (Fgpiox_Pcor)
Chapter 37 General-Purpose Input/Output (GPIO) FGPIOx_PSOR field descriptions Field Description 31–0 Port Set Output PTSO Writing to this register will update the contents of the corresponding bit in the PDOR as follows: Corresponding bit in PDORn does not change. Corresponding bit in PDORn is set to logic 1. 37.3.3 Port Clear Output Register (FGPIOx_PCOR) This register configures whether to clear the fields of PDOR.
Page 654: Port Data Input Register (Fgpiox_Pdir)
FGPIO memory map and register definition FGPIOx_PTOR field descriptions (continued) Field Description Corresponding bit in PDORn does not change. Corresponding bit in PDORn is set to the inverse of its existing logic state. 37.3.5 Port Data Input Register (FGPIOx_PDIR) Address: Base address + 10h offset Reset FGPIOx_PDIR field descriptions Field...
Page 655: Functional Description
Chapter 37 General-Purpose Input/Output (GPIO) 37.4 Functional description 37.4.1 General-purpose input The logic state of each pin is available via the Port Data Input registers, provided the pin is configured for a digital function and the corresponding Port Control and Interrupt module is enabled.
Page 656: Kl04 Sub-Family Reference Manual, Rev. 3.1, November
Functional description During Compute Operation, the GPIO registers remain accessible via the IOPORT interface only. Since the clocks to the Port Control and Interrupt modules are disabled during Compute Operation, the Pin Data Input Registers do not update with the current state of the pins.
Page 657 Appendix A Revision History of this Document This appendix describes corrections to the this reference manual for convenience. Grammatical and formatting changes are not listed here unless the meaning of something changed. Changes between revisions 3.1 and 3 Table A-1. Changes between revisions 3.1 and 3 Chapter Description Chip Configuration...
Page 658: Freescale Semiconductor, Inc
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NXP Semiconductors MKL04Z8VFK4 Reference Manual

Chapter 1 About this Document

Chapter 2 Introduction

Chapter 3 Chip Configuration

Chapter 4 Alternate Non-Volatile IRC User Trim Description

Chapter 5 Clock Distribution

Chapter 6 Reset and Boot

Chapter 7 Power Management

Chapter 8 Security

Chapter 9 Debug

Chapter 10

Chapter 32

Chapter 12

Chapter 13

Chapter 14

Chapter 15 LLWU Signal Descriptions

Chapter 17

Chapter 18

Chapter 20 Arbitration

Chapter 33

Chapter 23

Chapter 24

Chapter 28

Chapter 25

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Summary of Contents for NXP Semiconductors MKL04Z8VFK4