MCGIRCLK
OSCERCLK
MCGPCLK
MCGIRCLK
OSCERCLK
MCGPCLK
Figure 5-8. LPUART0 and LPUART1 clock generation
5.7.9 FlexIO clocking
The FlexIO module has a selectable clock as shown in the following figure.
The chosen clock must remain enabled if the FlexIO is to
continue operating in all required low-power modes.
MCGIRCLK
OSCERCLK
MCGPCLK
Freescale Semiconductor, Inc.
NOTE
Figure 5-9. FlexIO clock generation
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Chapter 5 Clock Distribution
11
10
LPUART0 clock
01
SIM_SOPT2[LPUART0SRC]
11
10
LPUART1 clock
01
SIM_SOPT2[LPUART1SRC]
11
10
01
SIM_SOPT2[FLEXIOSRC]
FlexIO clock
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