Chip-Specific Pit Information; Pit/Dma Periodic Trigger Assignments; Pit/Adc Triggers; Pit/Tpm Triggers - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Chapter 30
Periodic Interrupt Timer (PIT)

30.1 Chip-specific PIT information

30.1.1 PIT/DMA periodic trigger assignments

The PIT generates periodic trigger events to the DMA channel mux as shown in this
table.
Table 30-1. PIT channel assignments for periodic DMA triggering
PIT channel
PIT Channel 0
PIT Channel 1

30.1.2 PIT/ADC triggers

PIT triggers are selected as ADCx trigger sources using the bits of
SIM_SOPT7[ADCxTRGSEL]. For more details, see the

30.1.3 PIT/TPM triggers

PIT triggers are selected as TPMx trigger sources using the TPMx_CONF[TRGSEL] bits
in the TPM module. For more details, refer to TPM chapter.
Freescale Semiconductor, Inc.
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
DMA channel number
DMA Channel 0
DMA Channel 1
SIM chapter.
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