Clock Definitions - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Table of Contents

Clock definitions

System oscillator

CG — Clock gate

Note1: See subsequent sections for details on where these clocks are used.

Note2: 48Mhz clock (IRC48M) control register is defined in either USB or MCG_Lite. In case USB is not

available, IRC48M will be controlled by IRC_TRIMs in MCG_Lite module

Note3: FCRDIV support divider ratio 1,2,4,8,16, 32, 64, 128. LIRC_DIV2 provides the futher divide

down for MCGIRCLK.

Note4: OSC32KCLK is only available when external crystal is in 30KHz - 40KHz range.

5.4 Clock definitions

The following table describes the clocks in the previous block diagram.

Platform clock

System clock

Counter logic

Figure 5-1. Clocking diagram

Table continues on the next page...

KL27 Sub-Family Reference Manual , Rev. 5, 01/2016

MCGOUTCLK divided by OUTDIV1

Clocks the ARM Cortex-M0+ core.

MCGOUTCLK divided by OUTDIV1

Clocks the crossbar switch and NVIC.

MCGOUTCLK divided by OUTDIV1

Clocks the bus masters directly .

Clock options for

some peripherals

Core/Platform/System clock

Bus/Flash clock

Clock options for

some peripherals

Freescale Semiconductor, Inc.