Clock Gating; Signal Multiplexing Constraints; Kl27 Signal Multiplexing And Pin Assignments - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Table of Contents

Table 10-1. Reference links to related information (continued)

10.2.1 Clock gating

The clock to the port control module can be gated on and off using the SCGC5[PORTx]

bits in the SIM module. These bits are cleared after any reset, which disables the clock to

the corresponding module to conserve power. Prior to initializing the corresponding

module, set SIM_SCGC5[PORTx] to enable the clock. Before turning off the clock,

make sure to disable the module. For more details, see the

1. A given peripheral function must be assigned to a maximum of one package pin. Do

not program the same function to more than one pin.

2. To ensure the best signal timing for a given peripheral's interface, choose the pins in

closest proximity to each other.

10.3 KL27 Signal Multiplexing and Pin Assignments

The following table shows the signals available on each pin and the locations of these

pins on the devices supported by this document. The Port Control Module is responsible

for selecting which ALT functionality is available on each pin.

VREFH can act as VREF_OUT when VREFV1 module is

It is prohibited to set VREFEN in 32 QFN pin package as 1.2 V

on-chip voltage is not available in this package.

Related module

Peripheral bus

KL27 Sub-Family Reference Manual , Rev. 5, 01/2016

Clock Distribution

Peripheral bridge

Clock distribution

Freescale Semiconductor, Inc.