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Field
3
Channel 3 Polarity
POL3
0
The channel polarity is active high.
1
The channel polarity is active low.
2
Channel 2 Polarity
POL2
0
The channel polarity is active high.
1
The channel polarity is active low.
1
Channel 1 Polarity
POL1
0
The channel polarity is active high.
1
The channel polarity is active low.
0
Channel 0 Polarity
POL0
0
The channel polarity is active high.
1
The channel polarity is active low.
29.4.8 Configuration (TPMx_CONF)
This register selects the behavior in debug and wait modes and the use of an external
global time base.
Address: Base address + 84h offset
Bit
31
30
29
0
R
W
Reset
0
0
0
Bit
15
14
13
R
W
Reset
0
0
0
Field
31–28
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
Freescale Semiconductor, Inc.
TPMx_POL field descriptions (continued)
28
27
26
25
TRGSEL
0
0
0
0
12
11
10
9
0
0
0
0
0
TPMx_CONF field descriptions
Table continues on the next page...
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Chapter 29 Timer/PWM Module (TPM)
Description
24
23
22
21
0
0
0
0
0
8
7
6
5
DBGMODE
0
0
0
0
Description
20
19
18
17
0
0
0
0
4
3
2
1
0
0
0
0
0
16
0
0
0
471
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