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NXP Semiconductors MPC5777C Manual

Clock calculator
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See also: Reference Manual
NXP Semiconductors
Application Notes
MPC5777C Clock Calculator Guide
How to use MPC5777C tool to easily calculate device
frequency domains
by: NXP Semiconductors

1. Introduction

NXP's MPC5777C is a dual-core 32-bit microcontroller
dedicated to high-performance powertrain applications.
The MCU supports ASIL-D automotive safety rating
and runs on two e200z7 Power Architecture cores. The
MPC5777C features two versions, a standard version
whose core runs up to 264 MHz and a performance
version that supports up to 300 MHz. This application
note will refer to these versions as
"MPC5777C_264MHz" and "MPC5777C_300MHz",
respectively, for version-specific information; general
content that applies to both versions will refer to the
device as simply "MPC5777C".
The MPC5777C supports an 8-44 MHz external
oscillator (XOSC), a 16 MHz internal RC oscillator
(IRC), and two phase locked loops (PLL).
MPC5777C_264MHz's two PLLs support 200 MHz
and 264 MHz, respectively; MPC5777C_300MHz's
respective PLLs can run up to 240 MHz and 300 MHz.
The IRC is selected out of reset so increasing the
operating frequency from 16 MHz requires additional
configuration. The MPC5777C Clock Calculator is
meant to complement the reference manual. It seeks to
simplify the clock configuration process by providing a
graphical, interactive tool to help the user find the
Document Number: AN12176
Contents
1.
Introduction ........................................................................ 1
2.
Clock calculator design ...................................................... 2
2.1.
Tree ......................................................................... 4
2.2.
Device Select .......................................................... 7
2.3.
Oscillator control .................................................... 8
2.4.
Peripheral domains ................................................. 8
2.5.
2.6.
LFAST clocking ................................................... 10
2.7.
PLLx ..................................................................... 12
2.8.
2.9.
Summary ............................................................... 13
2.10.
Limits .................................................................... 16
3.
PLL1 with MPC5777C_264MHz .................................... 17
3.1.
Select the Device .................................................. 18
3.2.
Configure PER_CLK ............................................ 19
3.3.
Observe the registers ............................................. 29
3.4.
Copy the code ....................................................... 30
4.
Conclusion ....................................................................... 30
5.
Revision History .............................................................. 30
Rev. 1 , 12/2018

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Summary of Contents for NXP Semiconductors MPC5777C

  • Page 1: Table Of Contents

    NXP Semiconductors Document Number: AN12176 Application Notes Rev. 1 , 12/2018 MPC5777C Clock Calculator Guide How to use MPC5777C tool to easily calculate device frequency domains Contents by: NXP Semiconductors Introduction ................ 1 Clock calculator design ............2 2.1. Tree ................. 4 1.

  • Page 2: Clock Calculator Design

    Macro Security. A popup window will appear. In it, select Enable all macros. Figure 1. Enable macros 2. Clock calculator design The MPC5777C clock calculator takes the form of an interactive Microsoft Excel spreadsheet organized into multiple tabs as shown in the following figure. Figure 2. MPC5777C Clock calculator setup Clock sources (e.g.
  • Page 3 Peripheral Domains will take the user to PER_CLK in Tree. Textboxes that are links, when hovered over, will cause the mouse cursor to turn into a hand icon and a pop-up to appear, showing the destination address, as shown in the following figure. MPC5777C Clock Calculator Guide, Rev. 1, 12/2018 NXP Semiconductors...

  • Page 4: Tree

    Tree is the centerpiece of the tool. This tab is the starting point for all clock frequency calculations. It is organized to resemble the MPC5777C clock tree as presented in the following figure. MPC5777C Clock Calculator Guide, Rev. 1, 12/2018...
  • Page 5 Clock calculator design Figure 5. MPC5777C Reference manual clock Tree shows, in part, the diagram’s clock tool counterpart. The difference between the two is that the Figure 6 latter is interactive. MPC5777C Clock Calculator Guide, Rev. 1, 12/2018 NXP Semiconductors...
  • Page 6 Figure 6. Clock calculator Tree The flow of the diagram generally goes from left to right. On the left are the MPC5777C clock sources and on the right are the clock domains. MCU modules run on one or more of these clock domains.

  • Page 7: Device Select

    This changes the hardware specification table used by the MPC5777C Clock Calculator. For example, if MPC5777C_300MHz is selected, PLL1_PHI will shade red starting at 300 MHz rather than 264 MHz. The structure of the tool remains unchanged, though, since the two MPC5777C versions share the same architecture, but with different operating speeds.

  • Page 8: Oscillator Control

    Figure 9. Oscillator control 2.4. Peripheral domains Peripheral Domains is an in-depth diagram of MPC5777C modules. Where Tree leaves off at the clock domain level, Peripheral Domains picks up and progresses to the module level, as shown in the figure below.

  • Page 9: Flexcan Clocking And Mcan Clocking

    Domains still hosts FlexCAN and MCAN blocks that show their input clocks and are hyperlinked to FlexCAN Clocking and MCAN Clocking, respectively, as shown in the below figure. MPC5777C Clock Calculator Guide, Rev. 1, 12/2018 NXP Semiconductors...

  • Page 10: Lfast Clocking

    LFAST clocking presents a block diagram of the module with various clocks going into it. It also supports LFAST_PLL configuration to increase the LFAST frequency up to 480 MHz. The LFAST also MPC5777C Clock Calculator Guide, Rev. 1, 12/2018 NXP Semiconductors...
  • Page 11 LFAST Input Filter block to become lfast_sys_clk, which in turn is the signal that gets fed into the LFAST PLL and phase generators, as shown in the following figure. Figure 14. LFAST clocking input filter MPC5777C Clock Calculator Guide, Rev. 1, 12/2018 NXP Semiconductors...

  • Page 12: Pllx

    Clock calculator design If RF_REF is 10 or 20 MHz, lfast_sys_clk is the same; otherwise, lfast_sys_clk is 0. MPC5777C does not actually filter RF_REF the way this tool does. The purpose of the LFAST Input Filter block is to simulate how the user can technically set RF_REF to any value, but the resulting LFAST output would be unusable.

  • Page 13: Summary

    Clock calculator design shaded in green; values that exceed the desired frequency, but are within MPC5777C hardware specifications are marked in yellow; and frequencies that exceed the MPC5777C hardware specification are colored red. Below is a screenshot of the reference table for PLL0_PHI.
  • Page 14 This table provides a place where all of them can be found. The table is organized by module, followed by the clock type (i.e. BIU clock, peripheral clock, protocol clock, etc.), and finally the frequency, as currently configured. Below is a screenshot of clock summary table. MPC5777C Clock Calculator Guide, Rev. 1, 12/2018 NXP Semiconductors...
  • Page 15 These functions can be copied and pasted to a source file via Ctrl+C/Ctrl+V or by clicking on the associated Copy Code button, if macros are enabled. The following figure shows Sysclk_Init and its Copy Code button. MPC5777C Clock Calculator Guide, Rev. 1, 12/2018 NXP Semiconductors...

  • Page 16: Limits

    Limits is the reference tab for all the color-coding and other rules. The values in its tables are based on the MPC5777C’s datasheet and reference manual and should not be modified by the user. The following figure is a screenshot of the Limits tab.

  • Page 17: Clock Tool Example Use Case: Configure Emios To 60 Mhz Pll1 With Mpc5777C_264Mhz

    3. Clock tool example use case: Configure eMIOS to 60 MHz PLL1 with MPC5777C_264MHz The following sections presents an example application of the MPC5777C Clock Calculator. This application note’s example will configure eMIOS0’s clocks to 60 MHz. The example will not only show the correct configurations but also how the tool responds if improper configurations are attempted.

  • Page 18: Select The Device

    3.1. Select the device First choose the correct the device. Go to Device Select and set the device to MPC5777C_264MHz. This ensures that the MPC5777C Clock Calculator will use the spec sheet corresponding to the 264 MHz variant. MPC5777C Clock Calculator Guide, Rev. 1, 12/2018...

  • Page 19: Configure Per_Clk

    Trace PER_CLK all the way back to its point of origin. As shown in the figure, PER_CLK is sourced from the 16 MHz CORE_CLK and divided by 2, hence 8 MHz. The cell is a drop-down menu and the MPC5777C Clock Calculator Guide, Rev. 1, 12/2018 NXP Semiconductors...
  • Page 20 7 MHz to the XOSC frequency cell. A dialog box appears notifying the user that the value is not accepted when he/she tries to click away from the cell. MPC5777C Clock Calculator Guide, Rev. 1, 12/2018 NXP Semiconductors...
  • Page 21 Figure 25. Invalid frequency input Set MPC5777C to DCF Client mode, oscillator range to High, and XOSC frequency to 40 MHz. Next, set the value of the XOSC Enable/Select block to 1 to select XTAL, the external oscillator, as shown in the following figure.
  • Page 22 Figure 28. PLL0 calculator Configure the dividers to achieve 200 MHz. The correct configuration can be achieved by trial and error, but the MPC5777C clock calculator provides a lookup table in the pll0_phi tab, as shown in the following figure.
  • Page 23 40 MHz and a PREDIV of 2. This example will use a MFD of 20 and a RFD of 2, but before configuring the PLL0 tab, it is worth noting what happens if the output PLL frequency is out of range. MPC5777C Clock Calculator Guide, Rev. 1, 12/2018 NXP Semiconductors...
  • Page 24 Also, set RFDPHI1 to 10 so that PLL0_PHI1 is 40 MHz. This output will be the source of PLL1. Figure 32. PLL0_PHI configured to 200 MHz Go back to Tree to observe that the PLL0_PHI frequency is now 200 MHz and PLL0_PHI1 is 40 MHz. MPC5777C Clock Calculator Guide, Rev. 1, 12/2018 NXP Semiconductors...
  • Page 25 There are three settings that achieve exactly 120 MHz. This example will use an MFD of 18 and an RFDPHI of 3. In the PLL1 tab, turn on the PLL and enter these settings much in the same manner as for PLL0, as seen in the following figure. MPC5777C Clock Calculator Guide, Rev. 1, 12/2018 NXP Semiconductors...
  • Page 26 MPC574xP, but its general principle can be extrapolated to the MPC5777C. Set the system clock divider to divide by 1 so that CORE_CLK is 120 MHz. There are multiple bitfield values that does the job. This example will use the MPC5777C’s reset value of 4. See the following figure.
  • Page 27 Figure 38. CORE_CLK selected as peripheral clock source Navigate down to PER_CLK and set its divider field to 0, which corresponds to a divide by 2. Hence PER_CLK has been configured to 60 MHz. MPC5777C Clock Calculator Guide, Rev. 1, 12/2018 NXP Semiconductors...
  • Page 28 Note that if a clock domain exceeds its hardware spec, the corresponding box will be shaded in red. As shown in the following figure, the max SD_CLK frequency is 16 MHz. Since 120 MHz, exceeds its limit, its cell is shaded red. MPC5777C Clock Calculator Guide, Rev. 1, 12/2018 NXP Semiconductors...

  • Page 29: Observe The Registers

    For example, the register SIU_LFCLKCFG would not have to be included, since the LFAST was untouched. Registers that would have to be written would be ones like PLLDIG_PLL0DV and SIU_SYSDIV. Figure 42. Register summary after configuration MPC5777C Clock Calculator Guide, Rev. 1, 12/2018 NXP Semiconductors...

  • Page 30: Copy The Code

    40 MHz external oscillator. 4. Conclusion This application note gives an overview of the MPC5777C interactive clock calculator. It seeks to simplify clock configurations in the form of a graphical tool so that a user can more easily visualize the device’s clock signals’...
  • Page 31 3. Added the following new sections: Device select Select the device 4. Updated Figure 15 5. Changed Section 3 heading to “Clock tool example use case: Configure eMIOS to 60 MHz PLL1 with MPC5777C_264MHz” MPC5777C Clock Calculator Guide, Rev. 1, 12/2018 NXP Semiconductors...
  • Page 32 Information in this document is provided solely to enable system and software How to Reach Us: implementers to use NXP products. There are no express or implied copyright licenses Home Page: granted hereunder to design or fabricate any integrated circuits based on the nxp.com information in this document.

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