Spi Peripheral - NXP Semiconductors MKL27Z128VFM4 Reference Manual

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No
Reached
No
maximum
retries?
Yes
Report a timeout
error (End)
No
Figure 13-18. Host reads response from target via I2C

13.4.2 SPI Peripheral

The Kinetis Bootloader in KLx3 ROM supports loading data into flash via the SPI
peripheral, where the SPI peripheral serves as a SPI slave.
Maximum supported baud rate of SPI depends on the clock configuration fields in the
Bootloader Configuration Area (BCA) shown in
rate is 400 kbps with the factory settings. The actual baud rate is lower or higher than 400
kbps, depending on the actual value of the clockFlags and clockDivider fields in the
BCA.
The SPI peripheral uses the following bus attributes:
• Clock Phase = 1 (Second Edge)
• Clock Polarity = 1 (Active Low)
Because the SPI peripheral in KLx3 ROM serves as a SPI slave device, each transfer
should be started by the host, and each outgoing packet should be fetched by the host.
The transfer on SPI is slightly different from I2C:
• Host will receive 1 byte after it sends out any byte.
• Received bytes should be ignored when host is sending out bytes to target
• Host starts reading bytes by sending 0x00s to target
• The byte 0x00 will be sent as response to host if target is under the following
conditions:
Freescale Semiconductor, Inc.
Fetch
Response
Read 1 byte
from target
0x5A
received?
Yes
Read 1 byte
from target
Read
payload length
0xA4
Yes
received?
part from target
(2 bytes)
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Chapter 13 Kinetis ROM Bootloader
End
Read
payload data
from target
Yes
Payload length
less than supported
length?
Read
CRC checksum
from target
(2 bytes)
Table
13-3. The typical supported baud
Set payload length
No
to maximum
supported length
211

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