Block Diagram; Modes Of Operation - NXP Semiconductors MKL27Z128VFM4 Reference Manual

• Array of 32-bit shift registers with transmit, receive and data match modes
• Double buffered shifter operation for continuous data transfer
• Shifter concatenation to support large transfer sizes
• Automatic start/stop bit generation
• Interrupt, DMA or polled transmit/receive operation
• Programmable baud rates independent of bus clock frequency, with support for
asynchronous operation during stop modes
• Highly flexible 16-bit timers with support for a variety of internal or external trigger,
reset, enable and disable conditions

39.2.3 Block Diagram

The following diagram gives a high-level overview of the configuration of FlexIO timers
and shifters.
Input
Selection
FXIO_Dn
in
External Triggers
Freescale Semiconductor, Inc.
SHIFTBUF0
31
SHIFTER0
SHIFTBUFi
31
SHIFTERi
Timer
Selection
TIMER0
Figure 39-1. FlexIO block diagram
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
0
Output
Selection
0
TIMERi
Chapter 39 FlexIO
FXIO_Dn
out/outen
747