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Field
5
10-bit Mode select
M10
Causes a tenth, non-memory mapped bit to be part of the serial transmission. This tenth bit is generated
and interpreted as a parity bit. If M10 is set, then both C1[M] and C1[PE] must also be set. This field must
be cleared when C7816[ISO7816E] is set/enabled.
See
Data format (non ISO-7816)
0
The parity bit is the ninth bit in the serial transmission.
1
The parity bit is the tenth bit in the serial transmission.
BRFA
Baud Rate Fine Adjust
This bit field is used to add more timing resolution to the average baud frequency, in increments of 1/32.
See
Baud rate generation
38.4.12 UART Control Register 5 (UARTx_C5)
Address: 4006_C000h base + Bh offset = 4006_C00Bh
Bit
7
Read
TDMAS
Write
Reset
0
Field
7
Transmitter DMA Select
TDMAS
Configures the transmit data register empty flag, S1[TDRE], to generate interrupt or DMA requests if
C2[TIE] is set.
NOTE:
0
If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request
interrupt service.
1
If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a
DMA transfer.
6
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
5
Receiver Full DMA Select
RDMAS
Configures the receiver data register full flag, S1[RDRF], to generate interrupt or DMA requests if C2[RIE]
is set.
NOTE: If C2[RIE] is cleared, and S1[RDRF] is set, the RDRF DMA and RDFR interrupt request signals
Freescale Semiconductor, Inc.
UARTx_C4 field descriptions (continued)
for more information.
for more information.
6
5
0
RDMAS
0
0
UARTx_C5 field descriptions
• If C2[TIE] is cleared, TDRE DMA and TDRE interrupt request signals are not asserted
when the TDRE flag is set, regardless of the state of TDMAS.
• If C2[TIE] and TDMAS are both set, then C2[TCIE] must be cleared, and D must not be
written unless a DMA request is being serviced.
are not asserted, regardless of the state of RDMAS.
Table continues on the next page...
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Chapter 38 Universal Asynchronous Receiver/Transmitter(UART)
Description
4
3
0
0
0
Description
2
1
0
0
0
0
0
695
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