Timer Configuration N Register (Flexio_Timcfgn) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Memory Map and Registers
Field
01 Dual 8-bit counters baud/bit mode.
10 Dual 8-bit counters PWM mode.
11 Single 16-bit counter mode.

39.3.18 Timer Configuration N Register (FLEXIO_TIMCFGn)

The options to enable or disable the timer using the Timer N-1 enable or disable are
reserved when N is evenly divisible by 4 (eg: Timer 0).
Address: 4005_F000h base + 480h offset + (4d × i), where i=0d to 3d
Bit 31 30 29
R
W
Reset 0 0 0
Bit 15 14 13
0
R
TIMDIS
W
Reset 0 0 0
Field
31–26 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
25–24 Timer Output
TIMOUT
Configures the initial state of the Timer Output and whether it is affected by the Timer reset.
00 Timer output is logic one when enabled and is not affected by timer reset
01 Timer output is logic zero when enabled and is not affected by timer reset
10 Timer output is logic one when enabled and on timer reset
11 Timer output is logic zero when enabled and on timer reset
23–22 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
21–20 Timer Decrement
TIMDEC
Configures the source of the Timer decrement and the source of the Shift clock.
00 Decrement counter on FlexIO clock, Shift clock equals Timer output.
01 Decrement counter on Trigger input (both edges), Shift clock equals Timer output.
764
FLEXIO_TIMCTLn field descriptions (continued)
28 27 26 25
0
TIMOUT
0 0 0 0
12 11 10 9
0
TIMENA
0 0 0 0
FLEXIO_TIMCFGn field descriptions
Table continues on the next page...
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Description
24 23 22 21
0
TIMDEC
0 0 0 0
8 7 6 5
0
TSTOP
0 0 0 0
Description
20 19 18 17
0
TIMRST
0 0 0 0
4 3 2 1
0
0 0 0 0
Freescale Semiconductor, Inc.
16
0
0
0
0