Lpuart Status Register (Lpuartx_Stat) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Register definition
Field
0 One stop bit.
1 Two stop bits.
SBR Baud Rate Modulo Divisor.
The 13 bits in SBR[12:0] set the modulo divide rate for the baud rate generator. When SBR is 1 - 8191,
the baud rate equals "baud clock / ((OSR+1) × SBR)". The 13-bit baud rate setting [SBR12:SBR0] must
only be updated when the transmitter and receiver are both disabled (LPUART_CTRL[RE] and
LPUART_CTRL[TE] are both 0).

37.3.2 LPUART Status Register (LPUARTx_STAT)

Address: Base address + 4h offset
Bit 31 30 29
R
w1c
w1c
W
Reset
0 0 0
15 14 13
Bit
R
w1c w1c
W
Reset 0 0 0
Field
31 LIN Break Detect Interrupt Flag
LBKDIF
LBKDIF is set when the LIN break detect circuitry is enabled and a LIN break character is detected.
LBKDIF is cleared by writing a 1 to it.
654
LPUARTx_BAUD field descriptions (continued)
28 27 26 25
0 0 0 0
12 11 10 9
0 0 0 0
LPUARTx_STAT field descriptions
Table continues on the next page...
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Description
24 23 22 21
RAF TC
0 1 1 0
8 7 6 5
0
0 0 0 0
Description
20 19 18 17
w1c w1c w1c w1c
0 0 0 0
4 3 2 1
0 0 0 0
Freescale Semiconductor, Inc.
16
w1c
0
0
0