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Clocking modes
When configured for PSTOP1, both the system clock and bus clock are gated. All bus
masters and bus slaves enter Stop mode, but the clock generators in the MCG and the on-
chip regulator in the PMC remain in Run (or VLP Run) mode. Exit from PSTOP1 can be
initiated by a reset or an asynchronous interrupt from a bus master or bus slave. If
configured, an asynchronous DMA request can also be used to exit Partial Stop for the
duration of a DMA transfer before the device is transitioned back into PSTOP1.
PSTOP1 is functionally similar to Stop mode, but offers faster wake-up at the expense of
higher power consumption. Another benefit is that it keeps all of the MCG clocks
enabled, which can be useful for some of the asynchronous peripherals that can remain
functional in Stop modes.
7.2.2 DMA Wakeup
The DMA can be configured to wake the device on a DMA request whenever it is placed
in Stop mode. The wake-up is configured per DMA channel and is supported in Compute
Operation, PSTOP, STOP, and VLPS low power modes.
When a DMA wake-up is detected in PSTOP, STOP or VLPS then the device will initiate
a normal exit from the low power mode. This can include restoring the on-chip regulator
and internal power switches, enabling the clock generators in the MCG, enabling the
system and bus clocks (but not the core clock) and negating the stop mode signal to the
bus masters and bus slaves. The only difference is that the CPU will remain in the low
power mode with the CPU clock disabled.
During Compute Operation, a DMA wake-up will initiate a normal exit from Compute
Operation. This includes enabling the clocks and negating the stop mode signal to the bus
masters and bus slaves. The core clock always remains enabled during Compute
Operation.
Since the DMA wakeup will enable the clocks and negate the stop mode signals to all bus
masters and slaves, software needs to ensure that bus masters and slaves that are not
involved with the DMA wake-up and transfer remain in a known state. That can be
accomplished by disabling the modules before entry into the low power mode or by
setting the Doze enable bit in selected modules.
Once the DMA request that initiated the wake-up negates and the DMA completes the
current transfer, the device will transition back to the original low-power mode. This
includes requesting all non-CPU bus masters to enter Stop mode and then requesting bus
slaves to enter Stop mode. In STOP and VLPS modes the MCG and PMC would then
also enter their appropriate modes.
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
90
Freescale Semiconductor, Inc.
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